JPS6324173A - Fault detection system for integrated circuit - Google Patents

Abstract

PURPOSE:To output the influence of fault to an external output terminal by providing proper initial value of '0' or '1' to a storage element which in not capable of deciding output value and propagating a combination of the proper inititial value with output value of '0' and the combination of the proper initial value with output value of '1' to the external output terminal. CONSTITUTION:An assigning means 4 for proper initial value assigns the proper initial value Xi to an output fault signal value of the storage element 1 which is not capable of deciding output signal in the fault circuit. A generative means 5 for an input pattern series finds an input pattern series in order to obtain the fact that the signal value in a normal circuit of a signal line having a fault becomes a reverse signal to degenerate value of the fault. A generative means 7 for a propagation input pattern series finds an input pattern series in order to propagate the influence of a fault up to an external output terminal from the signal line having the fault. Thus finding is concluded to be successful when finding is enabled to find pattern series, but unsuccessful when finding is not enabled to find pattern series.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention propagates the influence of a stuck-at fault assumed inside an integrated circuit to an external input terminal of the integrated circuit by transmitting an input pattern sequence that is output to an external output terminal. The present invention relates to an integrated circuit failure detection method for detecting failures in integrated circuits.

[Conventional technology]

As the density of semiconductor integrated circuits (LSI) increases, it is becoming increasingly difficult to determine whether the LSI is a good product. To test an LSI, an input pattern is applied to an external input terminal, and a determination is made based on whether the pattern appearing at the external output terminal matches an expected value. Since the LSI is a sequential circuit in terms of -C, the expected value is not uniquely determined for one input pattern, but is influenced by the past input pattern series. For such an LSI, it is extremely difficult to obtain a cover turn sequence so that the effects of all possible stuck-at faults inside the LSr appear on the external output terminal.

Figure 19 shows an example of such a stuck-at fault with M, A,
This shows a case where the signal value of the signal line of the N0 circuit is fixed to a signal value of 0 due to a failure.

When the signal value of a signal line is fixed at a certain value in this way, it is called a stuck-at fault. A fault where the signal value is fixed at O is called a stuck-at-0 fault, and a fault where the signal value is fixed at 1 is called 1.
This is called a stuck-at fault.

By the way, in detecting a failure in an LSI, signal values as shown in Fig. 20 are used, and when the signal value of a certain signal line is fixed at the failure signal value due to a failure, the signal value when that signal value is normal is used. The normal signal value and the fault signal value are combined and expressed as a normal signal value/failure signal value.

For example, when a certain signal line is fixed at a signal value of 0 due to a stuck-at-0 fault, the fixed signal value O and the signal value 1 when normal are combined and expressed as Ilo.

By the way, the automatic generation of the input pattern sequence is as described above.
The objective is to create an input pattern series in which all the effects of a stuck-at fault assumed inside the SI appear at the external output terminal.

This example will be explained according to FIG. For example, as shown in Figure 21, if there is a stuck-at-0 fault in signal line B, there will be a fault in the signal line B connected to the external input terminal, and signal values 0 and 1 will be applied to A and B, respectively.
．． When 1 is input, a signal value of 1 is output to the signal line t due to the shadow U of the stuck-at-0 fault.

Ru. However, if signal line B is not faulty, signal value O should be output to signal line C, so this is expressed as 0/1, and the effect of the O stuck-at fault is propagated to the external output terminal connected to signal line E. The goal is to make sure that

Automatic generation of the input pattern series determines the signal value to be applied to the external input terminal so that the effect of the failure of the signal line B appears on the external output terminal.

By the way, LSI is an AND circuit, 68 circuits.

In the case of a combinational circuit consisting of only a combination of N million T circuits, there is a pairwise correspondence between the cover turn input to the external input terminal and the output cover turn output to the external output terminal, so it is difficult to detect a failure in the LSI. It's relatively easy. However, actual LSIs are usually constructed from so-called sequential circuits that include memory elements such as U-nochi circuits, and the output pattern is influenced by the input pattern series input in the past. Since there is no one-to-one correspondence with the cover turns, it is not easy to detect the failure.

FIG. 22 takes the D latch circuit as an example to explain the difficulty in detecting a fault in the sequential circuit. If the signal line E of the D latch circuit has a stuck-at-0 fault, the signal line of the D latch circuit It can be any signal value of Q′h<0 or 1, and the signal line Q
This shows that the value of is not determined.

By the way, one of the methods (design for testability) to facilitate the automatic generation of test data for sequential circuits is as follows.
There is a scan path method (Japanese Patent Publication No. 54-23213). This constructs a scan canvas by adding a shift register function to all memory elements in a logic circuit and connecting them all in series to form one shift register. By doing so, during a test operation, the scan path can be used to set signal values in the storage element and read signal values, thereby greatly improving the controllability and observability inside the logic circuit.

In addition, the parts other than the scan canvas can be regarded as a combinational circuit, and since there is no memory element in a combinational circuit, the output is uniquely determined according to the input.1. A method for automatically generating cover turn sequences for combinational logic circuits can be applied.

[Problem that the invention seeks to solve]

However, in the testability design described above, the number of constituent gates increases because the shift register function is added to all memory elements, and the addition of 11 control circuits reduces the operating speed of the logic circuit. This has the disadvantage of increasing the number of terminals and external output terminals. Therefore, if the testability design described above is applied to a circuit including many memory elements, the number of gates will increase significantly, making it impractical.

Therefore, a method for automatically generating input pattern sequences for logic circuits including memory elements is needed. After converting to , there was a problem that one had to rely on automatic generation method of human cover turn series for combinational circuits.

This invention was made to solve the above problems, and even when the output signal value is not determined due to a failure in the signal line, such as in a memory element, it does not rely on the scan canvas method described above, that is, it uses external input. The objective is to obtain a fault detection method that propagates the effects of faults to external output terminals without increasing the number of terminals or data.

[Means for solving problems]

Therefore, the present invention provides unique initial value assignment means 4 that assigns a unique initial value of 0 or 1 to the output value of each storage element whose output value cannot be determined due to the influence of a failure, and a unique initial value assigned by unique initial value assignment means 4. The combination of the initial value and the output value O when the memory element is assumed to be normal, and the combination of the above specific initial value and the output value 1 when the memory element is assumed to be normal, are propagated as they are to the external output terminal. A propagation type cover turn sequence generation means 7 for generating a cover turn sequence for detecting a failure in an integrated circuit by detecting either of the above two combinations propagated to an external output terminal as an influence of a failure. This is a characteristic feature.

[Effect]

In this invention, a unique initial value is assigned to each failure signal value of the output of each storage element whose output signal value cannot be determined due to the influence of a failure, and a normal signal value 0 and a unique initial value, and a normal signal value 1 and a unique initial value are assigned. A propagation type cover turn series in which the combination of both propagates to the external output terminal is input from the external input terminal.

Since the propagation type cover turn series manually input from the external input terminal propagates the combination of the normal signal value O and the unique initial value, and the combination of both the normal signal value 1 and the unique initial value, to the external output terminal,
Either of the two combinations will represent the effect of a fault, and whether the unique initial value is a signal value of 0 or 1, the effect of the fault can be observed at the external output terminal, and the fault can be detected. Can be detected.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the failure detection method of the present invention.
In the figure, 1 is initial value setting means for initializing the signal values of the signal lines of all the elements constituting the LSI to an undefined value X;
Reference numeral 2 denotes a consensus operation means for performing a consensus operation between the output of an element whose signal value is determined by a failure and the signal value of a signal line, 3 a failure storage element detection means for detecting a storage element with a failure, and 4 a failure storage element detection means 3. Unique initial value assignment means 5 assigns a unique initial value Xi to the failure signal value of a storage element with a failure detected by 5; 6 is an input pattern sequence generating means for generating an input pattern sequence so that the opposite signal value is output to the signal line; 6 is an input pattern for determining whether the input pattern sequence has been generated by the input pattern sequence generating means 5; The sequence generation determination means 7 is a propagation type cover turn sequence that generates a propagation type cover turn sequence for propagating the combination of normal signal value/defective λ signal value to an external output terminal when the input cover turn sequence is generated. A generation means 8 is a propagation type coverturn sequence generation determination means for determining whether or not a propagation type coverturn sequence has been generated; 9 is a signal value of the propagation type input pattern sequence generated when the propagation type coverturn sequence is generated; This is a signal value conversion means that converts the clock pulse into a clock pulse input to an external input terminal.

Further, FIG. 2 shows signal values handled in the automatic input pattern generation method for a logic circuit to which the present invention is applied. Xi
and Xi are signal values newly introduced in the present invention, and the storage element i whose output signal value cannot be determined due to a failure
FIG. 3 is a table showing unique initial values of . These Xi and Xi are signal values that appear only in the faulty circuit, and are a type of indefinite value, but in this invention, they are signal values unique to the memory element i, so they are 3, which corresponds to the signal values 0 and 1. be treated as such.

FIG. 3 shows the combination of signal values shown in FIG. 2 in a normal circuit and a faulty circuit. In FIG. 3, the circles indicate combinations in which the normal signal value and the failure signal value are different, and hereinafter this combination will be referred to as the influence of the failure. Furthermore, in Fig. 3, the × mark indicates a combination in which the normal signal value and the failure signal value match, the Δ mark indicates a combination including an indefinite value, and the ○ mark indicates a combination that includes an undefined value.
This is a possible combination that could result in either a mark or an X mark. The automatic test data generation method for logic circuits according to the present invention handles the combinations of signal values shown in FIG. In addition, the following method of expressing signal values is normal signal value/
For example, the signal value of a normal circuit is O1, and the signal value of a faulty circuit is O/1.

Fig. 4 is a table showing the truth value of the two-man-powered AND gate when handling the signal values in Fig. 2, Fig. 5 is a table showing the truth value of the two-man-power OR gate, and Fig. 6 is the truth value of the NOT gate. FIG. 7 is a table showing the truth values of the D latch.

Next, the operation of the present invention will be explained with reference to FIG.

FIG. 8 shows the flow of an automatic input pattern generation method for a logic circuit according to the present invention. In FIG. 8, the initial value setting means I initializes the output signal values of all elements in the normal circuit and the faulty circuit, the signal values of the signal lines, and the signal values of the external input terminal and external output terminal to an undefined value X ( Step Fl).

Further, the agreement operation means 2 determines the output of the element whose signal value is determined by the failure in the faulty circuit and the signal value of the signal line (step F2). The faulty memory element detection means 3 determines whether there is a memory element in the faulty circuit whose output signal value cannot be determined because no clock is input to the clock input terminal due to a fault, and if there is, the process proceeds to step F4; if not, the process proceeds to step F5. (Step F3). The unique initial value allocating means 4 allocates a unique initial value Xi to the output failure signal value of the storage element i whose output signal value cannot be determined in the failure circuit (step F4). The input pattern sequence generation means 5 sets the signal value of the signal line in which the fault exists in a normal circuit to a signal value opposite to the stuck-at value of the fault, that is, the signal line in which the stuck-at-at-zero fault exists has a normal signal value of 1, 1. An input pattern sequence is determined so that a normal signal value of 0 is obtained for a signal line in which a stuck-at fault exists (step F5). If the input pattern sequence generation means 5 has determined the human cover turn sequence, the input pattern sequence generation determination means 6 proceeds to step F7; if not, the input pattern sequence generation determination means 6 proceeds to step FIO (step F6).
. The propagation cover pattern sequence generating means 7 obtains an input pattern sequence so that the influence of the fault propagates from the signal line where the fault exists to the external output terminal (step F7). The propagation-type coverturn sequence generation determination means 8 proceeds to step F9 if the propagation-type coverturn sequence generation means 7 has found the propagation-type coverturn sequence, and if not, proceeds to step FIO (step F8). The signal value conversion means 9 performs step F.
Since the input pattern series obtained in Steps 5 and F7 is an input test pattern for detecting a failure, the signal value of the external clock input terminal is converted into an actual signal value, and the test data generation is deemed successful and ends. Here, conversion to an actual signal value means, as shown in Figure 9, if the clock to be input to the external clock input terminal is a positive pulse, if the generated signal value is 1, a positive pulse is input. , when the generated signal value is 0, no positive pulse is input, and if the clock to be input to the external clock input terminal is a negative pulse, when the generated signal value is 0, a negative pulse is input, When the generated signal value is 1, conversion is performed so that no negative pulse is input. Further, since an input pattern for detecting a failure was not found in step F10, the input pattern generation is deemed to have failed and is terminated.

10, 11, 12, and 13 are applied to the case where the signal value of a certain signal line is set to the target signal value in order to cause the effect of a failure in step F5 in FIG. This table shows the rules to follow. Figure 10 is 2
In the case of a human-powered A N D gate, when the signal value of this output is set to the target signal value 1, the next target signal value becomes the target signal value 1 in all the human-powered signal lines, and the signal value of this output is set to the target signal value 1. When the signal value is set to O, the next target signal value becomes the target signal value 0 on any one input signal line. Figure 11 shows the case of a two-manpower δR gate, and when the signal value of this output is set to the target signal (l!0), the next target signal value becomes the target signal value 0 in all the human-power signal lines, and this output When the signal value of is set to the target signal value 1, the next target signal value becomes the target signal value 1 on any one input signal line.Figure 12 shows the case of a NOT gate, and the signal value of this output is When the target signal value is 1, the next target signal value is the target signal value O1 on the input signal line.When this output signal value is the target signal value 0, the next target signal value is the target signal value 1 on the input signal line. Figure 13 shows the case of D latch, and when the signal value of this output is the target signal value O (or 1), the next target signal value will be the target signal value on the data input (D input) signal line. 0 (or l) and clock input (E input)
The target signal value is 1 on the signal line of the clock input (E input), or the target signal value is 0 on the signal line of the clock input (E input), and the target signal value is O (or 1) on the signal line of the output of the D latch one cycle before. Become. Step F5 in Figure 8
10, 11, 12 and 13.
By sequentially applying the rules shown in the figure from the signal line where the fault exists to the external input terminal, an input pattern series that causes the effect of the fault is determined. Figure 14 shows the first
Figure 0.

This shows an example in which the rules shown in FIGS. 11, 12, and 13 are applied one after another to determine an input pattern sequence that causes the effect of a failure.

For the signal line where the O stuck-at fault has occurred in this way,
A signal value input to an external input terminal is determined such that a signal value of 1 is output when the signal line is normal.

15, 16, and 17 show the target signal line selected in step F7 in FIG. 8 to propagate the effect of the fault to the output of the element when the effect of the fault propagates to the input of the element. and the rules for the target signal value. 1st
Figure 5 shows the case where the influence of a failure propagates to the input of an AND gate. By setting the other inputs of that AND gate to the target signal line and reducing each target signal value to 1/1, the influence of the failure is transmitted to the input of the AND gate. propagates from input to output.

Figure 16 shows the case where the influence of the failure is propagated to the input of the 6R gate.By setting the other input of that OR gate to the target signal line and setting each target signal value to Olo, the influence of the failure is transmitted to the input of the OR gate. Propagates from input to output. Figure 17 (
In a), the influence of the failure is propagated to the D input of the D latch. By setting the E input as the target signal line and setting the target signal value to 1/1, the influence of the failure is propagated to the output of the D latch. 1st
Figure 7 (b) shows the shadow of failure in the D-latch with 8 human power of 90/l.
＜In the normal circuit, the clock is not input, but in the faulty circuit, the clock is input）is propagated, and the signal line of the output of the D latch is set as the target signal line one cycle before the cycle in which the influence of the failure is propagated, and the target signal value is set as the target signal line. 010 (or 1/1
), and by setting the target signal value 1/1 (or 010) to the target signal line input in the period in which the influence of the failure propagated, the output signal value of the D latch in the period in which the influence of the failure propagated is set to the normal circuit. Since the clock does not enter in the circuit, the signal value becomes 0 (or 1), and in the faulty circuit, the clock enters, so the signal value becomes 1 (or 0), and the effect of the fault becomes 0/1 (or 110), and the D latch Propagate to output. Figure 17 (C1 shows the case where the influence of a failure I10 (a clock is input in a normal circuit, but no clock is input in a failure circuit) is propagated to the E input of the D launch, and in the failure circuit, the output signal value of the D latch is In this case, the output of this D latch i has been given a unique initial value Xi in advance in step F4 in FIG. value 0
/X (or 1 / Therefore, the output of D latch i is 0/Xi (or 1/Xi) in the period in which the fault propagated, and in the next period in which the fault propagated! /Xi (or O/Xi) failure and propagates. If the effects of these two failures are both propagated to the external output terminal, in the actual circuit, whether Xi is a signal value of O or 1, one of them will be affected by the failure, and it will be observed at the external output terminal. can. In step F7 in FIG. 8, the rules shown in FIGS. 15, 16, and 17 for propagating the influence of the fault, and the rules shown in FIGS.
The rules shown in Figures 1, 12, and 13 are applied one after another from the signal line where the fault exists to the external output terminal, thereby creating an input pattern series that propagates the effects of the fault to the external output terminal. is found. Figure 18 shows Figure 10,
An example in which the rules shown in Figures 11, 12, 13, 15, 16, and 17 are applied one after another, and an input pattern sequence that propagates the effects of a failure to an external output terminal is determined. It is. In this example, the output signal value of D latch 3 cannot be determined due to a failure in the faulty circuit, but the specific initial values X and l of D latch 3 are either signal values O or 1 in the actual circuit. Since either 0/X3 or 1/Xz propagated to the external output terminal will definitely be affected by a fault, this fault can always be detected at the external output terminal using the input test pattern series determined here.

In addition, although the case where this invention was applied to a D latch was demonstrated in the said Example, it is clear that this can be applied to a memory element other than a D latch. Further, although the above embodiments are implemented using software, it is also possible to implement this system using a hardware device.

〔Effect of the invention〕

As explained above, the present invention allows the output value of each storage element whose output value cannot be determined due to the influence of a failure to be 0 or 1.
a combination of the unique initial value assigned by the unique initial value allocating means and an output value 0 when the storage element is normal, and the unique initial value and the storage element; and a propagation input pattern sequence generation means for generating an input pattern sequence that propagates the combination with the output value 1 when it is assumed that the output value is normal to the external output terminal as it is, and the above-mentioned two sets propagated to the external output terminal. Since the system is configured to detect failures in the integrated circuit by considering any one of them as the effects of a failure, it is possible to propagate the effects of failures to external output terminals without increasing the number of external output terminals or gates. This has the effect of ensuring a high failure detection rate.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a table of signal values handled in the automatic test data generation method for logic circuits of the present invention, and Figure 3 is a diagram of normal signal values and fault signal values. A table showing the combinations, Figure 4 is a table showing the truth value of a two-man AND gate, Fig. 5 is a table showing the truth value of a two-man OR gate, and Fig. 6 is a table showing the truth value of a NOT gate. Figure 7 is a table showing the truth value of the D latch, Figure 8 is a diagram showing the flow of the operation of the present invention, and Figure 9 is a conversion table for converting input signal values into actual signal values. Front door, 1st
Figure 0 shows the rules for obtaining the next target signal value from the target signal value on the output signal line of a two-man powered AND gate, and Figure 11 shows the rules for obtaining the next target signal value from the target signal value on the output signal line of a two-man powered OR gate. Figure 12 is a diagram showing the rules for obtaining the target signal value. Figure 12 is a diagram showing the rules for acquiring the next target signal value from the target signal value of the NOT gate output signal line. Figure 13 is the D latch output signal. A diagram showing the rules for obtaining the next target signal value from the target signal value of the line. Figure 14 is an example of finding an input pattern sequence that causes the effect of a fault. Figure 15 shows an example of how the input pattern of an AND gate is affected by a fault. Figure 16 is a diagram showing the rules for obtaining the next target signal value when the signal propagates, and Figure 17 is a diagram showing the rules for obtaining the next target signal value when the influence of a fault propagates to the ○R agate input. Figure 18 shows the rules for obtaining the next target signal value when the influence of a fault propagates to the input of the D latch, and Figure 18 shows an example of finding an input pattern sequence that propagates the influence of a failure to the external output terminal. Fig. 19 is a diagram showing an example of a stuck-at fault, Fig. 20 is a table showing signal values handled in conventional logic simulation, and Fig. 21 is a diagram showing a conventional fault detection method. FIG. 22 is a diagram showing that in the conventional art, the output of the D latch cannot be determined due to a failure. 1... Initial value setting means, 2... Agreement operation means, 3.
. . . Faulty storage element detection means, 4. Unique initial value assignment means, 5. Input pattern sequence generation means, 6. Input Kabakoon sequence generation determination means, 7. Propagation input pattern sequence generation means, 8... Propagation input pattern series generation determination means, 9... Signal value conversion means. Agent Masuo Oiwa (and 2 others) Figure 2 Figure 3 Figure 8 〇, X's Hee 5 and 1 Teshi rJ Possible 1 υ゛ Island Otsu Figure 4 (α) Imo 4 O b) 1 Dan Li Ki1 v5 Figure 7 Figure 82 Figure 9 ￥10 figure (phantom (b) Also 1; Figure 11 (α) (b) 5ta lJ Figure 12 (σ・)
(b)■;J white quill number IA Fig. 13 (a) Fig. 13 (b) ■IJ eye qt number 14,000 Fig. ro 1.7 r Moon blindness 51 Mutual man 15 Effect of failure (125/1.1/Φヱヂ゛) Figure 17 (a) Figure 17 (b) Figure 17 (C) 口) ま 8 目次への訳 f 訳 fig. 18 (久) 口 1; Word No. 11

Claims (1)

[Claims] A fault in the integrated circuit is detected by inputting to an external input terminal of the integrated circuit an input pattern sequence that propagates the influence of a stuck-at fault assumed inside the integrated circuit to an external output terminal of the integrated circuit. In a fault detection method for integrated circuits, a unique initial value assigning means assigns a unique initial value of 0 or 1 to the output value of each storage element whose output value cannot be determined due to the influence of the failure, and a unique initial value assigned by the unique initial value assigning means is provided. The combination of the initial value and the output value 0 when the memory element is assumed to be normal, and the combination of the above specific initial value and the output value 1 when the memory element is assumed to be normal, are propagated as they are to the external output terminal. a propagation input pattern sequence generating means for generating an input pattern sequence, and detects a failure in the integrated circuit by detecting either of the above two combinations propagated to the external output terminal as an influence of the failure. A fault detection method for integrated circuits.