JPS63240182A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To facilitate real-time image processing by storing charges from a photoelectric converting element in respective storage parts (frame memory) provided opposite vertical charge transfer meas respectively. CONSTITUTION:A signal from a photodiode 1 which is stored in a storage time T1 is transferred to a vertical CCD 2 with pulses (P1) and then signal charges are transferred to the storage parts 13 at high speed with a pulse train P2). A signal stored in a storage time T2, on the other hand, is also transferred to the storage parts 13 at high speed. Here, the T1 and T2 are shorter than one field. The signals transferred to the storage parts 3 and 13 are transferred in order to horizontal CCD registers 4 in a vertical scanning period, inputted to a signal processing circuit 7 through output amplifiers 5 and 15 and output lines 6 and 16, and processed as specified, so that the result is outputted to an output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device suitable for five-image signal processing.

[Conventional technology]

Figure 2 shows FIT, which is one of the conventional solid-state imaging devices.
(Flame engineering transfer
) type CCD @ image element configuration The FIT type COD reads out the signal charge accumulated in the photodiode 1 to the vertical CCD 2 within the vertical blanking period and transfers it to the storage section 3 at high speed. do.

Then, during the video period, the signal is outputted from the storage section 3 as a video signal from the output section 5 through the horizontal CCD 4.

Compared to other imaging methods, this F.E.T. has the great advantage of significantly reducing the occurrence of smear, a false signal peculiar to solid-state imaging devices.

Such a FIT-type COD device is described in detail in ``rFIT-CCD Image Pickup Device'' on page 36 of the 198th TV Society.

[Problem that the invention seeks to solve]

The above-mentioned solid-state image sensor has characteristics preferable as an image sensor for a normal video camera.

Image processing, especially moving image processing functions and electronic shutter functions, were not considered.

An object of the present invention is to provide a solid-state imaging device suitable for image processing.

[Means for solving problems]

The above purpose is to provide a plurality of storage sections (frame memories) opposite to each of the vertical charge transfer means that receives and receives signal charges from a photoelectric conversion element and transfers them in the vertical direction, and each of these storage sections This is achieved by separately storing signal charges with different accumulation times.

[Effect]

Since the signal charges stored in each of the multiple storage units (frame memories) of the imaging device have different storage times, simultaneous output allows image processing such as extraction of time-varying components of image information in real time. can be easily done.

〔Example〕

Below, one embodiment of the present invention will be explained with reference to FIG. 1. In FIG.
03 is a collection area of the storage section 3.

4 is a horizontal charge-coupled device (horizontal COD register), 5 is an output amplifier, and information for one screen is stored in area 103. Furthermore, the storage area 1 which is the gathering area of the storage unit 13
13 and horizontal charge coupled device (horizontal CCD register) 1
4 and an output amplifier 15, information for another screen can be stored in the storage area 113. Both of these screen information are processed by a signal processing circuit 7 via output lines 6 and 16. Then, the processed information is outputted from the output terminal 8, indicating the operation of this embodiment.

This will be explained in detail using the timing diagram shown in Figure 3.
First, the signal accumulated during the accumulation time T1 is . Pulse P
1 to the vertical CCD 2 (Vcpz→2 is “
The signal charge of the vertical CCD 2 is transferred from the vertical C0D2 to the storage section 3 at high speed by the pulse train Pi (when Vcpz→3 is at the "H" level), while the signal charge is accumulated during the W integration time Tx. The signal is also transferred to the vertical VLC1)D2 by the pulse P8 (when Vcpz→2 is at "H" level), and then from the vertical C0D2 to the horizontal COD register 1.
4 to the storage section 13 at high speed (when Vcpz→engine δ is at "H" level). Here, the storage period Tt and the size of Tz are such that the sum of T1 and T2 is one field. As long as it is less than 1 hour. The signals that have been completely transferred to the W edges 3 and 13 are those that have been accumulated during the respective accumulation times T1 and Tz. These storage parts 3 and 1
The signal transferred to 3 is.

During the vertical scanning period, data is sequentially transferred to horizontal COD registers 4 and 14 (Vaps → number and Vcpta → 14 are set to H).
When the signal is at level, it is outputted via output amplifiers 5 and 15 and output lines 6 and 16. Output signals outputted via outputs IIA6 and 16 (Vsigs and Vgtg
ze) is subjected to predetermined processing by the signal processing circuit 7,
The resulting output is output to the output terminal 8.

Next, a specific example of the signal processing circuit 7 will be explained. First, the output of the output terminal 8, v8, is as follows, assuming that the signals of the input terminals 6 and 16 are Vs□B and V□118, respectively.
It can be expressed as ze − (1). Here C1, cz
is any positive or negative constant. Especially CZ・T t
If the condition +C x·Tz=0 is satisfied, moving image components at the accumulation times TI and T2 appear in the output v6.

In FIG. 4(a), which shows the signal processing circuit 7 shown in the above equation (1), 41 and 42 are amplifiers with gains of Ct and Cz, respectively, and 43 is an adder.

Figure 4(b) shows the configuration of Figure 4(a), level determination @4
4.a Ox which is the one with switch 45.46 added
, Cx satisfy the condition of Cx・Tx+Cx・Tx=0, the output of the adder 43 becomes the signal Vs□6
The larger the difference between and V s i & 18, the thicker it becomes.
Can judge videos. In particular, when capturing images of high-speed moving objects, an image signal with a short accumulation time is used for the image of the moving object, and an image signal with a long accumulation time is used for the still image of the background. Can be done. Also,
The signal processing circuit 7 shown in FIG. 1 may be omitted, and the signals may simply be output in parallel via the output lines 6.about.16.

FIG. 5 shows another embodiment of the present invention.
This is an embodiment in which coupling parts 51 to 54 are added to the embodiment shown in the figure, and an imaging part 101. @Stacking part 103゜113, horizontal CC
This is to ensure the respective transfer between DCD Lettuce 5.14.

FIG. 6 shows another embodiment of the present invention.
The arrangement of the storage section 113 and the horizontal COD register section 14 is different from the embodiment shown, but the functions are the same.

FIG. 7 shows another embodiment of the invention. This embodiment has a signal return path added to the embodiment shown in FIG. Wiring 71
feeds back the output from the processing circuit 7 to the charge input circuit 72 of the horizontal CCD 14. The signal fed back to the horizontal CCD 14 may be stored in the storage section 113 and read out repeatedly, or the feedback signal may be transferred to the photoelectric conversion section 101 side and added to the newly stored signal to convert the S/S of the signal. N
You can increase the ratio.

FIG. 8 shows another embodiment of the present invention, and FIG.
A charge sweep region 81 and a coupling portion 82 are provided in the embodiment shown in the figure. After the dark current generated in the vertical CCD section of the photoelectric conversion section 101 is transferred to the sweep region 81 at high speed, normal signals can be transferred to the storage region sections 103 and 113.

FIG. 9 shows another embodiment of the present invention, which is basically the same as FIG. 1. The difference between the two is the storage section 10.
3 and 113 are arranged alternately to form the storage region 900. This operation will be explained using the timing shown in FIG. 3 again. ? J accumulation time T1 After the accumulated signal is transferred to the vertical COD register 2, the predetermined amount is transferred to the gate 901.
The first memory section 103-1 in the storage area 900 via
The signals accumulated during the primary accumulation time T2 and transferred to the storage areas 103-2 and 103-3 are similarly transferred to the second memory areas 113-1, 113-2, and 113- in the storage area 900.
Transferred to 3. During the vertical scanning period, the distribution is gate 90.
The signals are alternately transferred to the horizontal CCD registers 4 or 14 via CCD registers 2 and output to the amplifiers 5 or 15.

FIG. 10 shows another embodiment of the present invention, in which a charge sweep section 81 and a coupling section 82 are added to the embodiment of FIG.
is added.

It goes without saying that the above embodiments may be combined with each other.

〔Effect of the invention〕

According to the present invention, since it is possible to output signals stored in each of a plurality of storage units (frame memories) of an imaging device and each having a different storage time, it is possible to extract time-varying components of image information in real time, etc. image processing can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an imaging device according to an embodiment of the present invention;
FIG. 2 is a diagram showing a conventional frame interline transfer type CCD sensor, FIG. 3 is a diagram showing the operation timing of the imaging device of the present invention, and FIG. 4 to FIG. It is a figure showing an example of. 1... Photodiode, 2... Vertical CCD register,
103.113...Storage part, 4.14...Horizontal CO
D register, 7...signal processing circuit. No./B No. 2 Concave 5 Small Kaanfu' 6 Specific force 4 No. 3 Fig. υSi 16
Toi city - La Fig. 4) (b) 4 Tasuino now 46 Sui/-+ Fig. 5 4) Horizontal cc. No. 700 million processing circuit Figure 6 'i7 Concave (Kakei 1 Sub-vJ 3 Figure 9I21 No. 70 Old ゛

Claims (1)

[Claims] 1. A plurality of photoelectric conversion element groups having capacitance such as photodiodes arranged two-dimensionally, and a plurality of photoelectric conversion element groups that vertically transfer signal charges accumulated in the photoelectric conversion element groups. A charge-coupled device consisting of an imaging section, an accumulation section that accumulates signal charges detected by the imaging section for a predetermined period of time, and a charge-coupled device that reads out the signal charges transferred to this accumulation section in the horizontal direction. In the solid-state imaging device, the storage section includes a plurality of storage regions, and the signal charge of the photoelectric conversion element is transferred to the storage region in multiple portions within one field period, and is stored in a predetermined storage region. . A solid-state imaging device, wherein signal charges accumulated in each accumulation region are output using at least one horizontal charge-coupled device within a video period. 2. Claim 1 is characterized in that a charge sweeping region is provided for discharging unnecessary charges of the imaging section to the outside, and the imaging section is provided between the charge sweeping region and the accumulation region. solid-state imaging device.