JPS63204977A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS63204977A
JPS63204977A JP62038220A JP3822087A JPS63204977A JP S63204977 A JPS63204977 A JP S63204977A JP 62038220 A JP62038220 A JP 62038220A JP 3822087 A JP3822087 A JP 3822087A JP S63204977 A JPS63204977 A JP S63204977A
Authority
JP
Japan
Prior art keywords
diode
output
diodes
photoelectric conversion
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62038220A
Other languages
Japanese (ja)
Inventor
Yuichiro Ito
雄一郎 伊藤
Toshiro Yamamoto
俊郎 山本
Isao Tofuku
東福 勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62038220A priority Critical patent/JPS63204977A/en
Publication of JPS63204977A publication Critical patent/JPS63204977A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the fall of an S/N due to a low sensitivity picture element by substituting a high sensitivity diode output for the output of a low sensitivity diode. CONSTITUTION:Among plural number of photoelectric conversion diodes (three number of D1-D3) to constitute one picture element, the diode of the low sensitivity (e.g., D3) is stored previously in a second memory 8, prepared as a substituting means, and after the output of the respective diodes D1-D3 are successively stored in first memory 7, and the data of the three to constitute the same picture element make a set complete, at the time when the outputs of these three diodes are read out from the first memory 7, and added together, the output data of the defective diode D3 is substituted by the output data of the satisfactory diode (D1 or D2) and transmitted to an adder 4, and the addition of three data is performed. Thus, the fall of the S/N can be prevented.

Description

【発明の詳細な説明】 〔概 要〕 本発明は、時間遅延積分(Time Delay In
tegration、以後TDIと略記する)を使った
固体撮像装置において、雑音が大きい、または信号が小
さい等の低感度の光電変換ダイオード(以下単にダイオ
ードと記す)が存在する場合に、この低感度ダイオード
の出力を高感度ダイオード出力で置換することにより、
低感度画素によるS/N比の低下を防止するようにした
ものである。
[Detailed Description of the Invention] [Summary] The present invention provides time delay integration.
When a low-sensitivity photoelectric conversion diode (hereinafter simply referred to as a diode) with large noise or a small signal exists in a solid-state imaging device that uses a By replacing the output with a highly sensitive diode output,
This is to prevent the S/N ratio from decreasing due to low sensitivity pixels.

〔産業上の利用分野〕[Industrial application field]

本発明はT D I fil像装置における低感度ダイ
オード出力を補正し得る固体撮像装置に関する。
The present invention relates to a solid-state imaging device capable of correcting low sensitivity diode output in a TDI fil imaging device.

〔従来の技術〕[Conventional technology]

TDI楊像装置において低感度ダイオードが存在すると
、他のダイオードが正常でもTDI処理後のS/N比が
劣化する。このため低感度ダイオードの悪影響をなくす
手段あるいは方法が必要となる。
If a low-sensitivity diode exists in a TDI image device, the S/N ratio after TDI processing will deteriorate even if the other diodes are normal. Therefore, a means or method is needed to eliminate the adverse effects of low sensitivity diodes.

従来のTDI固体撮像装置の一例として、5画素3段T
DI構成の撮像装置を第3図に示す。図中、1は光電変
換ダイオード、2はCODシフトレジスタ、3はA/D
変換器、4は加算器、5は出力端子、6−1〜6−2は
1ライン遅延回路であり、また矢印は受光面上における
像の移動方向を示す。
As an example of a conventional TDI solid-state imaging device, a 5-pixel 3-stage T
FIG. 3 shows an imaging device with a DI configuration. In the figure, 1 is a photoelectric conversion diode, 2 is a COD shift register, and 3 is an A/D
Converter, 4 is an adder, 5 is an output terminal, 6-1 to 6-2 are one-line delay circuits, and arrows indicate the moving direction of the image on the light receiving surface.

同図の例では、各画素はそれぞれ3個の光電変換ダイオ
ードにより構成されている。即ち、同図の一番上のダイ
オード1−1.1−2.1−3で一個の画素を構成し、
その下の2−1.2−2.2−3で二番目の画素を、以
下同様に各5個の画素ともそれぞれ3個のダイオードに
よって構成されている。
In the example shown in the figure, each pixel is composed of three photoelectric conversion diodes. That is, one pixel is composed of diodes 1-1.1-2.1-3 at the top of the figure,
Below that, the second pixel is 2-1.2-2.2-3, and in the same way, each of the five pixels are each made up of three diodes.

かかる構成とした場合、同一画素を構成する3個のダイ
オード1は、同一の像を異なるタイミングで見ることと
なる。即ち第2段目、3段目のダイオード1は第1段目
、第2段目のダイオード1が一つの像を見た時刻から一
定時間経過後に、その像をみることとなる。
In such a configuration, the three diodes 1 constituting the same pixel view the same image at different timings. That is, the diodes 1 in the second and third stages see the image after a certain period of time has elapsed from the time when the diodes 1 in the first and second stages saw the image.

そこでこれら各ダイオード1の出力はA/D変換器3に
よってディジタル信号に変換された後、第1段目のダイ
オード1の出力には遅延回路6−1と6−2で2段の遅
延を与え、第2段目のダイオード1の出力には遅延回路
6−3で1段の遅延を与え、第3段目のダイオード1の
出力と同一タイミングで加算器4に入力させ、3者を加
え合わせる。
Therefore, the output of each of these diodes 1 is converted into a digital signal by the A/D converter 3, and then the output of the first stage diode 1 is given a two-stage delay by delay circuits 6-1 and 6-2. , the output of the second stage diode 1 is given one stage delay by the delay circuit 6-3, and is input to the adder 4 at the same timing as the output of the third stage diode 1, and the three are added together. .

以上のようにして、各画素の受光時間を実効的に3倍と
して、感度を上げている。
In the manner described above, the light receiving time of each pixel is effectively tripled to increase sensitivity.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のT D I !11像装置では、上述の如<TD
I処理を施すことにより、各画素の感度を上げているが
、一つの画素中に低感度ダイオード(信号が小さい、ま
たは雑音が大きい)が存在すると、たとえ他のダイオー
ドが正常であっても、その画素のTDI処理後のS/N
比が改善されず、逆に劣化するという問題が生じる。
Conventional TDI! In the 11 imager, as described above, <TD
I processing increases the sensitivity of each pixel, but if there is a low sensitivity diode (small signal or large noise) in one pixel, even if the other diodes are normal, S/N after TDI processing of that pixel
A problem arises in that the ratio is not improved and, on the contrary, deteriorates.

本発明の目的は、一つの画素中に低感度のダイオードが
存在しても、S/N比を劣化させることのない固体撮像
装置を提供することにある。
An object of the present invention is to provide a solid-state imaging device in which the S/N ratio does not deteriorate even if a low-sensitivity diode is present in one pixel.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は第1図の原理説明図に示すように、一つの画素
を構成する複数個の光電変換ダイオード(同図ではDi
、D2.03の3個)のうち、予め低感度のダイオード
(例えばD3とする)を、置換手段として設けた第2の
メモリ8に記憶しておき、各ダイオードDI、D2.D
3の出力を順次第1のメモリ7に格納し、同一画素を構
成する3個のデータが揃った後、第1のメモリ7からこ
れら3個のダイオードの出力を読み出して加え合わせる
に際し、上記第2のメモリ8に記憶している欠陥ダイオ
ードを示すデータに基づいて、欠陥ダイオード(この場
合はD3)の出力データを良好なダイオード(この場合
はDIまたはD2)の出力データで置換して加算器4に
送出し、3個のデータの加算を行う。なお同図の100
は信号処理部を示す。
As shown in the principle explanatory diagram of FIG. 1, the present invention utilizes a plurality of photoelectric conversion diodes (Di
, D2.03), a low-sensitivity diode (for example, D3) is stored in advance in the second memory 8 provided as a replacement means, and each diode DI, D2. D
The outputs of the 3 diodes are sequentially stored in the memory 7 of the 1, and after the data of the 3 diodes constituting the same pixel are collected, the outputs of the 3 diodes are read out from the 1st memory 7 and added. Based on the data indicating the defective diode stored in the memory 8 of 2, the output data of the defective diode (D3 in this case) is replaced with the output data of the good diode (DI or D2 in this case) and the adder 4, and the three data are added. Note that 100 in the same figure
indicates a signal processing section.

〔作 用〕[For production]

本発明は、S/N比が低い、或いは雑音が太きい等の欠
陥ダイオードの出力を、他の感度の良いダイオードの出
力と置換してTDI処理することにより、欠陥ダイオー
ドの出力が排除され、TD■処理後のS/N比の低下を
防止できる。
The present invention eliminates the output of a defective diode by replacing the output of a defective diode with a low S/N ratio or high noise with the output of another sensitive diode and performing TDI processing. It is possible to prevent a decrease in the S/N ratio after TD■ processing.

〔実 施 例〕〔Example〕

以下第2図により、本発明の一実施例として、2画素、
3段TDI構成とした例を説明する。
Referring to FIG. 2 below, as an embodiment of the present invention, two pixels,
An example of a three-stage TDI configuration will be described.

同図において、1は光電変換ダイオード、2はCODシ
フトレジスタ、3はA/D変換器、4は加算器、5は出
力端、7はダイオード出力を記憶する第1のメモリ、8
は低感度ダイオード出力を置換するためのアドレスデー
タを記憶する第2のメモリで置換手段を構成し、9は置
換制御信号、10は加算器4へのタイミング信号、10
0は信号処理部である。
In the figure, 1 is a photoelectric conversion diode, 2 is a COD shift register, 3 is an A/D converter, 4 is an adder, 5 is an output terminal, 7 is a first memory that stores the diode output, and 8
9 constitutes a replacement means by a second memory storing address data for replacing the low sensitivity diode output, 9 is a replacement control signal, 10 is a timing signal to the adder 4, 10
0 is a signal processing section.

次に本実施例の動作を説明する。Next, the operation of this embodiment will be explained.

上記構成の固体撮像装置を用いて始めに基準黒体を盪像
し、各々の光電変換ダイオード1−1.1−2゜1−3
.2−1.2−2.2−3の感度を測定し、同一のTD
■グループ、即ち同図では同一画素を構成するダイオー
ド1−1.1−2.1−3のグループと、ダイオード2
−1.2−2.2−3 ノブループにおいて、S/N比
が最大になるように低感度ダイオードを高感度ダイオー
ドで置換するため、両者のアドレスデータを置換手段と
して設けた第2のメモリ8に記憶させる。
First, a reference black body is imaged using the solid-state imaging device having the above configuration, and each photoelectric conversion diode 1-1.1-2°1-3
.. 2-1.2-2.2-3 sensitivity was measured and the same TD
■The group, that is, the group of diodes 1-1.1-2.1-3 that constitute the same pixel in the figure, and the group of diode 2
-1.2-2.2-3 In the knob loop, in order to replace a low sensitivity diode with a high sensitivity diode so that the S/N ratio is maximized, a second memory 8 is provided as a means for replacing the address data of both. to be memorized.

このようにした後、逼像を開始し、各ダイオード1の出
力をA/D変換器3を介してディジタルデータに変換し
、それぞれを第1のメモリ7の各ダイオード1ごとに定
められた所定アドレスに格納して行く。
After doing this, imaging is started, and the output of each diode 1 is converted into digital data via the A/D converter 3, and each is stored in the first memory 7 at a predetermined value determined for each diode 1. Store it in the address.

次いで同一画素を構成する3個のダイオードの出力が全
部揃ったところで、これらを第1のメモリ7から読み出
して加算器4に出力する。この読み出しは、第1のメモ
リ7に対して読み出すべきアドレスを指定して行うが、
このアドレスは第2のメモリ8で参照され、もし上述の
ように前もって検知された欠陥ダイオードのアドレスで
あった場合には、そのアドレスに換えて置換すべきダイ
オードの出力の格納アドレスが、置換制御信号9として
第1のメモリ7に送出される。これにより欠陥ダイオー
ドの出力に換えて代替ダイオードの出力が第1のメモリ
7から加算器4に送出され、タイミング信号10に従っ
て3個の出力データが加算される。
Next, when all the outputs of the three diodes constituting the same pixel are collected, they are read out from the first memory 7 and output to the adder 4. This reading is performed by specifying the address to be read from the first memory 7.
This address is referred to in the second memory 8, and if it is the address of a defective diode detected in advance as described above, the storage address of the output of the diode to be replaced is replaced by the replacement control. It is sent to the first memory 7 as a signal 9 . As a result, the output of the substitute diode is sent from the first memory 7 to the adder 4 in place of the output of the defective diode, and the three output data are added in accordance with the timing signal 10.

以上により本実施例においては、欠陥ダイオードの出力
を高感度ダイオードの出力で代替してTDI処理が行わ
れる。これにより、低感度ダイオードの存在によるS/
N比の低下を防止できる。
As described above, in this embodiment, TDI processing is performed by replacing the output of the defective diode with the output of the high sensitivity diode. This reduces the S/
A decrease in the N ratio can be prevented.

因みに、3個のダイオードの出力と雑音の例を、第1表
に示す。
Incidentally, an example of the output and noise of three diodes is shown in Table 1.

第   1   表 従来の場合だと、TDI後のS/N比は、(15÷10
 +  5) /(1” + 1” + 2” )””
;12.3であるが、本発明によれば、低感度のダイオ
ード1−3の出力を、高感度のダイオード1−1の出力
で置換するため、TDI後のS/N比は、((15+1
5) + 10) / ((1+1)” + 1” )
 ”” #17.9となり、S/N比は約1.5倍に改
善される。
Table 1 In the conventional case, the S/N ratio after TDI is (15÷10
+ 5) / (1” + 1” + 2”)””
;12.3, but according to the present invention, the output of the low sensitivity diode 1-3 is replaced with the output of the high sensitivity diode 1-1, so the S/N ratio after TDI is (( 15+1
5) + 10) / ((1+1)" + 1")
""#17.9, and the S/N ratio is improved by about 1.5 times.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、TDI撮像装置にお
いて低感度のダイオードが存在しても、TDI処理後の
S/N比の低下を小さくすることが可能であり、低感度
ダイオードが存在しても、高感度の撮像装置が得られる
As explained above, according to the present invention, even if a low-sensitivity diode exists in a TDI imaging device, it is possible to reduce the decrease in the S/N ratio after TDI processing; Also, a highly sensitive imaging device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図は本発明一実施例説明図、 第3図は従来のTDI固体撮像装置説明図である。 図において、1は光電変換ダイオード、2はCCDシフ
トレジスタ、3はA/D変換器、4は加算器、5は出力
端、7は第1のメモリ、8は置換制御手段としての第2
のメモリ、100は信号処理部を示す。 /1発明厘理仮明訂 第1図 第2図
FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a conventional TDI solid-state imaging device. In the figure, 1 is a photoelectric conversion diode, 2 is a CCD shift register, 3 is an A/D converter, 4 is an adder, 5 is an output terminal, 7 is a first memory, and 8 is a second memory as a replacement control means.
100 represents a signal processing section. /1 Inventor theory provisional revision Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 入射光量に対応した電気信号を出力する複数個の光電変
換ダイオード(1)からなる画素と、前記光電変換ダイ
オードから出力される電荷を転送するCCDシフトレジ
スタ(2)と、該CCDシフトレジスタを介して出力さ
れた前記各画素を構成する複数個の光電変換ダイオード
の出力に対して時間遅延積分処理を施す信号処理部(1
00)とを具備するとともに、所定値より感度の低い光
電変換ダイオードの出力を、該光電変換ダイオードと同
一画素を構成する複数個の光電変換ダイオードのうちの
他の光電変換ダイオードの出力と置換して前記信号処理
部に送出する置換手段(8)とを具えたことを特徴とす
る固体撮像装置。
A pixel consisting of a plurality of photoelectric conversion diodes (1) that output electrical signals corresponding to the amount of incident light, a CCD shift register (2) that transfers the charge output from the photoelectric conversion diodes, and A signal processing unit (1
00), and replaces the output of a photoelectric conversion diode with sensitivity lower than a predetermined value with the output of another photoelectric conversion diode among a plurality of photoelectric conversion diodes constituting the same pixel as the photoelectric conversion diode. A solid-state imaging device characterized by comprising: substitution means (8) for sending the signal to the signal processing section.
JP62038220A 1987-02-20 1987-02-20 Solid-state image pickup device Pending JPS63204977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62038220A JPS63204977A (en) 1987-02-20 1987-02-20 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62038220A JPS63204977A (en) 1987-02-20 1987-02-20 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS63204977A true JPS63204977A (en) 1988-08-24

Family

ID=12519219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62038220A Pending JPS63204977A (en) 1987-02-20 1987-02-20 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS63204977A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022180A1 (en) * 1994-02-15 1995-08-17 Stanford University Cmos image sensor with pixel level a/d conversion

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022180A1 (en) * 1994-02-15 1995-08-17 Stanford University Cmos image sensor with pixel level a/d conversion
US5461425A (en) * 1994-02-15 1995-10-24 Stanford University CMOS image sensor with pixel level A/D conversion

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