JPS63240059A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63240059A
JPS63240059A JP62075310A JP7531087A JPS63240059A JP S63240059 A JPS63240059 A JP S63240059A JP 62075310 A JP62075310 A JP 62075310A JP 7531087 A JP7531087 A JP 7531087A JP S63240059 A JPS63240059 A JP S63240059A
Authority
JP
Japan
Prior art keywords
base
transistor
emitter
layer
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62075310A
Other languages
Japanese (ja)
Inventor
Nobutaka Amano
信孝 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62075310A priority Critical patent/JPS63240059A/en
Publication of JPS63240059A publication Critical patent/JPS63240059A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce base stored charges at the time of saturation, and to increase the switching rate of a switching circuit by forming an opening section to one part of a collector layer surrounding an emitter layer in a lateral type P-N-P transistor constituting a Darlington circuit in complementary connection. CONSTITUTION:An opening section is shaped to one part of a section oppositely faced to a diffusion layer 4 for connecting a base electrode of a P-type collector layer 2 surrounding a P-type emitter layer 3 in a lateral type P-N-P transistor Q4. Consequently, the quantity of recombination in a base in holes injected to the base from an emitter is increased, and the holes in the base are changed effectively into base currents and discharged to a low-potential power 7 through a collector-emitter path for a transistor Q1. Accordingly, base stored charges can be reduced, thus quickening the turn-OFF time of the transistor Q4, then increasing the switching rate of a switching circuit.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置に関し、特にコンプリメンタリ−接
続のダーリントン回路を有するスイッチング回路が半導
体基板上に形成された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a switching circuit having a complementary-connected Darlington circuit is formed on a semiconductor substrate.

［従来の技術］ 第３図はトランジスタアレイデバイスなどに用いられる
スイッチング回路の従来例の回路構成を示す図、第４図
はこの従来例の有するＰＮＰトランジスタＱ２のレイア
ウトパターンを示す平面図、第５図は第４図のＡ−Ａ線
矢視断面図である。[Prior Art] FIG. 3 is a diagram showing the circuit configuration of a conventional example of a switching circuit used in a transistor array device, etc. FIG. 4 is a plan view showing a layout pattern of a PNP transistor Q2 of this conventional example, and FIG. The figure is a sectional view taken along the line A--A in FIG. 4.

このスイッチング回路は信号入力端子６に人力された信
号を分圧する抵抗Ｒ，，Ｒ２と、エミッタが低電位電源
端子７に、またベースが抵抗ＲＩ。This switching circuit has resistors R, R2 that divide the voltage of a signal input to the signal input terminal 6, an emitter connected to a low potential power supply terminal 7, and a base connected to a resistor RI.

Ｒ２の分圧点に、それぞれ接続されたエミッタ接地ＮＰ
ＮトランジスタＱＩと、ＮＰＮトランジスタＱ＋のコレ
、フタと高電位電源端子５との間に設けられた負荷抵抗
Ｒ３と、ベースが負荷抵抗Ｒ３とＮＰＮトランジスタＱ
＋の接続点に接続されたＰＮＰトランジスタＱ２とＮＰ
ＮトランジスタＱ３とで構成されたコンプリメンタリ−
接続のダーリントン回路と、ＮＰＮトランジスタＱ３の
ベースとエミッタ間に接続された抵抗Ｒ４と、出力端子
８とからなっている。Emitter grounding NP connected to the voltage dividing point of R2, respectively.
This includes an N transistor QI and an NPN transistor Q+, a load resistor R3 provided between the lid and the high potential power supply terminal 5, and a base connected to the load resistor R3 and the NPN transistor Q.
PNP transistor Q2 and NP connected to the + connection point
Complementary composed of N transistor Q3
It consists of a connected Darlington circuit, a resistor R4 connected between the base and emitter of an NPN transistor Q3, and an output terminal 8.

ＰＮＰトランジスタＱ２は、Ｐ型半導体基板１１上に形
成されたＮ型エピタキシャル層１をＰ型絶縁層９で他領
域から電気的に分離して得られた島領域内に形成されて
おり、Ｐ型エミッタ層３と、このエミツタ層３を完全に
とっかこむＰ型コレクタ層２と、ベース電極接続用拡散
層４と、Ｎ型埋込層１０とから構成されている。The PNP transistor Q2 is formed in an island region obtained by electrically separating an N-type epitaxial layer 1 formed on a P-type semiconductor substrate 11 from other regions with a P-type insulating layer 9, and is a P-type transistor. It is composed of an emitter layer 3, a P-type collector layer 2 that completely surrounds the emitter layer 3, a base electrode connection diffusion layer 4, and an N-type buried layer 10.

［発明が解決しようとする問題点］ 上述した従来の半導体装置は、ＰＮＰトランジスタＱ２
がオンしているときには深く飽和し、ベースに多量の電
荷が蓄積されるとともに、入力信号がハイレベルからロ
ーレベルに変化し、このＰＮＰトランジスタＱ２がオン
からオフへ移行するときには、ベース蓄積電荷は、トラ
ンジスタＱ１のベース・コレクタ間およびベース・エミ
ッタ間のリーク電流ならびにトランジスタＱ２のベース
・コレクタ間のリーク電流によってしか放電されないた
めに、スイッチングにかなりの遅延が生じ、この結果、
スイッチング回路全体のスイッチング速度が遅くなると
いう欠点がある。この場合の遅延時間は数μｓから十数
μｓにもおよぶために、例えばディスプレイ素子をダイ
ナミック駆動する場合には表示誤りをおこすという欠点
がある。[Problems to be Solved by the Invention] The conventional semiconductor device described above has a PNP transistor Q2.
When Q2 is on, it is deeply saturated and a large amount of charge is accumulated in its base.When the input signal changes from high level to low level and this PNP transistor Q2 shifts from on to off, the base accumulated charge is , is discharged only by the base-collector and base-emitter leakage currents of transistor Q1 and the base-collector leakage current of transistor Q2, resulting in a considerable switching delay, resulting in
This has the disadvantage that the switching speed of the entire switching circuit is slow. Since the delay time in this case ranges from several μs to more than ten μs, there is a drawback that, for example, when dynamically driving a display element, display errors may occur.

［問題点を解決するための手段］ 本発明の半導体装置は、コンプリメンタリ−接続のダー
リントン回路を構成する横形ＰＮＰトランジスタのエミ
ツタ層をとりかこむコレクタ層の一部に開口部が設けら
れている。[Means for Solving the Problems] In the semiconductor device of the present invention, an opening is provided in a part of the collector layer surrounding the emitter layer of a lateral PNP transistor constituting a complementary-connected Darlington circuit.

［作用］ 横形ＰＮＰトランジスタのエミツタ層をとっかこむコレ
クタ層の一部に開口部を設けることにより、エミツタ層
から注入された正孔のうち、ベース層において再結合す
るものが増加するので、等価的に直流電流増幅率が低下
し、飽和の程度が浅くなってベース蓄積電荷が減少する
ためにターンオフ時間が早まり、その結果、スイッチン
グ回路のスイッチング速度の改善を図ることができる。[Function] By providing an opening in a part of the collector layer surrounding the emitter layer of the lateral PNP transistor, the number of holes injected from the emitter layer that recombine in the base layer increases, so that the equivalent The DC current amplification factor decreases, the degree of saturation becomes shallower, and the base accumulated charge decreases, so the turn-off time becomes faster, and as a result, the switching speed of the switching circuit can be improved.

また、このコンプリメンタリ−接続のダーリントン回路
においては、出力段のＮＰＮトランジスタの電流増幅率
を高く設定することにより、横形ＰＮＰトランジスタの
電流増幅率の低下によってほとんど影響をうけない。Furthermore, in this complementary-connected Darlington circuit, by setting the current amplification factor of the NPN transistor in the output stage to be high, it is hardly affected by a decrease in the current amplification factor of the lateral PNP transistor.

［実施例］ 次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の半導体装置の一実施例におけるスイ
ッチング回路の回路図、第２図は第１図におけるＰＮＰ
トランジスタＱ４のレイアウトパターンを示す平面図で
ある。[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a switching circuit in an embodiment of the semiconductor device of the present invention, and FIG. 2 is a circuit diagram of a PNP in FIG.
FIG. 3 is a plan view showing a layout pattern of a transistor Q4.

本実施例は、第３図に示したスイッチング回路の従来例
の有する横形ＰＮＰトランジスタＱ２を別の横形ＰＮＰ
トランジスタＱ４で置換したもので、その他の構成はす
べて従来例と同一である。In this embodiment, the lateral PNP transistor Q2 of the conventional switching circuit shown in FIG. 3 is replaced with another lateral PNP transistor Q2.
It is replaced with transistor Q4, and all other configurations are the same as the conventional example.

横形ＰＮＰトランジスタＱ４のレイアクドパ々−−ノ　
Ｌ４７Ｍ、’）、　丙１７　病÷す　ト　ろ　Ｌ啼　　
　ｐ　鰻す１−　夕　ゆ、々　層　３をどっかこむＰ型
コレクタ層２のベース電極接続用拡散層４に対向する部
分の一部に開口部が設けられている。これにより、エミ
ッタからベースに注入された正孔のうちベースにおける
再結合量が増し、効果的にベース電流となってトランジ
スタＱ＋のコレクタ・エミッタ経路を介して低電位電源
７に放電されるので、ベース蓄積電荷を減少させること
ができ、トランジスタＱ４のターンオフ時間が早められ
、スイッチング回路のスイッチング速度が改善される。Layout pattern of horizontal PNP transistor Q4
L47M,')、Hei17 disease÷su toro L啼
An opening is provided in a part of the P-type collector layer 2, into which the p-type collector layer 3 is placed, facing the base electrode connection diffusion layer 4. As a result, the amount of holes injected from the emitter to the base increases, and the amount of recombination at the base increases, effectively turning into a base current and discharging it to the low potential power supply 7 via the collector-emitter path of transistor Q+. The base accumulated charge can be reduced, the turn-off time of transistor Q4 is accelerated, and the switching speed of the switching circuit is improved.

また、Ｐ型コレクタ層２の形状は、マスクパターンの変
更で簡単に変更でき、ＰＮＰトランジスタＱ４が最も好
ましい電流増幅率になるように自由に調整可能である。Furthermore, the shape of the P-type collector layer 2 can be easily changed by changing the mask pattern, and can be freely adjusted so that the PNP transistor Q4 has the most preferable current amplification factor.

［発明の効果］ 以上説明したように本発明は、コンプリメンタリ−接続
のダーリントン回路を構成する横形ＰＮＰトランジスタ
のコレクタ層の一部に開口部を設けることにより、飽和
時のベース蓄積電荷を低減し、スイッチング回路のスイ
ッチング速度を改善できる効果がある。[Effects of the Invention] As explained above, the present invention provides an opening in a part of the collector layer of the lateral PNP transistor constituting the complementary-connected Darlington circuit, thereby reducing the base accumulated charge at saturation. This has the effect of improving the switching speed of the switching circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体装置の一実施例におけるスイッ
チング回路の回路図、第２図は第１図の横形ＰＮＰトラ
ンジスタＱ４のレイアウトパターンを示す平面図、第３
図は従来例におけるスイッチング回路の回路図、第４図
は第３図のＰＮＰトランジスタＱ２のレイアウトパター
ンを示す平面図、第５図は第４図のＡ−Ａ線矢視断面図
である。 １・・・Ｎ型エピタキシャル層、 ２・・・Ｐ型コレクタ層、 ３・・・Ｐ型エミッタ層、 ４・・・ベース電極接続用拡散層、 ５・・・高電位電源端子、 ６・・・信号入力端子、 ７・・・低電位電源端子、 ８・・・出力端子、 ９・・・Ｐ型絶縁層、 １０・・・Ｎ型埋込層、 １１・・・Ｐ型半導体基板、 Ｑ１〜Ｑ４　・・・トランジスタ、 Ｒ１〜Ｒ４・・・抵抗。 特許出願人　　日本電気株式会社 第１図 第２図 第３図FIG. 1 is a circuit diagram of a switching circuit in an embodiment of the semiconductor device of the present invention, FIG. 2 is a plan view showing a layout pattern of the horizontal PNP transistor Q4 in FIG. 1, and FIG.
4 is a plan view showing a layout pattern of the PNP transistor Q2 of FIG. 3, and FIG. 5 is a sectional view taken along the line A--A in FIG. 4. DESCRIPTION OF SYMBOLS 1...N type epitaxial layer, 2...P type collector layer, 3...P type emitter layer, 4...diffusion layer for base electrode connection, 5...high potential power supply terminal, 6...・Signal input terminal, 7...Low potential power supply terminal, 8...Output terminal, 9...P type insulating layer, 10...N type buried layer, 11...P type semiconductor substrate, Q1 ~Q4...Transistor, R1~R4...Resistor. Patent applicant: NEC Corporation Figure 1 Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）エミッタ接地ＮＰＮトランジスタと、該エミッタ
接地ＮＰＮトランジスタのコレクタにその一端が接続さ
れた負荷抵抗と、該負荷抵抗と前記エミッタ接地ＮＰＮ
トランジスタとの接続点にベースが接続されたエミッタ
接地横形ＰＮＰトランジスタと、該ＰＮＰトランジスタ
のコレクタにベースが接続されたコレクタ接地ＮＰＮト
ランジスタとを有するスイッチング回路が半導体基板上
に形成された半導体装置において、 前記エミッタ接地横形ＰＮＰトランジスタのエミッタ層
をとりかこむコレクタ層の一部に開口部が設けられてい
ることを特徴とする半導体装置。(1) A common emitter NPN transistor, a load resistor whose one end is connected to the collector of the common emitter NPN transistor, and the load resistor and the common emitter NPN transistor.
A semiconductor device in which a switching circuit including a common-emitter lateral PNP transistor whose base is connected to a connection point with a transistor, and a common-collector NPN transistor whose base is connected to a collector of the PNP transistor is formed on a semiconductor substrate, A semiconductor device characterized in that an opening is provided in a part of a collector layer surrounding an emitter layer of the emitter-grounded lateral PNP transistor. （２）前記エミッタ接地横形ＰＮＰトランジスタのコレ
クタ層の開口部が、ベース電極接続用拡散層に対向して
設けられている特許請求の範囲第１項に記載の半導体装
置。(2) The semiconductor device according to claim 1, wherein the opening in the collector layer of the common emitter lateral PNP transistor is provided opposite to the base electrode connection diffusion layer.
JP62075310A 1987-03-27 1987-03-27 Semiconductor device Pending JPS63240059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62075310A JPS63240059A (en) 1987-03-27 1987-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62075310A JPS63240059A (en) 1987-03-27 1987-03-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63240059A true JPS63240059A (en) 1988-10-05

Family

ID=13572553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62075310A Pending JPS63240059A (en) 1987-03-27 1987-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63240059A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216738A (en) * 1993-01-14 1994-08-05 Toshiba Corp Photocoupler device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216738A (en) * 1993-01-14 1994-08-05 Toshiba Corp Photocoupler device

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