JPS63239939A - Method and apparatus for introducing impurity into semiconductor substrate - Google Patents

Method and apparatus for introducing impurity into semiconductor substrate

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Publication number
JPS63239939A
JPS63239939A JP7169087A JP7169087A JPS63239939A JP S63239939 A JPS63239939 A JP S63239939A JP 7169087 A JP7169087 A JP 7169087A JP 7169087 A JP7169087 A JP 7169087A JP S63239939 A JPS63239939 A JP S63239939A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
impurity
impurities
container
compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7169087A
Other languages
Japanese (ja)
Inventor
Yoshitaka Tsunashima
綱島 祥隆
Katsuya Okumura
勝弥 奥村
Toshio Mitsuno
三ツ野 敏夫
Masahiro Kashiwagi
柏木 正弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7169087A priority Critical patent/JPS63239939A/en
Publication of JPS63239939A publication Critical patent/JPS63239939A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make it possible to introduce impurities into an inner wall part such as a groove and the like, which are formed in a semiconductor substrate, uniformly with good controllability as in a flat part, by exposing the semiconductor substrate in a pressure reduced compound gas atmosphere including impurities, and heating the substrate. CONSTITUTION:Compound gas including impurities, which are to be introduced into a semiconductor substrate 8, is introduced into a container 2, the inside of which is exhausted. The pressure of the gas in the container 2 is reduced lower than an atmospheric pressure. The temperature of the semiconductor substrate 8, which is provided in the container 2, is made higher than the temperature of the inner wall of the container 2. For example, the silicon substrate 8 is mounted on a sample stage 13 in the impurity introduced chamber 2. Arsine is introduced through a gas introducing system 18. The substrate 8 is heated with infrared-ray lamps 14. A temperature of 1,000 deg.C is kept for one minute. The arsine is decomposed on the surface and in the vicinity of the surface of the substrate. Arsenic is introduced into the surface of the substrate. Then the arsine is evacuated, and argon is introduced. Thereafter the substrate 8 is heated again with the infrared-ray lamps 14. The temperature of 1,000 deg.C is kept for 30 minutes, and the arsenic, which is introduced in the surface of the substrate, is diffused. Thus an N-type conductor layer is formed.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、半導体基体内への不純物導入方法および装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method and apparatus for introducing impurities into a semiconductor substrate.

(従来技術) 近年、ダイナミックRAM (dRAM)等の半導体集
積回路は、構成素子の微細化による高集積化が著しい、
特に1トランジスタ/1キヤパシタ構成のメモリセルを
用いたdRAMにおいては、メモリセルの縮少が重要で
ある。メモリセル縮少の際に問題となるのが、十分な読
み出しマージンのあるSZN比の確保およびソフトエラ
ーの耐性の点からセルキャパシタの蓄積電荷量を減少さ
せることが回置なことである。従来通りのキャパシタ絶
縁膜の薄膜化により蓄積電荷量を維持する方法は、現在
その絶縁膜が、電界強度および信頼性の面から薄膜化限
界に近づくため、その適用が困難である。
(Prior art) In recent years, semiconductor integrated circuits such as dynamic RAM (dRAM) have become highly integrated due to miniaturization of component elements.
Particularly in a dRAM using memory cells with a one-transistor/one-capacitor configuration, reducing the number of memory cells is important. A problem when reducing memory cells is that it is important to reduce the amount of charge stored in cell capacitors in order to ensure an SZN ratio with sufficient read margin and to ensure soft error resistance. The conventional method of maintaining the amount of stored charge by thinning the capacitor insulating film is currently difficult to apply because the insulating film approaches its thinning limit in terms of electric field strength and reliability.

これに代わって、キャパシタ領域のシリコン基板表面に
溝を堀り、この溝側壁部を利用して実効的なキャパシタ
面積を稼ぐ構造(トレンチキャパシタセル)が、蓄積電
荷量を維持する方法として有望視されている。
Instead, a structure (trench capacitor cell) in which a trench is dug in the surface of the silicon substrate in the capacitor region and the sidewalls of the trench are used to increase the effective capacitor area is seen as a promising method for maintaining the amount of stored charge. has been done.

トレンチキャパシタセルには、種々の構造のものが考え
られているが、溝の内部に高濃度の不純物拡散層を形成
した構造は、基板側に空乏層が伸びず、キャパシタの蓄
積電荷量が減少しない、そのため、1/2Vcc動作さ
せることも可能で、キャパシタ絶縁膜に対する負担も軽
減される。この場合、狭く、深い溝内部の垂直な側面に
、不純物を制御性良く、均一にドーピングする方法が重
要になる。
Various structures have been considered for trench capacitor cells, but the structure in which a highly concentrated impurity diffusion layer is formed inside the trench prevents the depletion layer from extending toward the substrate, reducing the amount of accumulated charge in the capacitor. Therefore, it is also possible to operate at 1/2 Vcc, and the load on the capacitor insulating film is also reduced. In this case, it is important to have a method for doping impurities uniformly and with good control on the vertical side surfaces inside the narrow and deep trench.

従来、集積回路プロセスでは、拡散層形成には、イオン
注入法がその特徴である制御性の良さから広く使用され
ている。しかし、イオン注入法をトレンチ構造へ応用す
る場合、不純物イオンの注入方向が一定のため、溝の垂
直な側面で注入イオンに対して影となる部分ができ、不
純物の注入されない領域が生じる。影になる領域をなく
す手段として、注入傾斜角を変化させたり、シリコン基
板を回転させる方法が考えられる。しかし、いずれの方
法も、今後の高集積化から予想される開口部の狭く、よ
り深い溝への応用は不可能である。
Conventionally, in integrated circuit processes, ion implantation has been widely used to form diffusion layers due to its characteristic good controllability. However, when applying the ion implantation method to a trench structure, since the direction of implantation of impurity ions is constant, a portion is formed that shadows the implanted ions on the vertical side surfaces of the trench, resulting in a region where no impurity is implanted. Possible means of eliminating shadowed regions include changing the implantation tilt angle and rotating the silicon substrate. However, none of these methods can be applied to narrower and deeper grooves that are expected to result from future high integration.

イオン注入法に代わるトレンチキャパシタの不純物拡散
層の形成法としては、同相がらの拡散を利用した方法が
考えられる。拡散源として、不純物を添加した多結晶シ
リコン膜やシリコン酸化膜を溝内部に形成した後、熱拡
散によって、シリコン基板の表面へ不純物を導入する方
法である。この場合拡散源の形成方法が問題であり、適
切な不純物濃度の均質な膜が、溝の内壁に均一に形成さ
れることが必要となる。しかし、溝の開口部が狭く、深
さが深くなる程、均一は拡散源の形成は困難になる。
As a method of forming an impurity diffusion layer of a trench capacitor in place of the ion implantation method, a method using in-phase diffusion can be considered. This is a method in which a polycrystalline silicon film or a silicon oxide film doped with impurities is formed inside the trench as a diffusion source, and then the impurities are introduced into the surface of the silicon substrate by thermal diffusion. In this case, the problem is how to form the diffusion source, and it is necessary to uniformly form a homogeneous film with an appropriate impurity concentration on the inner wall of the trench. However, the narrower the groove opening and the deeper the groove, the more difficult it becomes to form a uniform diffusion source.

例えば、化学気相成長(CVD)法で形成する場合、被
覆性が溝の底部に近づく程悪くなり、薄膜化する。この
薄膜化は、不純物の拡散量の不足を招き、Uの上部と底
部とで不純物拡散層の濃度が均一にならなくなる。また
、不純物を含む溶液を塗布・乾燥させて、拡散源とする
方法では、溝内部の気泡が抜けきらないおそれがあり、
1チップ百方個以上の数の溝の内部に洩れなく溶液を導
入することは、溝の開口幅が狭く、深さが深くなるにし
たがって、困難になると考えられる。また、固相拡散法
では、いずれの場合も、拡散した後に拡散源を除去する
必要があり、プロセス的に複雑なものにならざるを得な
い。
For example, in the case of forming by chemical vapor deposition (CVD), the closer to the bottom of the groove the coverage becomes worse and the film becomes thinner. This thinning causes an insufficient amount of impurity diffusion, and the concentration of the impurity diffusion layer becomes uneven between the top and bottom of the U. In addition, with the method of applying and drying a solution containing impurities and using it as a diffusion source, there is a risk that the air bubbles inside the groove may not be completely removed.
It is thought that it becomes more difficult to introduce a solution into the grooves, which number more than 100 squares per chip, without leaking, as the opening width of the grooves becomes narrower and the depth thereof becomes deeper. Furthermore, in any case, in the solid-phase diffusion method, it is necessary to remove the diffusion source after diffusion, which inevitably results in a complicated process.

すなわち既存の不純物導入方法では、上記の点からダイ
ナミックランダムアクセスメモリのキャパシタセルに限
らず、シリコン表面に形成した開口部の幅が狭く、深さ
が深い溝の内壁等に不純物を制御性よく導入することは
、困難である。
In other words, with existing impurity introduction methods, it is possible to controllably introduce impurities not only into capacitor cells of dynamic random access memory but also into the inner walls of deep trenches with narrow openings formed on the silicon surface. It is difficult to do so.

(発明が解決しようとする問題点) 本発明は、上記の点に鑑みなされたもので、その目的と
するところは、半導体基体に形成される溝等の内壁部分
に、平担部と同様に不純物を均一に制御性良く導入する
ことを可能とする半導体基体内への不純物の導入方法お
よび装置を提供することにある。
(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned points, and its purpose is to provide the inner wall portion of a groove etc. formed in a semiconductor substrate with a flat portion similar to a flat portion. It is an object of the present invention to provide a method and apparatus for introducing impurities into a semiconductor substrate, which makes it possible to introduce impurities uniformly and with good controllability.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 本発明は、半導体基体内に不純物を導入する方法として
、半導体基体を減圧された不純物を含む化合物ガス雰囲
気に晒し、半導体基体を加熱することにより不純物を含
む化合物を基体表面あるいは、その近傍で分解し、前記
不純物を半導体基体内に拡散することにある。また本発
明は上記方法のための不純物の導入装置として、不純物
を含む化合物ガスを容器内に導入、および排気する手段
と、容器内を大気圧以下に減圧する手段と、前記容器内
に配置される半導体基体を容器内壁よりも高温に加熱・
保持する手段とを備えるものである。
(Means for Solving the Problems) The present invention is a method for introducing impurities into a semiconductor substrate by exposing the semiconductor substrate to a reduced pressure atmosphere of a compound gas containing impurities and heating the semiconductor substrate. The purpose is to decompose the compound at or near the surface of the substrate and diffuse the impurities into the semiconductor substrate. The present invention also provides an apparatus for introducing impurities for the above method, which includes means for introducing and exhausting a compound gas containing impurities into a container, means for reducing the pressure in the container to below atmospheric pressure, and a device disposed in the container. The semiconductor substrate is heated to a higher temperature than the inner wall of the container.
and holding means.

(作  用) 本発明によれば、半導体基体の例えば開口部が狭く且つ
深い溝内部にも、平担部と同様に不純物を均一に制御性
よく導入することが可能となる。
(Function) According to the present invention, it is possible to introduce impurities uniformly and with good controllability into, for example, a groove with a narrow and deep opening in a semiconductor substrate, similarly to the flat portion.

すなわち、不純物を含む化合物ガスを存在する気相状態
を不純物拡散源として減圧した形で使用することにより
、不純物を含む化合物分子の平均自由行程を長くして、
半導体基体上の例えば開口部の狭く且つ深い溝の内部に
も拡散源である不純物を含む化合物分子を確実に侵入さ
せることが可能になり、平担部と同様に不純物を均一に
溝の奥まで導入させることができる。また、雰囲気中に
含まれる不純物を含む化合物の量を多くすることにより
、半導体基体中へ導入される不純物量は、半導体基体を
加熱した温度における基体中の不純物の固溶限界と拡散
係数とで決定するため、制御性の良い不純物の導入が可
能となる。さらに同相拡散源を用いた場合と異なり、拡
散源が気相状態であるために、拡散源の除去工程が必ず
しも必要ではなく、不純物導入工程が複雑にならない利
点がある。
In other words, by using a compound gas containing impurities in a reduced pressure state as an impurity diffusion source, the mean free path of the compound molecules containing impurities is lengthened.
For example, it is possible to reliably infiltrate compound molecules containing impurities as a diffusion source into the inside of a narrow and deep groove of an opening on a semiconductor substrate, and the impurity can be uniformly distributed deep into the groove in the same way as in a flat area. can be introduced. Furthermore, by increasing the amount of impurity-containing compounds contained in the atmosphere, the amount of impurities introduced into the semiconductor substrate is determined by the solid solubility limit and diffusion coefficient of the impurity in the substrate at the temperature at which the semiconductor substrate is heated. Therefore, it is possible to introduce impurities with good controllability. Further, unlike the case where an in-phase diffusion source is used, since the diffusion source is in a gas phase, a process for removing the diffusion source is not necessarily required, and there is an advantage that the impurity introduction process is not complicated.

(実 施 例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図は、本発明による不純物導入装置の一実施例を示
す概略構成図である。
FIG. 1 is a schematic diagram showing an embodiment of an impurity introduction device according to the present invention.

この装置は、試料を導入する試料導入室1と。This device includes a sample introduction chamber 1 into which a sample is introduced.

試料に不純物を拡散導入する不純物導入室2と、試料を
取り出す試料搬出室3とが、それぞれ第1のゲートバル
ブ4、第2のゲートバルブ5を介して、順次配列されて
おり、試料を951の試料搬送装置11と第2の試料搬
送装[12とによって、順次搬送し、試料である半導体
基体8、例えばシリコン基板中へ不純物の導入を行なう
ものである。
An impurity introduction chamber 2 for diffusing and introducing impurities into a sample and a sample transfer chamber 3 for taking out a sample are arranged in sequence via a first gate valve 4 and a second gate valve 5, respectively. The sample transport device 11 and the second sample transport device [12] sequentially transport impurities into a semiconductor substrate 8, which is a sample, such as a silicon substrate.

また、前記不純物導入室2は、第3のゲートバルブ6を
介して、ターボ分子ポンプ9と、さらに第4のゲートバ
ルブ7を介して、ロータリーポンプ10とに接続されて
おり、真空排気することが可能である。また、図示しな
いが前記試料導入室1、および前記試料搬出室3も、そ
れぞれ真空排気することが可能になっている。
Further, the impurity introduction chamber 2 is connected to a turbo molecular pump 9 via a third gate valve 6 and to a rotary pump 10 via a fourth gate valve 7, and is evacuated. is possible. Although not shown, the sample introduction chamber 1 and the sample transfer chamber 3 can also be evacuated.

さらに、前記不純物導入室2には、第1のガス導入系1
8、および第2のガス導入系19が、それぞれ第1のバ
ルブ16、および第2のバルブ17を介して接続されて
おり、不純物化合物を含むガス、および不活性なガスを
、装置内に導入することができる。
Furthermore, a first gas introduction system 1 is provided in the impurity introduction chamber 2.
8 and a second gas introduction system 19 are connected via a first valve 16 and a second valve 17, respectively, and introduce a gas containing an impurity compound and an inert gas into the apparatus. can do.

また、前記不純物導入室2には1石英製の試料台13を
持つ試料を上下動させることのできる試料支持装置15
を具えている6さらにこの試料支持装置15は、赤外線
ランプ14を具えており、試料8を所望の温度に加熱す
ることができる。
Further, in the impurity introduction chamber 2, there is provided a sample support device 15 that can vertically move a sample having a sample stage 13 made of quartz.
The sample support device 15 further includes an infrared lamp 14, which can heat the sample 8 to a desired temperature.

次に1本発明方法の実施例として上述した装置を用いて
、開口部の狭い、深い溝を有するシリコン基板表面にヒ
素を導入する方法について説明する。
Next, as an embodiment of the method of the present invention, a method of introducing arsenic into the surface of a silicon substrate having a deep groove with a narrow opening using the above-mentioned apparatus will be described.

まず、試料のシリコン基板を試料導入室1の搬送装置1
1上に載置した後、該導入室1を密閉して。
First, the silicon substrate of the sample is transferred to the transfer device 1 in the sample introduction chamber 1.
1, the introduction chamber 1 is sealed.

真空排気することにより、該導入室の圧力を10−4〜
10−’Pa程度に減圧する。
By evacuating, the pressure in the introduction chamber is reduced to 10-4~
Reduce the pressure to about 10-'Pa.

不純物導入室2は、通常ターボ分子ポンプ9でtoSP
a以下に減圧されており、第1のゲートバルブ4を開け
た後、該搬送装置11を用いて、該不純物導入室2内の
試料支持装置15上の試料台13に移す。そして、第1
のゲートバルブ4および第3のゲートバルブ6を閉じて
該不純物導入室2を密閉した後、第1のバルブ16を開
けて、第1のガス導入系18から、ヒ素の水素化合物で
あるアルシン(AgH,)を導入する。アルシンを圧力
にして10−1〜10Pa程度導入した後、第1のバル
ブ16を閉じて、アルシンガスを該不純物導入室2内に
封入する。
The impurity introduction chamber 2 is normally equipped with a turbo molecular pump 9 toSP.
After opening the first gate valve 4, the sample is transferred to the sample stage 13 on the sample support device 15 in the impurity introduction chamber 2 using the transfer device 11. And the first
After closing the gate valve 4 and the third gate valve 6 to seal the impurity introduction chamber 2, the first valve 16 is opened and arsine (a hydrogen compound of arsenic) is introduced from the first gas introduction system 18. AgH,) is introduced. After arsine is introduced at a pressure of about 10 -1 to 10 Pa, the first valve 16 is closed and arsine gas is sealed into the impurity introduction chamber 2 .

この状態のまま、赤外線ランプ14により試料のシリコ
ン基板(半導体基体8に相当する)8を加熱し、100
0℃に1分間保持することにより、基板表面および表面
近傍でアルシンを分解させ、基板表面にヒ素を所望の量
だけ導入する。
In this state, the sample silicon substrate (corresponding to the semiconductor substrate 8) 8 was heated with the infrared lamp 14, and
By holding at 0° C. for 1 minute, arsine is decomposed on and near the substrate surface, and a desired amount of arsenic is introduced onto the substrate surface.

その後、第4のゲートバルブ7を開けて、ロータリーポ
ンプ10により、不純物導入室2汀のアルシンを排気す
る。その後、第2のバルブ17を開けて、アルゴンを圧
力にして10−1〜10Pa程度導入した後、再び赤外
ランプ14により試料のシリコン基板8を加熱し、 t
ooo℃に30分間保持することにより、基板表面導入
されたヒ素を拡散させ、所望の拡散深さのn型溝itN
を形成する。その後、ゲートバルブ7を閉じて、不純物
導入室2を真空排気することにより、10−4〜10−
’Pa程度に減圧する。
Thereafter, the fourth gate valve 7 is opened, and the arsine in the impurity introduction chamber 2 is exhausted by the rotary pump 10. Thereafter, the second valve 17 is opened and argon is introduced at a pressure of about 10-1 to 10 Pa, and then the silicon substrate 8 of the sample is heated again by the infrared lamp 14.
By keeping the temperature at ooo°C for 30 minutes, the arsenic introduced into the substrate surface is diffused, and an n-type groove itN with a desired diffusion depth is formed.
form. Thereafter, by closing the gate valve 7 and evacuating the impurity introduction chamber 2, the steps 10-4 to 10-
Reduce the pressure to about 'Pa.

引き続いて、第2のゲートバルブ5を開けて。Next, open the second gate valve 5.

搬送装置12を用いて、試料台13上のシリコン基板8
を該搬送装置12に移し、10−4〜10−’Pa程度
に減圧させている試料搬出室3に搬送する。その後該ゲ
ートバルブ5を閉じて、該試料搬出室3を大気圧に戻し
た後、試料のシリコン基板8を装置から取り出す。
Using the transport device 12, the silicon substrate 8 on the sample stage 13 is
is transferred to the transport device 12 and transported to the sample transport chamber 3 where the pressure is reduced to about 10-4 to 10-'Pa. Thereafter, the gate valve 5 is closed to return the sample transfer chamber 3 to atmospheric pressure, and then the sample silicon substrate 8 is taken out from the apparatus.

以上の工程を経ることにより、シリコン基板表面にヒ素
を拡散させる工程が終了するが、気相の不純物拡散源で
あるアルシンを用いているために、試料であるシリコン
基板上に形成された開口部の狭く、深い溝形状の内部に
も均一にヒ素を形成することが可能となる。
By going through the above steps, the process of diffusing arsenic onto the silicon substrate surface is completed, but since arsine, which is a vapor phase impurity diffusion source, is used, the openings formed on the silicon substrate, which is the sample, are It becomes possible to uniformly form arsenic even inside the narrow and deep groove shape.

上記実施例では、不純物化合物雰囲気において。In the above example, in an impurity compound atmosphere.

基板の加熱工程を行なっているが、あらかじめ基板の加
熱を行ない、基板温度を上げた状態で不純物化合物ガス
を導入してもよい。
Although the substrate heating process is performed, the impurity compound gas may be introduced in a state where the substrate is heated in advance and the substrate temperature is raised.

表面に不純物を含んだ薄膜を形成して、この薄膜から不
純物を拡散してもよい。
A thin film containing impurities may be formed on the surface and the impurities may be diffused from this thin film.

また、上記実施例においては、基板表面に導入された不
純物を拡散させる高温加熱工程を同じ装置内で行なって
いるが、この高温加熱工程は、別の装置で行なってもよ
い。
Furthermore, in the above embodiments, the high temperature heating step for diffusing impurities introduced into the substrate surface is performed in the same device, but this high temperature heating step may be performed in a separate device.

さらに上記実施例においては、不純物化合物としてアル
シンを用いたが、拡散する不純物元素が、燐、ヒ素、ア
ンチモン、ホウ素、もしくはガリウム等であれば、その
素子の水素化物、塩化物もしくは弗化物であってもよい
Furthermore, in the above example, arsine was used as the impurity compound, but if the impurity element to be diffused is phosphorus, arsenic, antimony, boron, or gallium, it may be a hydride, chloride, or fluoride of the element. It's okay.

また、シリコン基板の加熱方法として、上記実施例では
、赤外線ランプを用いたが、半導体基体にて吸収し得る
エネルギーを持つ光を照射する方法であれば、他の種々
な方法の利用が可能である。
Furthermore, in the above example, an infrared lamp was used as a method of heating the silicon substrate, but various other methods can be used as long as they irradiate light with energy that can be absorbed by the semiconductor substrate. be.

また、上述した実施例では、不純物を含む化合物の分解
を熱反応によって行なったが、分解に十分なエネルギー
を持った光の照射によって行っても良い、また、エレク
トロン・サイクロトロン・レゾナンス、もしくは、マグ
ネトロンを用いて。
Furthermore, in the above-mentioned embodiments, the decomposition of compounds containing impurities was carried out by thermal reaction, but it may also be carried out by irradiation with light having sufficient energy for decomposition, or by electron, cyclotron, resonance or magnetron. Using.

不純物化合物を分解、プラズマ化して、半導体基体表面
に堆積あるいは、基板内に導入する方法を用いてもよい
A method may be used in which the impurity compound is decomposed and turned into plasma, and then deposited on the surface of the semiconductor substrate or introduced into the substrate.

上記実施例による方法を用いて、第2図(a) 、 (
b)にその平面及び断面を示す様なシリコン基板の溝内
部および主表面に拡散層を形成した場合のMOSキャパ
シタのC−V(容量−電圧)特性を第2図(C)に示す
、第2図(C)において、従来例と上記実施例によって
形成されたキャパシタのC−■特性を比較する。従来例
では、第2図(d)、 (e)に断面を示す様に半導体
基体の溝部に不純物の導入されない領域があるため、そ
の部分で基体が空乏化して、容量が減少する。しかし1
本実施例は、第2図(d)に断面を示す様に均一に不純
物が拡散されるため、容量を保つことができる。
Using the method according to the above embodiment, FIG. 2(a), (
Figure 2(C) shows the C-V (capacitance-voltage) characteristics of a MOS capacitor when a diffusion layer is formed inside the trench and on the main surface of a silicon substrate, as shown in the plane and cross section in Figure 2(C). In FIG. 2(C), the C-■ characteristics of the capacitors formed by the conventional example and the above embodiment are compared. In the conventional example, as shown in cross-sections in FIGS. 2(d) and 2(e), there is a region in the groove portion of the semiconductor substrate into which impurities are not introduced, so that the substrate becomes depleted in that region and the capacitance decreases. But 1
In this embodiment, the impurities are uniformly diffused as shown in the cross section of FIG. 2(d), so that the capacitance can be maintained.

本実施例では、MOSキャパシタの場合を説明したが、
その他の表面に開口の狭く且つ深い溝等の形状を有する
半導体基体への不純物導入工程においても発明を用いる
ことにより、均一で制御性の良い不純物拡散層を平担部
は言うにおよばず溝内部にも形成することができる。
In this embodiment, the case of a MOS capacitor was explained, but
By applying the invention to the process of introducing impurities into other semiconductor substrates with shapes such as narrow and deep grooves on the surface, a uniform and well-controlled impurity diffusion layer can be created not only on the flat parts but also inside the grooves. can also be formed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、凹形状の溝を有するシリコン基板の表
面に、高集積化に適応した。均一で制御性の良い所定導
電型を与える不純物層を形成することができる。したが
って、例えば素子領域の微細化とともに表面に形成され
る溝のアスペクト比が増々大きくなるのに対応して、そ
の微細な深い溝等の内部への不純物の拡散が可能となり
、素子の高集積化及び高速化に有効である。
According to the present invention, the surface of a silicon substrate having concave grooves is suitable for high integration. It is possible to form an impurity layer that is uniform and provides a predetermined conductivity type with good controllability. Therefore, for example, as the aspect ratio of grooves formed on the surface increases with the miniaturization of element regions, it becomes possible to diffuse impurities into the inside of the fine deep grooves, thereby increasing the degree of integration of elements. and is effective for speeding up.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による不純物導入装置の一実施例を示
す概略構成図、第2図は、本発明の実施例の効果を、M
OSキャパシタのC−■特性によって従来例と比較して
評価した結果を示す図である。 1・・・試料導入室、    2・・・不純物導入室、
3・・・試料搬出室、 4・・・第1のゲートバルブ、 5・・・第2のゲートバルブ、 6・・・第3のゲートバルブ、 7・・・第4のゲートバルブ、 8・・・シリコン基板、   9・・・ターボ分子ポン
プ、10・・・ロータリーポンプ、 11.12・・・
試料搬送装置、13・・・石英製試料台、  14・・
・赤外線ランプ、15・・・試料支持装置、  16.
17・・・バルブ。 18・・・第1のガス導入系、19・・・第2のガス導
入系。 101・・・P型シリコン基板、 102・・・ゲート絶縁膜、 103・・・ポリシリコンゲート電極、104・・・n
型不純物拡散層。 105・・・開口部の狭い、深い形状の溝。 代理人 弁理士 則 近 憲 佑 同  竹花喜久男 第2図 !府Iた1玉 イTン己1ミx三五 第2図
FIG. 1 is a schematic configuration diagram showing an embodiment of an impurity introduction device according to the present invention, and FIG. 2 shows the effect of the embodiment of the present invention by M
FIG. 3 is a diagram showing the results of evaluation in comparison with a conventional example based on C-■ characteristics of an OS capacitor. 1... Sample introduction chamber, 2... Impurity introduction chamber,
3... Sample carry-out chamber, 4... First gate valve, 5... Second gate valve, 6... Third gate valve, 7... Fourth gate valve, 8. ...Silicon substrate, 9...Turbo molecular pump, 10...Rotary pump, 11.12...
Sample transport device, 13... Quartz sample stand, 14...
- Infrared lamp, 15... sample support device, 16.
17...Valve. 18...First gas introduction system, 19...Second gas introduction system. 101...P-type silicon substrate, 102...gate insulating film, 103...polysilicon gate electrode, 104...n
type impurity diffusion layer. 105...A deep groove with a narrow opening. Agent Patent Attorney Nori Chika Ken Yudo Kikuo Takehana Diagram 2! Figure 2

Claims (13)

【特許請求の範囲】[Claims] (1)半導体基体内に導入されるべき不純物を含む化合
物ガスを容器内に導入し且つ前記容器内を排気して前記
容器内のガス圧力を大気圧以下に減圧するとともに、前
記容器内に設置された半導体基体を前記容器の内壁より
も高温にすることを特徴とする半導体基体内への不純物
導入方法。
(1) Introducing a compound gas containing impurities to be introduced into a semiconductor substrate into a container, evacuating the inside of the container to reduce the gas pressure in the container to below atmospheric pressure, and installing the compound gas in the container. A method for introducing impurities into a semiconductor substrate, the method comprising heating the heated semiconductor substrate to a higher temperature than the inner wall of the container.
(2)特許請求範囲第1項記載の半導体基体内への不純
物導入方法に於いて、減圧された不純物を含む化合物ガ
ス雰囲気に晒された前記容器内の半導体基体を加熱した
後、前記不純物を含む化合物を前記半導体基体表面ある
いはその近傍で分解し、前記不純物を前記半導体基体内
に拡散することを特徴とする半導体基体内へ不純物導入
方法。
(2) In the method for introducing impurities into a semiconductor substrate according to claim 1, after heating the semiconductor substrate in the container exposed to a reduced pressure atmosphere of a compound gas containing impurities, the impurities are introduced into the semiconductor substrate. 1. A method of introducing impurities into a semiconductor substrate, comprising decomposing a compound contained therein at or near the surface of the semiconductor substrate and diffusing the impurity into the semiconductor substrate.
(3)特許請求範囲第1項記載の半導体基体内への不純
物導入方法に於いて、減圧された不純物を含む化合物ガ
ス雰囲気に晒された容器内の半導体基体を加熱した後、
前記不純物の化合物を半導体基体表面あるいはその近傍
で分解し、前記不純物を前記半導体基体表面に堆積させ
た後、前記半導体基体を加熱処理し、前記半導体基体内
に不純物を拡散することを特徴とする半導体基体内への
不純物導入方法。
(3) In the method for introducing impurities into a semiconductor substrate according to claim 1, after heating the semiconductor substrate in a container exposed to a reduced pressure atmosphere of a compound gas containing impurities,
The method is characterized in that the impurity compound is decomposed on the surface of the semiconductor substrate or in the vicinity thereof, the impurity is deposited on the surface of the semiconductor substrate, and then the semiconductor substrate is heat-treated to diffuse the impurity into the semiconductor substrate. A method of introducing impurities into a semiconductor substrate.
(4)特許請求範囲第1項記載の半導体基体内への不純
物導入方法において、容器内に不純物を含む化合物の堆
積性ガスを導入し、減圧された前記ガス雰囲気に晒され
た前記容器内の前記半導体基体を加熱して不純物の化合
物及び堆積性のガスを前記半導体基体の表面あるいはそ
の近傍で分解反応させて、不純物を含む薄膜を表面に堆
積させ、前記半導体基体を半導体加熱処理し、不純物を
含む前記薄膜より前記に半導体基体内に不純物を拡散す
ることを特徴とする半導体基体内への不純物導入方法。
(4) In the method for introducing impurities into a semiconductor substrate according to claim 1, a deposition gas of a compound containing an impurity is introduced into a container, and the inside of the container exposed to the reduced pressure gas atmosphere is The semiconductor substrate is heated to cause a decomposition reaction of impurity compounds and deposition gas at or near the surface of the semiconductor substrate to deposit a thin film containing impurities on the surface, and the semiconductor substrate is subjected to semiconductor heat treatment to remove the impurities. A method of introducing an impurity into a semiconductor substrate, characterized in that the impurity is diffused into the semiconductor substrate through the thin film containing the above.
(5)特許請求範囲第1項記載の半導体基体内への不純
物導入方法において、減圧下で前記容器内の半導体基体
を加熱した後、不純物を含む化合物ガスを前記容器内に
導入し、不純物の化合物を前記半導体基体表面あるいは
その近傍で分解し、所望の不純物量を前記半導体基体内
に拡散導入し、しかる直後に再度前記不純物のガスを排
気することを特徴とする半導体基体内への不純物の導入
方法。
(5) In the method for introducing impurities into a semiconductor substrate according to claim 1, after heating the semiconductor substrate in the container under reduced pressure, a compound gas containing impurities is introduced into the container, and the impurity is removed. A method for removing impurities into a semiconductor substrate, characterized in that a compound is decomposed on the surface of the semiconductor substrate or in its vicinity, a desired amount of impurities is diffused into the semiconductor substrate, and immediately thereafter, the impurity gas is exhausted again. How to introduce it.
(6)特許請求範囲第1項記載の半導体基体内への不純
物導入方法において、減圧下で容器内の半導体基体を加
熱した後、不純物の化合物を含むガスを前記容器内に導
入し、不純物の化合物を前記半導体表面あるいはその近
傍で分解し、前記半導体基体表面に堆積させた後、前記
不純物の化合物のガスを排気し、しかる後に前記半導体
基体を加熱処理し、前記半導体基体内に不純物を拡散す
ることを特徴とする半導体基体内への不純物導入方法。
(6) In the method for introducing impurities into a semiconductor substrate according to claim 1, after heating the semiconductor substrate in a container under reduced pressure, a gas containing an impurity compound is introduced into the container. After the compound is decomposed on or near the semiconductor surface and deposited on the surface of the semiconductor substrate, the gas of the impurity compound is exhausted, and then the semiconductor substrate is heat-treated to diffuse the impurity into the semiconductor substrate. A method for introducing impurities into a semiconductor substrate, characterized by:
(7)特許請求範囲第1項記載の半導体基体内への不純
物導入方法において、減圧下で容器内の半導体基体を加
熱した後、前記容器内に不純物の化合物を含む堆積性の
ガスを導入し、不純物の化合物及び堆積性のガスを前記
半導体表面あるいはその近傍で分解反応させ、不純物を
含む薄膜を表面に堆積させた後、前記不純物の化合物及
び堆積性のガスを排気し、しかる後前記半導体基体を加
熱処理し、不純物を含む薄膜より前記半導体基体内に不
純物を拡散することを特徴とする半導体基体内への不純
物導入方法。
(7) In the method for introducing impurities into a semiconductor substrate according to claim 1, after heating the semiconductor substrate in a container under reduced pressure, a deposition gas containing an impurity compound is introduced into the container. , the impurity compound and the deposition gas are decomposed and reacted on or near the semiconductor surface to deposit a thin film containing the impurity on the surface, the impurity compound and the deposition gas are exhausted, and then the semiconductor 1. A method of introducing impurities into a semiconductor substrate, comprising heating the substrate and diffusing impurities into the semiconductor substrate through a thin film containing impurities.
(8)半導体基体がシリコンであることを特徴とする特
許請求範囲第2項乃至第7項に記載の半導体基体内への
不純物導入方法。
(8) A method for introducing impurities into a semiconductor substrate according to any one of claims 2 to 7, wherein the semiconductor substrate is silicon.
(9)半導体基体の表面に、開口部の最小幅が2μm以
下の溝あるいは孔が形成されていることを特徴とする特
許請求範囲第2項乃至第7項に記載の半導体基体内への
不純物導入方法。
(9) Impurities in the semiconductor substrate according to claims 2 to 7, characterized in that a groove or hole with an opening having a minimum width of 2 μm or less is formed on the surface of the semiconductor substrate. How to introduce it.
(10)前記不純物の化合物として、燐、砒素、アンチ
モン、ホウ素、もしくはガリウム等の元素の水素化物、
塩化物もしくは弗化物であることを特徴とする特許請求
の範囲第2項乃至第7項に記載の半導体基体内への不純
物導入方法。
(10) As the impurity compound, a hydride of an element such as phosphorus, arsenic, antimony, boron, or gallium;
A method for introducing an impurity into a semiconductor substrate according to claims 2 to 7, wherein the impurity is a chloride or a fluoride.
(11)半導体基体の加熱を前記半導体基体が吸収しう
るエネルギーを有する光の照射により行うことを特徴と
する特許請求範囲第2項乃至第7項に記載の半導体基体
内への不純物導入方法。
(11) A method for introducing impurities into a semiconductor substrate according to any one of claims 2 to 7, characterized in that the semiconductor substrate is heated by irradiation with light having energy that can be absorbed by the semiconductor substrate.
(12)前記不純物の化合物の分解を熱反応、光反応、
もしくは、ECR又はマグネトロンを用いたプラズマ反
応により行なうことを特徴とする特許請求範囲第2項乃
至第7項に記載の半導体基体内への不純物導入方法。
(12) Decomposition of the impurity compound by thermal reaction, photoreaction,
Alternatively, the method for introducing impurities into a semiconductor substrate according to claims 2 to 7, characterized in that the method is carried out by a plasma reaction using ECR or a magnetron.
(13)容器と、この容器内に不純物を含む化合物ガス
を導入する手段と、前記容器内を排気する手段と、前記
容器内のガス圧力を大気圧力以下に減圧する手段と、前
記容器内に設置される半導体基体を前記容器内壁よりも
高温に加熱保持する加熱手段とを具備した半導体基体内
への不純物導入装置。
(13) a container, a means for introducing a compound gas containing impurities into the container, a means for evacuating the inside of the container, a means for reducing the gas pressure in the container to below atmospheric pressure; An apparatus for introducing impurities into a semiconductor substrate, comprising: heating means for heating and maintaining the semiconductor substrate to be installed at a higher temperature than the inner wall of the container.
JP7169087A 1987-03-27 1987-03-27 Method and apparatus for introducing impurity into semiconductor substrate Pending JPS63239939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7169087A JPS63239939A (en) 1987-03-27 1987-03-27 Method and apparatus for introducing impurity into semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7169087A JPS63239939A (en) 1987-03-27 1987-03-27 Method and apparatus for introducing impurity into semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS63239939A true JPS63239939A (en) 1988-10-05

Family

ID=13467796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7169087A Pending JPS63239939A (en) 1987-03-27 1987-03-27 Method and apparatus for introducing impurity into semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS63239939A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430168A2 (en) * 1989-12-01 1991-06-05 Seiko Instruments Inc. Doping method of impurity into semiconductor trench wall
WO1993017448A1 (en) * 1992-02-25 1993-09-02 Ag Processing Technology, Inc. D.B.A. Ag Associates Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure
US5338697A (en) * 1989-12-01 1994-08-16 Seiko Instruments Inc. Doping method of barrier region in semiconductor device
US5366922A (en) * 1989-12-06 1994-11-22 Seiko Instruments Inc. Method for producing CMOS transistor
US5514620A (en) * 1989-12-01 1996-05-07 Seiko Instruments Inc. Method of producing PN junction device
US5851909A (en) * 1989-08-11 1998-12-22 Seiko Instruments Inc. Method of producing semiconductor device using an adsorption layer
US5874352A (en) * 1989-12-06 1999-02-23 Sieko Instruments Inc. Method of producing MIS transistors having a gate electrode of matched conductivity type
JP2007005828A (en) * 2000-09-14 2007-01-11 Vishay Intertechnology Inc High-precision high-frequency capacitor formed on semiconductor substrate
US9136060B2 (en) 2000-09-14 2015-09-15 Vishay-Siliconix Precision high-frequency capacitor formed on semiconductor substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60216538A (en) * 1984-04-12 1985-10-30 Fuji Electric Corp Res & Dev Ltd Diffusing method of impurity to semiconductor substrate
JPS60245218A (en) * 1984-05-18 1985-12-05 ミテル・コ−ポレ−シヨン Method and apparatus for producing semiconductor element
JPS6220306A (en) * 1985-07-18 1987-01-28 M Setetsuku Kk Controlling method for impurity diffusion layer of semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60216538A (en) * 1984-04-12 1985-10-30 Fuji Electric Corp Res & Dev Ltd Diffusing method of impurity to semiconductor substrate
JPS60245218A (en) * 1984-05-18 1985-12-05 ミテル・コ−ポレ−シヨン Method and apparatus for producing semiconductor element
JPS6220306A (en) * 1985-07-18 1987-01-28 M Setetsuku Kk Controlling method for impurity diffusion layer of semiconductor substrate

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5851909A (en) * 1989-08-11 1998-12-22 Seiko Instruments Inc. Method of producing semiconductor device using an adsorption layer
US5338697A (en) * 1989-12-01 1994-08-16 Seiko Instruments Inc. Doping method of barrier region in semiconductor device
US5514620A (en) * 1989-12-01 1996-05-07 Seiko Instruments Inc. Method of producing PN junction device
EP0430168A2 (en) * 1989-12-01 1991-06-05 Seiko Instruments Inc. Doping method of impurity into semiconductor trench wall
US5366922A (en) * 1989-12-06 1994-11-22 Seiko Instruments Inc. Method for producing CMOS transistor
US5874352A (en) * 1989-12-06 1999-02-23 Sieko Instruments Inc. Method of producing MIS transistors having a gate electrode of matched conductivity type
JP2755369B2 (en) * 1992-02-25 1998-05-20 エージー.アソシェーツ、インコーポレイテッド Gas phase doping of semiconductor materials under reduced pressure in a radiantly heated cold wall reactor
EP0628213A4 (en) * 1992-02-25 1997-02-19 Processing Technology Inc D B Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure.
US5324684A (en) * 1992-02-25 1994-06-28 Ag Processing Technologies, Inc. Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure
WO1993017448A1 (en) * 1992-02-25 1993-09-02 Ag Processing Technology, Inc. D.B.A. Ag Associates Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure
EP0628213A1 (en) * 1992-02-25 1994-12-14 Ag Associates, Inc. Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure
JP2007005828A (en) * 2000-09-14 2007-01-11 Vishay Intertechnology Inc High-precision high-frequency capacitor formed on semiconductor substrate
EP1895569B1 (en) * 2000-09-14 2013-06-12 Vishay Intertechnology, Inc. Precision high-frequency capacitor formed on semiconductor substrate
EP1895568B1 (en) * 2000-09-14 2014-07-16 Vishay Intertechnology, Inc. High-frequency capacitor formed on semiconductor substrate
US9136060B2 (en) 2000-09-14 2015-09-15 Vishay-Siliconix Precision high-frequency capacitor formed on semiconductor substrate

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