JPS63239860A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the occupying area per one memory cell and to highly integrate memory cells by providing the plate electrode of a capacitor and the gate electrodes of an MISFET planarly substantially in close contact. CONSTITUTION:Many grooves (recesses)1a having, for example, rectangular sectional shape are formed on a semiconductor substrate 1. A word line WL is formed through an insulating film 3 on the substrate 1 at (protrusions) between grooves 1a, and electrodes 4 are formed through the film 3 in the bottom of the groove 1a. The word line WL and electrodes 4 are formed, for example, of films superposed with metal film of W, Mo, T, Ti, etc., or their silicide film, or metal film or its silicide film on a polycrystalline silicon film. These word line WL and the electrode 4 are provided in close contact as seen planarly, and the occupying area per one memory cell can be reduced as compared with a planar type memory cell. Thus, the memory cells can be highly integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a highly integrated semiconductor integrated circuit device having memory cells.

[Prior art]

Conventionally, dynamic RAM (Random Access
A planar type memory cell is known as a memory cell for ss memory (for example, Nikkei Electronics, June 3, 1985 issue, p. 219).This planar type memory cell usually stores information as a charge. It consists of a capacitor for charging and an n-channel MISFET for taking out and taking out this charge. This capacitor includes a semiconductor substrate, an insulating film formed on the surface of the semiconductor substrate,
It is composed of a plate electrode provided on this insulating film. in this case.

Usually, n is present in the p-type semiconductor substrate below the insulating film.
A °-type semiconductor region and a p-type semiconductor region are provided, and the storage capacitance is increased by the junction capacitance between these semiconductor regions. That is, the capacitor has a so-called Hi
-C structure (for example, Japanese Patent Application No. 60-8639
No. 3), the p-type semiconductor region prevents electrons generated in the semiconductor substrate from entering the n-type semiconductor region when alpha rays or the like enter the memory cell, thereby preventing the occurrence of soft errors. It also plays a role in prevention.

[Problem that the invention seeks to solve]

However, in the conventional planar memory cell described above, the word line forming the gate electrode of the MISFET and the plate electrode of the capacitor are provided quite apart from each other, so the area occupied by each memory cell is large. There has been a problem in that it is difficult to increase the integration density of memory cells.

An object of the present invention is to provide a technology that can achieve high integration density of memory cells.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the plate electrode of the capacitor and the gate electrode of the MISFET are provided in close contact with each other in plan view.

[Effect]

According to the above-described means, since the plate electrode and the gate electrode are provided close to each other, the area occupied by each memory cell is reduced, so that it is possible to achieve a high integration density of the memory cells.

〔Example〕

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

Figure 1 shows a dynamic RAM according to Embodiment I of the present invention.
FIG. 2 is a cross-sectional view taken along the line X-X in FIG. 1, and FIG. 3 is a plan view of the main part of the dynamic RAM shown in FIGS. FIG. 3 is a circuit diagram showing an equivalent circuit.

As shown in FIGS. 1 and 2, in the dynamic RAM according to Embodiment I, an element isolation region 2 made of, for example, a p4 type semiconductor region is provided on the surface of a semiconductor substrate 1 such as a p type silicon substrate. It is being Note that isolation between elements may be achieved by providing a groove on the surface of the semiconductor substrate 1 and filling this groove with oxide (Sins), or by selectively thermally oxidizing the surface of the semiconductor substrate 1. The surface of the semiconductor substrate 1 is provided with a large number of grooves (concave portions Ha) having, for example, a substantially rectangular cross-section. Reference numeral 3 indicates an insulating film such as a Sun film. A word line WL is provided on the surface of the semiconductor substrate 1 between the grooves 1a (convex portions) via the insulating film 3, and an electrode 4 is provided at the bottom of the groove 1a via the insulating film 3. These word lines WL and electrodes 4 are formed by forming a metal film such as tungsten, molybdenum, tantalum, titanium, etc., a silicide film thereof, or a polycrystalline silicon film on which the metal film or its silicide film is formed. These word lines WL and electrodes 4 are arranged in close proximity to each other when viewed from above, and therefore the area occupied by each memory cell is smaller than that of a conventional planar memory cell. Therefore, it is possible to achieve a high integration density of memory cells.

On the other hand, a portion of the semiconductor substrate 1 adjacent to the groove 1a
For example, n-type semiconductor regions 5a and 5b are provided therein, and a p-type semiconductor region 6a, for example, is provided to cover these semiconductor regions 5a and 5b.

6b is provided. Then, the word line WL is used as a gate electrode, the semiconductor regions 5a and 5b are used as a source region and a drain region, and, for example, an n
A channel MISFET T is configured. Further, a capacitor C is constituted by the one electrode 4, the insulating film 3 which is a dielectric film, and the semiconductor region 5a which is the other electrode. This capacitor C has a storage capacity increased by the junction capacitance between the semiconductor regions 5a and 6a.
It has a li-C structure. These capacitors C and n-channel MISFET T constitute a memory cell. Note that memory cells adjacent to each other in the direction in which a bit line BL (described later) extends are connected to each other by a semiconductor region 5b. This semiconductor region 5b is set to the ground potential Vss or power supply potential Vcc of one circuit as shown in FIG. 3 (see FIG. 3). Further, since the n-type semiconductor regions 5a and 5b are completely covered by the p0-type half regions 6a and 6b, electrons generated in the semiconductor substrate 1 when alpha rays or the like are incident on the memory cell. can be effectively prevented from entering the semiconductor regions 5a, 5b. Therefore, the soft error resistance can be improved. Furthermore, the p-type semiconductor regions 6a and 6b allow MI
Since the breakdown voltage (bunch-through voltage) between the source and drain of SFET T is increased, the channel length can be shortened. Therefore, there is no problem even if the n-type regions 5a and 5b wrap around under the gate electrode (WL).

Furthermore, the code 7 is an insulating film (1) such as a 5in2 film, for example.
(not shown in FIG. 1), and a large number of bit lines BL made of, for example, an aluminum film are provided through contact holes 7a provided in this insulating film 7.

Next, an example of a method for manufacturing a dynamic RAM according to the embodiment (2) configured as described above will be explained.6 As shown in FIG. After forming a mask (not shown), p-type impurities such as boron are ion-implanted into the semiconductor substrate 1 at a high concentration using this mask.

Next, after removing the mask, a mask 8 such as a Sin film having a predetermined shape is formed on the semiconductor substrate 1, and this mask 8 is used to form the semiconductor substrate 1. By sequentially ion implanting an n-type impurity such as arsenic and a p-type impurity such as boron into the material.

Semiconductor regions 5a, 5b, 6a, and 6b are formed in self-alignment with respect to the mask 8. by this.

Since the semiconductor region for increasing the storage capacity of the capacitor C and the source region and drain region of the n-channel MI 5FET can be formed at the same time, the manufacturing process can be simplified.

Next, the semiconductor substrate 1 is anisotropically etched in a direction perpendicular to the surface by anisotropic etching such as reactive ion etching (RIE) using the mask 8, as shown in FIG. , grooves 1a are formed in self-alignment with respect to the mask 8. Thereafter, the mask 8 is removed by etching.

Next, as shown in FIG. 2, the surface of the semiconductor substrate 1 is insulated by, for example, thermal oxidation. After forming I3.

For example, the word line WL and the electrode 4 are formed in a self-aligned manner by depositing metal over the entire surface using a directional deposition technique (for example, cluster ion beam deposition). In this case, these word lines WL and electrodes 4
Vapor deposition conditions, grooves 1a, etc. are selected so that word lines WL and electrodes 4 are formed in a state where they are separated from each other without being connected at the side wall of groove 1a. Conventionally, these word lines WL and electrodes 4 were formed in separate processes. However, according to this embodiment, since these word lines WL and electrodes 4 are formed at the same time as described above,
The manufacturing process can be simplified.

Next, after forming an insulating film 7 on the entire surface, a predetermined portion of this insulating film 7 is removed by etching to form a contact hole 7a.First, an aluminum film, for example, is formed on the entire surface, and then this aluminum film is etched. The bit lines BL are formed by patterning, thereby completing the intended dynamic RAM.

Figure 6 shows the dynamic RAM according to the embodiment of the present invention.
FIG. 7 is a sectional view taken along line Y-Y in FIG. 6. FIG. Note that the memory cell of the dynamic RAM according to this embodiment (2) has a similar low-level circuit as shown in FIG.

As shown in FIGS. 6 and 7, in the dynamic RAM according to the embodiment (2), lla on the surface of the semiconductor substrate 1
A word line WL made of, for example, polycrystalline silicon is provided on both side walls of the groove 1a with an insulating film 3 interposed therebetween. Further, an electrode 4 made of, for example, a polycrystalline silicon film is provided on the semiconductor substrate 1 between 1 WtLa and an insulating film 8 interposed therebetween. The word AIWL and the semiconductor regions 5a and 5b constitute an n-channel MISFET T. This MISFET
At T, the semiconductor substrate 1 at the side wall portion of the groove 1a
channels are induced in the The word line WL and the electrode 4 are provided in close contact with each other, and since the word line WL is provided on the side wall of the groove 1a, its occupied area is small. The area occupied by each can be reduced, and therefore the number of SFETs on the memory cell can be increased. Also,
As in Example I, the semiconductor regions 5a and 5b are completely covered by the semiconductor regions 6a and 6b, so that the soft error resistance can be improved.

Next, an example of a method for manufacturing the dynamic RAM according to the embodiment (2) configured as described above will be described.

As shown in FIG. 7, the steps are carried out in the same manner as described in Example I until the step of forming the insulating film 3 on the surface of the semiconductor substrate 1 is completed.Next, for example, a polycrystalline silicon film is formed on the entire surface, After this polycrystalline silicon film is doped with an n-type impurity such as phosphorus to lower its resistance, a photoresist 9 having a predetermined shape, for example, is formed on this polycrystalline silicon film.

Next, using photoresist 9 as a mask, the polycrystalline silicon film is anisotropically etched by, for example, RIE, thereby forming electrodes 4 at the same time as word lines WL. As a result, the manufacturing process can be simplified compared to the conventional case where the electrode 4 and the word line WL are formed in separate steps. Insulating film 7, contact hole 7a, and bit line BL are formed in the same manner as described above to complete the intended dynamic RAM.

Figure 8 shows a dynamic RAM according to an embodiment of the present invention.
FIG. 9 is a sectional view taken along the Z-Z line in FIG. 8, and FIG. 10 is a plan view of the main parts.

FIG. 10 is a circuit diagram showing a low level circuit of a memory cell of the dynamic RAM shown in FIGS. 8 and 9; FIG.

As shown in FIGS. 8 and 9, in the dynamic RAM according to the embodiment (2), one word line WL is provided inside the groove 1a provided on the surface of the semiconductor substrate 1, and this groove 1a An electrode 4 is provided on the surface of the semiconductor substrate 1 between them with an insulating film 3 interposed therebetween. This example ■
Even in.

The channel of the n-channel MISFET T is induced on the side wall of the groove 1a. Note that the word line WL is common to a pair of memory cells adjacent to each other in the direction in which the bit line BL extends. These word lines WL and electrodes 4
are provided in close proximity to each other as in Example ■,
This makes it possible to achieve a high integration density of memory cells. Further, the semiconductor regions 5a and 5b are replaced by a semiconductor region 6a,
Since it is completely covered with 6b, the soft error resistance can be improved. Furthermore, two bit lines BL are provided in parallel to each other on each memory cell, and electrodes 4 of capacitors C in memory cells adjacent to each other in the direction in which these bit lines BL extend are provided alternately through contact holes 7a. Different bit lines BL are in contact with each other.

Next, an example of a method for manufacturing the dynamic RAM according to the embodiment (2) configured as described above will be described.

As shown in FIG. 9, the steps are carried out in the same manner as described in Example 2 until the step of forming the insulating film 3 on the surface of the semiconductor substrate 1 is completed. Next, a polycrystalline silicon film, for example, is formed on the entire surface, and this polycrystalline silicon film is doped with an n-type impurity such as phosphorus to lower the resistance, and then a predetermined shape is formed on this polycrystalline silicon film. For example, a photoresist 9 is formed.

Next, using this photoresist 9 as a mask, the polycrystalline silicon film is anisotropically etched by, for example, RIE, so that the surface of the polycrystalline silicon film in the groove 1a is almost at the same height as the surface of the semiconductor substrate 1. At the same time, the electrode 4 is formed. As a result, the primary order which can simplify the manufacturing process as described in Example I,
After removing the photoresist 9, the insulating film 7. is formed in the same manner as described in Example I. A contact hole 7a and a bit line BL are formed to complete the intended dynamic RAM.

Figure 11 shows a dynamic RA according to an embodiment of the present invention.
FIG. 12 is a plan view of the main part of M, and FIG.
FIG. 3 is a cross-sectional view along the line. Note that, unlike the circuit shown in FIG. 3, in the memory cell of the dynamic RAM according to this embodiment (2), the semiconductor region 5b of the MISFETT is connected to the bit line BL, while one electrode 4 of the capacitor is connected to a fixed potential (for example, 1/2 Vcc potential) is applied.

As shown in FIGS. 11 and 12, in the dynamic RAM according to the embodiment (2), MI
SFET T and capacitor C are formed. MISF
In order to connect ET T and bit line BL, MISF
A contact hole 7a is formed in the insulating film 7 on the ETT. At this time, to prevent short circuit between word line WL and bit line BL.

The surface of the word line WL is insulated! Covered by 10. The insulating film 10 is formed, for example, by etching a Si film formed by CVD into a predetermined shape by RIE. On the other hand, the electrode 4 is formed as a common electrode for a plurality of memory cells. That is, it is formed except for the inside of the groove 1a where the MISFET T is formed. Note that isolation between capacitors and the like of adjacent memory cells is achieved by a thick silicon oxide film 2 formed by selective thermal oxidation of the surface of the substrate 1. Also, insulation l
A p'-type channel stopper is formed in the substrate 1 below lA2. Thereby, the double-type semiconductor region is also made into a continuous semiconductor region common to a plurality of memory cells.

[S] 11th brother Fig. 13 shows the dynamic RA according to the embodiment ① of the present invention.
FIG. 14 is a plan view of the main part of M, and FIG.
FIG. 3 is a cross-sectional view along the line. Note that the memory cell of the dynamic RAM according to this embodiment (2) has an equivalent circuit similar to that of the embodiment (2).

As shown in FIGS. 13 and 14, in the dynamic RAM according to the embodiment (2), a wide groove 1a is provided on the surface of the semiconductor substrate 1, and an insulating film 3 is formed on both side walls of the groove 1a.
Word lines WL made of, for example, polycrystalline silicon are provided through the respective word lines WL. An electrode 4 made of, for example, a polycrystalline silicon film is provided at the bottom of the trench 1a with an insulating film 3 interposed therebetween. On the surface of the semiconductor substrate 1 between the electrodes 1lla, n-type and P'' type semiconductor regions 5b and 6b are formed, while on the semiconductor substrate 1 under the electrode 4, n'' type and p'' type semiconductor regions 5a are formed. and 6a are formed by the word fiWL and the semiconductor regions 5a and 5b.

An n-channel MISFET T is configured.

In this MISFET T, a channel is created in the semiconductor substrate 1 at the sidewall portion of the trench 1a. electrode 4,
The insulating film 11110, the insulating film 2, and the channel stopper thereunder are substantially the same as in Example (2).

In this example, the step of the contact hole 7a for connecting the MISFET T and the bit line BL is the same as that in the embodiment
It's smaller.

In the embodiments (1) and (2), the area occupied by each memory cell can be reduced as in the other embodiments, and therefore the memory cells can be integrated at a high density. Also,
Since the semiconductor regions 5a and 5b are completely covered by the semiconductor regions 6a and 6b, the soft error resistance can be improved.

The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in each embodiment, the p-type region 6a or 6
b can be omitted 6 In the present invention, dynamic R
The present invention can be applied to various semiconductor integrated circuit devices having memory cells other than AM.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it is possible to achieve high integration density of memory cells.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 shows a dynamic RAM according to Embodiment I of the present invention.
A plan view of the main parts. FIG. 2 is a sectional view taken along the line XX in FIG. 1. Figure 3 shows the dynamic RAM shown in Figures 1 and 2.
FIG. 3 is a circuit diagram showing an equivalent circuit of a memory cell. 4 and 5 are cross-sectional views for explaining an example of a method for manufacturing the dynamic RAM shown in FIGS. 1 and 2 in order of steps. FIG. 6 shows a dynamic RAM according to an embodiment of the present invention.
A plan view of the main parts. FIG. 7 is a sectional view taken along line Y-Y in FIG. 6. FIG. 8 shows a dynamic RAM according to the embodiment ① of the present invention.
FIG. 9 is a sectional view taken along the Z-Z line in FIG. 8. FIG. 10 shows the dynamic RA shown in FIGS. 8 and 9.
A circuit diagram showing an equivalent circuit of a memory cell of M, FIG. 11 is 1
FIG. 2 is a plan view of a main part of a dynamic RAM according to an embodiment (2) of the present invention. FIG. 12 is a sectional view taken along the Y-Y line in FIG. 11, and FIG. 13 is a dynamic RA according to the embodiment
FIG. 14 is a sectional view taken along the line Y--Y in FIG. 13. In the figure, 1... semiconductor substrate, 2... element isolation region,
3.7... Insulating film, 4... Electrode, 5a, 5b, 6
a, 6b...Semiconductor region, WL...Word line, BL
...It's a bit line. ).゛ 1 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 10 Figure 11

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a memory cell consisting of a capacitor and a MISFET, wherein one electrode of the capacitor formed on a semiconductor substrate and the MISFE
A semiconductor integrated circuit device characterized in that gate electrodes of T and T are provided substantially close to each other in a planar view. 2. The semiconductor integrated circuit device according to claim 1, wherein one electrode of the capacitor is provided at the bottom of a groove provided on the surface of the semiconductor substrate. 3. The semiconductor integrated circuit device according to claim 1, wherein the gate electrode is provided inside a groove provided in a surface of a semiconductor substrate. 4. The semiconductor integrated circuit device according to claim 3, wherein the gate electrode is provided on a side wall of the trench. 5. The semiconductor integrated circuit device according to claim 1 or 2, wherein one electrode of the capacitor and the gate electrode are made of a metal film formed by vapor deposition. 6. In order to increase the storage capacity of the capacitor, a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type are provided in the semiconductor substrate, and the semiconductor region of the first conductivity type and the source region of the MISFET or 6. The semiconductor integrated circuit device according to claim 1, wherein a drain region is covered by the second conductivity type semiconductor region. 7. The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein the semiconductor integrated circuit device is a dynamic RAM.