JPS63239690A - Read-only memory - Google Patents

Abstract

PURPOSE:To speed up reading operation by connecting a depression type load MOSFET whose gate receives the earth potential of a circuit between a data line of a memory array and a power supply voltage and reading out the contents of the MOSFET by an amplifying MOSFET. CONSTITUTION:One memory cell in a mask ROM is constituted of a pair of N<+>-type semiconductor areas 1 to be used as source areas or drain areas and a MOSFETQm provided with a gate insulating film 2 and a gate electrode 3. The semiconductor areas 1 are formed on the surface of a semiconductor substrate consisting of P<->-type silicone monocrystal. A voltage lower than the power supply voltage is impressed on the drain area of the MOSFETQm, i.e. a data line. Thereby, the depression type MOSFET whose gate receives the earth potential is connected to the data line as a load. Since the potential of the data line can be stabilized by the load means, information can be rapidly read out.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in mask-type ROMs (read-only memories) in which information is written by implanting impurity ions through a gate electrode.

[Conventional technology]

A storage MOS FET (metal insula) is installed at the intersection of the word line and the data line according to the storage information.
terSemlconductor Fleld Ef
A horizontal mask-type ROM that forms a transducer (translator) is known (for example, Sanpo Publishing ■, 1
(See "How to Use IC Memory," co-authored by Matsuo Shinde and Ryo Oomote, September 30, 1977, pp. 73-76).

As one of these horizontal mask ROMs, electronic
X (Electronic), May 3, 1983
A mask ROM described in P50 to P51 of the 1st is known. In this mask ROM, after forming a data line made of an aluminum film, a MOSFE, which is a memory cell, is
Impurities are introduced into the channel region of T by ion implantation through the gate electrode (and glabellar insulating film). This raises (or lowers) the threshold voltage of the MOSFET, so that information is stored.

In this mask ROM, information can be written after forming data lines and source lines near the end of the manufacturing process, so the time required to complete manufacturing can be shortened.

[Problem that the invention seeks to solve]

As a result of studies on this technology, the inventor found that the following problems occur.

The impurities are selectively implanted using a mask made of a photoresist film. The opening of this photoresist)-r screen is configured to have a larger size than the channel forming region in consideration of mask misalignment. For this reason, M.O.
The impurity is also introduced into the main surfaces of the source and drain regions adjacent to the channel of the SFET. Since this introduction of impurities is performed with high energy, crystal defects are generated at the pn junction interface portions of the source and drain regions. Crystal defects cannot be sufficiently recovered because heat treatment can only be performed at a low temperature of about 450° C. to prevent the data line made of aluminum from melting. Therefore, the gate voltage is o at the pn junction surface of the drain region.
When V, a leakage current flows that has a dependence on the drain voltage.

This leakage current flowing from the drain region to the substrate increases as the drain voltage increases. Additionally, leakage current increases with device usage time and degradation time decreases. This phenomenon is remarkable when a negative bias voltage is applied to the substrate.

An object of the present invention is to provide a technique that can reduce leakage current caused by the process of writing information into a ROM.

Another object of the present invention is to provide a technology that can extend the life of a ROM.

Another object of the present invention is to provide a technique capable of reducing power consumption of a ROM.7 Another object of the present invention is to provide a ROM capable of high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

A voltage lower than a power supply voltage (operating voltage) is applied to the drain region of a MOSFET that is a memory cell, that is, a data line. For this purpose, a dipleg MOSFET whose gate receives a ground potential is connected to the data line as a load.

[Effect]

By the means described above, it is possible to reduce the leakage current generated in the pn junction of the drain region.
The deterioration time can be lengthened.

Further, it is possible to reduce power consumption and prevent latch-up. Further, since the load means can stabilize the potential of the data line, information can be read out at high speed.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a mask type ROM to which the present invention is applied. Although not particularly limited, this ROM is formed on a single semiconductor substrate such as single crystal silicon using a known 0M08 circuit manufacturing technique. Although not particularly limited, this ROM is formed on a semiconductor substrate made of single-crystal P-type silicon. An N-channel MOSFET is composed of a source region and a drain region formed on the surface of such a semiconductor substrate, and a gate electrode formed on the surface of the semiconductor substrate (channel region) between the source region and the drain region with a thin gate insulating film interposed therebetween. be done. The P-channel inter-channel O8FET is formed in an N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N-channel MOSFETs forming memory cells and peripheral circuits formed thereon.
Constitutes a common substrate gate for ET. Although not particularly limited, in this embodiment, a negative bias voltage (
A substrate bias voltage) VBB (for example, -3V) is applied. Bias voltage VIB is generated by bias voltage generation circuit VG.
generated by. The configuration of the voltage generating circuit VG is the same as a known one, so a description thereof will be omitted. The N type reel region is formed on the P channel O8F formed thereon.
Configures the substrate gate of ET.

The memory array M-ARY includes a plurality of word lines WO to Wn arranged in the horizontal direction and a plurality of data lines (bit lines or digit lines) D00 to DOI arranged in the vertical direction. and a storage MOSFET Qm placed at the intersection of these.

In this embodiment, although not particularly limited, the advantages of high density storage elements and low power consumption during read operation,
t) Chi/! D00. A common source line C8O is provided between and parallel to D10. The common source line C8O has a corresponding data line DO.
Memory MOSF whose drain is connected to O,DIO
The sources of ETQm are commonly connected. Further, the data line D10 has an adjacent common source line C8I.
The drains of the storage MOSFETQm whose sources are coupled to are commonly connected. The above common source line C81
The drain of the other storage MOSFETQm corresponding to is connected to data 1DO1. The drains of storage MOSFETQm whose sources are coupled to a common source line C82 provided next to the data line Dot are commonly coupled to this data line Dot.

The data lines and common source lines C8 are arranged alternately. The data lines, excluding the data line DOO at the end, are commonly connected to the drains of two (two columns) storage MOSFETs Qm assigned different Y addresses on both sides thereof.

That is, data line DOO is coupled to common data line CDO via MOSFET QI 1 forming a Y gate (power switch). The common source line C8O corresponding thereto is coupled to the ground potential Vss (OV) of the circuit via the switch MOSFET QI2. Another data line DIO corresponding to the common source line C8O is coupled to the common data line CDI via a MOSFET Q13 forming a Y gate. These switch MOSFETs
A selection signal YO formed by a Y decoder circuit YDCR, which will be described later, is commonly supplied to the gates of Q11 to Q13.

The data line DIO also has another Y address (Yl)
MOSFETQI that constitutes the Y gate assigned
4 to the common data line CDI. Common source line C8I placed on the right side of the data line DIO
is coupled to the circuit ground potential VgBK via the switch MO3FET QI5. The data line DOI arranged on the right side of this common source line C3I is connected to the common data line CD0I through a MOSFET QI6 that constitutes a Y gate.
C-coupled. A selection signal Y1 formed by the Y decoder circuit YDCR is supplied to the gates of these MOSFETs Q14 to Q16. Thereafter, data lines, common data lines, and switch MOSFETs are formed by repeating similar patterns.

The gates of the storage MOSFETs arranged in the same row are respectively coupled to the corresponding word lines WO to Wn. Word lines WO to Wn are each supplied with a selection signal formed by an X decoder circuit XDCR, which will be described later.

In this embodiment, depletion type N-channel MOSFETs QI to Q7 are provided between the data lines DOO to Dol and the common source lines C8O to C82, etc., and the power supply voltage (circuit operating voltage) Vcc (5V). . In fact, as described later, MOSFET
P channel M is connected between QI to Q7 and power supply voltage VCC.
OS F ETQ33 is connected. Above data #DO
Depletion type MOS compatible with O or DOI
FETQ1, Q3. Q5. Q7 and the like supply a bias voltage to the data line and act as its load means. Depletion type MOSFETQ2, Q4, Q6, etc. compatible with common source @CSO or C82 are as follows:
It acts as a MOSFET that supplies a bias voltage that sets the common source line to a non-select level (high level).

For example, by the Y decoder circuit YDCR, the selection signal Y1
is formed, switch MOSFETs Q14 to Q1.6 are turned on, thereby causing data lines D10. DO1 and common source line C81 are selected. In this case, storage MOSFs are arranged between the data lines DIO and DOI and the common source line C8I.
Only ET must be selected. but,
When the potential of the common source lines C8O and C82 is set to a low level like the ground potential of the circuit, the data line DIO
The storage information of the storage MOSFET arranged between the common source line cso and the data line DOI and the common source line C82 also appears on the data lines DIO and DOI.

Therefore, by providing the above-mentioned deplunging MIMOSFETs Q2, Q4, and Q6 on the common source line as described above, only the selected common source line C8O is given the circuit ground potential by the switch MOSFET Q15, and the non-selected By making the potential of the common source lines C8O and C82 equal to the bias potential of the data line, the data lines DIO and DOI and the common source lines C8O and C
This is to turn off the storage MOSFET disposed between the storage MOSFET 82 and the storage MOSFET 82, regardless of the storage information.

The load means can also be seen as voltage limiting means or voltage clamping means for limiting the voltage applied to the data 111D00 to Dot.

MOSFETQ1. , Q3, Q5, Q7, etc. essentially act as resistive elements, and the power supply voltage VC is reduced by the voltage drop.
A voltage lower than C is supplied to data lines DOO to DOI.

The load means may be composed of a P-channel MOSFET, and its composition may be composed of various known voltage limiting circuits. This load means applies a voltage lower than the power supply voltage VCC, that is, the high level signal of the binary signal, to the data line DOO.
-DOIK is applied. As will be described later, a voltage of approximately 3.5 or less, for example approximately 2V, is applied to the data lines DOO to DO.
applied to I.

When the MOSFETs QI to Q7 are ion-implanted with an N-type impurity, such as arsenic, into the substrate and annealed, the MOSFETs QI to Q7 have a depression w7FJ due to K.

This ion implantation was performed at 100 KeV, 2.7
It is carried out at a dose of oms/d.

In an embodiment in which the load means has a reference voltage of the circuit at its gate, it is a depletion-free type MOS that receives the ground potential of the circuit.
Since it is composed of FETs, it has the following effects. That is, since the only process element that determines the voltage drop in the load means is the arsenic dose described above, it is less susceptible to process-related variations. An appropriate voltage drop can be obtained with a smaller area than when the load means consists of a resistor. Since the bias voltage to the gate is the reference potential, the variation in the bias voltage is smaller than when the bias voltage is the power supply potential VCC or an intermediate potential between VCC and WaS. Therefore, fluctuations in the current flowing through the data line are small.

In addition, since it can be regarded as a stable constant current source, the power supply potential VCC
Even if the current flowing through the data line fluctuates, the current flowing through the data line does not easily fluctuate.

Similarly, the non-select level bias voltage applied to the common source line is applied to the MOS as a load means or voltage limiting means.
The power supply voltage VCC is controlled by FETQ2, Q4 and Q6, etc.
A lower voltage (approximately 2V in this example) is applied. Similarly, the potential of the common source line is made stable.

Actually, in order to reduce power consumption, a switch means, for example, a P-channel MOSFET Q33, controlled by the predecode signal SB and the internal chip selection signal C8 is connected between the load means and the power supply voltage VCC. Similarly,
Signals C8 and SB are connected between the load means and ground potential va8.
A switch means controlled by, for example, an N-channel MOSFET Q34 is connected. The two switch means are operated complementarily, i.e. MOS F
ETQ33 and Q34 constitute a CMOS inverter. This inverter is driven by a known two-man power CMOS NAND gate circuit G1.

Signal C8 is generated in timing generation circuit TG based on chip selection signal C8. When a chip is selected by the low level of the signal C8, the signal C8 is set to the high level.

Signal SB is generated in predecode circuit PD based on some Y address signals described later. One of six predetermined signals among the plurality of bits of the signal SB is input to a predetermined gate circuit G1. As shown in Figure 1, one CMOS inverter and one gate circuit G
1 is provided corresponding to a plurality of data lines and a common source line C8. In other words, one memory array M-ARY
But multiple data, 1! It is divided into memory blocks including D, and a CMOS inverter and a gate circuit Gl are provided for each memory block. By selectively setting one bit of the plurality of bits of the signal SB to a high level, a bias voltage is selectively supplied to one memory block. Details will be explained later using FIG. 2.

When the chip is not selected, the signal C8 is low level, so the MOS
FETQ34'), all data t! J! The potential of D and all the common source lines C8 is set to the ground potential vB8.

This makes it possible to reduce power consumption when a chip is not selected, that is, to reduce standby current.

When selecting a chip, the signal C8 becomes high level.

Therefore, the bias voltage is supplied by the MOSFET Q33 only to the memory block corresponding to the high level of the signal SB. On the other hand, no bias voltage is supplied to the remaining memory blocks corresponding to the low level of the signal SB. That is, the potentials of the data lines of the remaining memory blocks and the common data line C8 are set to the ground potential Vss+ by the MOSFET Q34. This makes it possible to reduce power consumption during chip selection.

Addressing of the mesorial array M-ARY having the above configuration is performed by the following circuit blocks.

An X address signal AX consisting of multiple bits supplied from an external terminal is supplied to an X address buffer XADB,
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These complementary address signals are decoded by an X decoder XDCR, which forms a selection signal for one word line. In this example, the above
The address buffer XADB and the X dehooder XDCR are collectively expressed as XADB-DCR.

In this embodiment, although not particularly limited, the word line selection signal (high level signal) also has a value lower than the power supply potential.
For example, it is set to 2.5v. Thereby, the current value flowing through the memory cell (that is, the sense amplifier) to which the limited drain voltage is supplied can be set to an appropriate value. For this purpose, the X address buffer yXADB includes word line voltage limiting means. This voltage limiting means may consist of known means.

A Y address signal AY consisting of a plurality of pits supplied from an external terminal is supplied to a Y address buffer YADB.
A complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an internal address signal in opposite phase is formed.

These complementary address signals are decoded by Y decoder YDCR, and selection signals for two data lines are formed by Y decoder YDCRK. In this example, the above Y
The address buffer YADB and Y decoder YDCR are collectively expressed as YADB-DCR.

Address buffer and decoder XADB-DCR,Y
ADB-DCR is a timing generation circuit TG.
It is brought into operation by a timing signal (not shown) generated based on signal C8.

and tL et al.'s circuits XADB, YADB, and XDCR.

YDCR has the same configuration as the known 0M08 circuit.

Note that in the read operation, only one common source line corresponding to the selected data line is set to the ground potential, and the other common source lines are kept at the bias potential. Therefore, even though a large number of storage MOSFETs are connected to one word line, the data line is connected to the selected storage MOSFET.
Since the current according to the stored information flows only through the ET, it is possible to reduce power consumption. Furthermore, storage MOSFETs to which different Y addresses are assigned to data lines can be combined by a selection operation according to the Y address of the common source line, so that storage MOSFETs can be arranged at high density.

The structure of the mask ROM shown in FIG. 1 is shown in FIGS. 3 and 4. FIG. 4 is a sectional view taken along the line A--A in FIG. 3. In FIG. 3, in order to simplify the drawing, the insulating film 2
, 9 and 15 are omitted.

One memory cell of the mask ROM in FIG. 1 consists of a pair of nu semiconductor regions l used as a source region or a drain region, a gate insulating film (810 mm) 2, and a gate insulating film (810 mm) 2).
is constructed using one MOSFETQm with pole 3. The semiconductor region 1 is provided on the surface of a semiconductor substrate 4 made of p-W silicon single crystal. Adjacent MOS
The FETQm are electrically isolated by a field insulating film 5. The gate electrode 3 is disposed on the field insulating film 5 and constitutes a word line W. The gate electrode 3 (and the word 41jW) has a polycide structure composed of a polycrystalline silicon layer 3A and a molybdenum silicide (or silicide of a high melting point metal such as tungsten, titanium, or tal) layer 3B provided on the polycrystalline silicon layer 3A. have 7 is a conductive layer made of aluminum and has data #! D or common source @CS, and is connected to the semiconductor region 1 through a contact hole 8 formed in the glabellar insulating film 9.

The insulating film 9 is made of, for example, a silicon oxide film, a silicon nitride film, and a phosphor silicate glass (PSG) film in order at 1ta.
It becomes ak. A data line is connected to region 1, which is a common drain for four memory cells. A common source line C8 is connected to region 1 which is a common source for four memory cells. Since ion implantation is performed through the gate electrode 3, the aluminum layer 7 does not exist on the gate electrode 3. The opening 13 has a lower MO
In order to introduce an impurity, for example, boron, which is a p-type impurity, into SFETQm, the interlayer Rg9 is partially removed by etching. The introduced impurity is activated by annealing to form a p-type semiconductor region 14. The threshold voltage of the MOSFETQ into which p-type impurities are introduced is higher than the threshold voltage of the other 17) MOSFETQm. 15 is a protective film made of, for example, a silicon oxide film, and the semiconductor substrate 4 formed to cover the top of the

The storage MOSFETQm is made to have different threshold voltages according to storage information. Although not particularly limited, a storage MOSF to which logic "'l" is written
The ET is implanted into the semiconductor substrate (channel region) 4 under the gate electrode 3 through the opening 13 by selective ion implantation technique (with the resist mask for forming the opening 13 left). An impurity (boron) of the same conductivity type as the semiconductor substrate 4 is introduced. As a result, 2.
0V~3. It is made to have a relatively high threshold voltage such as Ov. The writing process using such ion implantation technology is the final process of a semiconductor integrated circuit formed on a semiconductor wafer, for example, after forming a data line or a common source line C8 made of an aluminum layer, it is a memory cell. 0.0 through the gate electrode 3 of MOSFETQm.
8-1. Boron (B
) is carried out by the ion implantation process. Since the insulating film 9 remains for avoidance of contamination due to ion implantation or gettering of impurities, and the gate electrode 3 is thick with polycide, high-energy ion implantation is performed. This causes defects in the substrate. Also, since annealing can only be performed at low temperatures (approximately 450°C or less),
Defects caused by activation of impurities and ion implantation cannot be fully recovered. This causes increased leakage current in the memory cell and breakdown voltage at the drain junction. In addition, the amount of impurities reaching the channel region is small and splattered. Therefore, the threshold voltage of the memory MOSFET Qm to which the above writing has been performed is set to be relatively low, such as 2 to 3 V, and the thickness of the gate electrode 3 and the remaining interlayer insulating film 9 formed on its surface is It is assumed that there is a relatively large variation due to variations. On the other hand, the above writing is not performed (logical “0”)
The threshold voltage of the storage MOSFET is set to a relatively low voltage, for example, about 0.5 to 1.

The amount of impurity (boron) introduced into the MOSFETQm is shown in Figure 5, that is, the amount of impurity introduced and the leakage current,
It is set based on the relationship diagram between standby current and latch-up voltage. The horizontal axis shows impurities (
This shows the amount of introduced boron. The voltage Vo (gate voltage) applied to the gate electrode 3 of MOSFETQm is O
v, voltage applied to drain region 1 (drain voltage)
VD is 5.0■, voltage applied to substrate 4 (substrate voltage)
Experiments were conducted with VIIB set to -3. The vertical axis indicates the current flowing through the substrate per one memory cell, that is, the leakage current l3B. The vertical axis also shows standby current (current during standby mode of the mask ROM) I8!1 and latch-up voltage.

As shown in FIG. 5, the amount of impurity (boron) introduced is 1.
OX 10 atoms/c! If higher than t,
Standby current Igi increases significantly. This is because the leakage current IBM caused by damage caused by impurity implantation in the memory cell occupies a high (dominant) value in the standby current. Furthermore, if the circuits other than the memory cell array (decoders XDCR and YDCR, sense amplifier SA, etc.) are composed of complementary MO8 circuits (0M08 circuits), the latch-up voltage in the 0M08 section will drop considerably, that is, latch-up will easily occur. . This is because the current flowing through the substrate 4, that is, the leakage current IBM, which is considered as a latch-up trigger current, increases.

Therefore, the amount of impurity (boron) introduced is 1.0XI
Oatoms/crl or less 6 Considering the manufacturing margin, in order not to exceed the above value, the introduced amount should be O,B x 1 o atoms/all or less. That is, by reducing the leakage current per memory cell to 1 nA or less, it is possible to prevent an increase in standby current and a decrease in latch-up voltage.

The voltage applied to the drain region (or source region) of MOSFETQm is determined as shown in FIG.
It is set from a diagram of the relationship between leakage current Ill and time when D is applied. The horizontal axis shows time, which is actually the time equivalent to 10 years in this accelerated life test, and is shown as a value normalized to 1. MOSFETQm
The leakage current IBB is shown in FIG. In order to perform an accelerated test, the gate voltage VG of MO5FETQm is set to 5.5v, which is considerably larger than that during actual operation, which is about 2.5v. In addition, the boron dose is set to 2.3×10"atoms/cr!t, which is larger than the above-mentioned value6. As shown in FIG. To ensure a long service life (actually equivalent to 10 years), the drain voltage VD should be set to 3.
By setting the voltage to 5V or less, crystal defects caused by the introduction of impurities (Poro/), especially crystal defects in the pn junction area between the drain region (and source region) 1 and the semiconductor substrate, can be removed. 7. Since the leakage current InII is reduced, the standby current can be reduced and the ratte-up voltage can be increased.

For the same reason as described above, the bias voltage applied to the common source #JC8K when it is not selected is set to 3.5V or less.

The threshold voltage Vth of the MOSFETQm into which impurities (boron) are introduced is set from FIG. 7, that is, the relationship diagram between the amount of impurity introduced and the threshold voltage.

The horizontal axis indicates the amount of impurity (boron) introduced.

The vertical axis indicates the threshold voltage of MOSFETQm.

As shown in Figure 5 above, the leakage current
When K is set to be less than A, the amount of impurities introduced is approximately 1. OX10
Since it is necessary to keep the voltage below atoms/di, the threshold voltage is set to about 3.0 V or below, as shown in FIG. It is desirable that the threshold voltage of ``''On%lHb%lH information is 2.0v or more. In other words, the threshold voltage of MO3FgTQm into which impurities are not introduced is 0.5~
1. MOSF set at OV, while no impurities are introduced.
The threshold voltage of ETQm is set to 2.0 to 3. Set to Ov. This makes it possible to set a threshold voltage that allows information to be determined and to reduce leakage current 11111.
Deterioration of m can be prevented. Moreover, since leakage current is reduced, standby current can be reduced and latch-up voltage can be increased.

Note that, considering manufacturing margins, the threshold voltage is set to about 2.2 to 2.8 V. Moreover, the data in FIG. 7 is measured with the drain voltage V, ) being 5V.

In this way, in a mask ROM in which the process of writing information by introducing impurities is performed after forming the aluminum wiring of the data line and the common source line C8, the temperature is 900 to 1000°C.
Since crystal defects cannot be recovered by heat treatment at a relatively high temperature, the drain (and source) voltage is set to 3.5V as described above.
or set the threshold voltage to 2.0 to 3.
Ov (dose amount I x 10”atons/cI
It is particularly effective to reduce the leakage current 1 by setting it to a smaller value.

In this embodiment, the following die cells are provided in order to accurately identify the read signal from the storage MOSFET Qm having only the small difference in threshold voltage.

Although not particularly limited, in the dummy cell array D-ARY, for example, two Z-MO3FETs Qd, Qd whose gates are respectively coupled to each word line WO to Wn are connected.
are provided in parallel form.

These MO5FETs Qd, Qd are connected to a pair of dummy common source lines D placed between the dummy data aDD.
They are arranged in parallel with O5. One of the above-mentioned t-MOSFETQd is formed in the same manner as the above-mentioned storage MOSFETQm having a low threshold voltage (in which boron is not introduced). the other da ξ
-MOSFETQd is formed in the same manner as the memory M08FETQm (into which boron is introduced) having a high threshold voltage. The dummy MOSFET Qd', which has this high threshold voltage, compensates for the drop in high level due to leakage current that occurs in the storage MOSFET that should be turned off with respect to the word line selection level (approximately 2V). established for the purpose of

The potential of the die data line DD given by the dummy MOSFETs Qd and Qd' is the same as that of the switch MOSFET.
A sense amplifier SAO, which will be described later, is provided via Q20 to form a reference voltage Vr@f.

Supplied to SAI. The common source line DO3 is connected to the switch MOSFET Q19. The circuit ground potential V via Q21
ts K coupled. Above switch MOSFETQ19
Although not particularly limited, the selection signal YD formed by the Y decoder circuit YDCR is supplied to the gate of ~Q21. In this embodiment, this signal YD is set to a high level when selecting a chip.

MO8PITQ8-Q10 are provided between the dummy data line DD, the dummy common source line DO8, and the power supply voltage Vcc. MOSFETQ8~QIO are MO3FETQI
- Formed under the same conditions as Q7. MO5FETQ8~
QIO is dummy gator line DD and dummy common data @D
It is provided to limit the bias voltage applied to C8 for the reasons mentioned above and to make it equal to the bias voltage of the data line and common source line C8.

Furthermore, to reduce power consumption, MO3FETQ33 and Q
A CMOS inverter consisting of a P-channel MOSFET Q35 and an N-channel MOSFET Q36 corresponding to No. 34 is provided. The output of this CMOS inverter is MO:
Commonly connected to 3FETQ8 to QIO. Signal C8 is supplied to the CMOS inverter via CMOS inverter IVI. As a result, since signal C8 is at high level when selecting a chip, MOSFET Q35
A bias voltage is supplied to MOSFETs Q8 to QIOK. On the other hand, when the chip is not selected, the signal C8 is at a low level, so no bias voltage is supplied.

Therefore, the sense amplifier SAO of this embodiment, which can reduce the standby current, is composed of a preamplifier PAO that performs current/voltage conversion and a differential amplifier circuit AO. Preamplifier PAO is of a current sense type. As a result, the data line potential is set to a small value of 2V, the word line selection level is set to a small value of 2.5V, and the MOSFE
TQm threshold voltage 0.5~1.0V or 2.0~
Under the condition that there is only a small difference of 3.0V, the minute current flowing in the data line can be accurately sensed. Preamplifier PAO is composed of the following circuit elements. The common gate @CDO is a depleted mMO3FE whose gate is coupled to the circuit ground potential vgs.
P-channel MOS in diode form via TQ22
Coupled to the drain of FETQ23. As a result, the MOSFETs Q23 and Q are connected to the selected data line.
A read current is supplied through the switch MOSFET 22, the common data line CDO, and the Y gate. In this case, the above dipledge type MOSFETQ
Depending on the threshold voltage such as I, the selected data line has
A bias voltage corresponding to the threshold voltage is applied. Further, a bias voltage (approximately 2.OV) corresponding to the threshold voltage of the depletion transistor ff1M08FETQ22 is applied to the common data line CD0 (CDI). MOSFETQ33 and Q23 are P-channel boards, so they have no effect. The depletion provided in the data line and common source line of the memory array M-ARY is made common to the data line by forming MOSFETs QI to Q7, etc. and the depletion type MOSFET Q22 constituting the preamplifier PAO under the same manufacturing conditions. Both potentials of the data line CD (input terminal of the sense amplifier) can be set equally. As a result, in the read operation of the storage MOSFETQm, the current flowing through the MO3FETQ23 and Q22 constituting the preamplifier PAO is immediately transferred to the storage MOSFETQm selected according to the selection operation of the word line W and the data line.
As a result, a high-speed read operation can be realized.

That is, the data line has a large number of storage MOSFETQ
By making both of the bias voltages equal, the current detected by the sense amplifier SAO is changed to the current flowing through the memory M03FETQm, even though the parasitic capacitance has a relatively large capacitance due to the coupling of M03FETQm. Therefore, the above parasitic capacitance can be substantially ignored.

In this mask WROM, a relatively low bias voltage of about 2V is applied to the data line for high-speed read operation and the like. In other words, by matching the potential of the data HD to the intermediate potential at which the sensitivity of the sense amplifier is the highest, high-speed operation is attempted.However, the loading means of the data fi!D is Depletion type M receiving ground potential Vss
In the case of a device other than an OSFET, it is extremely difficult to set the bias voltage of the data line to a desired stable potential. When there is a potential difference between the bias voltage of the sense amplifier and the selected data line, there is a charge-up or discharge current that is consumed to equalize the potential difference, and during this time, the read current flowing through the storage element is masked. It will be done.

As a result, the read operation is slowed down by the time spent on charging up or discharging.
In this embodiment, the potential of the data line can be set to a predetermined stable potential.

The MOSFET Q22, which serves as a load means (ratio limiting means) for the common data @CD bias, is composed of a depressive 7f JMOSFET that receives the ground potential at its gate. potential.

Furthermore, MOSFETQ22 and MOSFETQ1-Q7
By forming the data II in the same manufacturing process,
i! The potentials of D and the common data line CD can be made equal. This is effective when using a current sense type sense amplifier (preamplifier).

The MOSFET Q23 is provided with a P-channel MOSFET Q24 in a current mirror configuration. Above M
Although not particularly limited, the drain of OSFETQ24 is an N-channel MOSFETQ in the form of a diode.
25 is provided as a load. Above MOSFETQ25
A power switch MOSFET whose gate receives an internal chip selection signal C8 is connected between the source of the circuit and the ground potential of the circuit.
By providing Q26, current flows through the MOSFETs Q24 and Q25 only when the read operation mode is set. A voltage signal according to the read current is obtained from the drain of the MOS FETQ25, and is supplied to a non-inverting input terminal (+) of a differential amplifier circuit AO consisting of a known 0M08 circuit.

The inverting input terminal of the differential amplifier circuit AO (→ is the MOSFE
The reference signal Vre is obtained from the dummy data line DD via a preamplifier similar to the above consisting of TQ27 to Q31.
f is supplied.

For the same reason as mentioned above, MOSFET Q27 receives the ground potential Vlili at its gate.
The shop is MOSFET. MOSFETQ
27 is also a MOSFET for faster readout.
Q27 and MO3FETs Q8 to QIO are formed in the same manufacturing process.

In addition, in the preamplifier on the reference potential side, MOSFET
The conductance of Q28 is made twice as large as that of MO3FETQ23, or the MOSFET
MOSFETQ29 (Q32) compared to ETQ28
The conductance of MOSFETQ, 1/ of that of 23
Set to 2. As a result, the memory MOS
The above reference voltage Vre is equivalent to 1/2 the conductance of the dummy MO3FETQd with respect to the FETQm.
f is formed.

A sense amplifier SAI consisting of a preamplifier FAI and a differential amplifier circuit Al similar to the above is also provided for the other common data line CDIK. Note that the reference voltage Vref of the sense amplifier SAI is obtained from the MOSFET Q32 which is in a current mirror configuration with the MOSFET Q28.

The output signals of the sense amplifiers SAO and SAI are outputted to an external terminal through an output 7777 circuit DOB (not shown). The output buffer circuit DOB is activated by a timing signal (not shown) generated in a timing generation circuit based on a signal C8.7 As a result of one selection operation of word line W and data 51D,
Two-pit output signals are obtained from one memory array M-ARY.

As mentioned above, when using a depletion blind MOSFET to equalize the operating point of the sense amplifier, in other words, the potential of the common data MCD and the potential of the data line, it is necessary to use a depletion blind MOSFET. Since the process variation in the threshold voltage is as small as about ±0.2V, extremely stable operating conditions can be created.

FIG. 2 shows a schematic block diagram of a mask ROM to which the present invention is applied. In the figure, only the decoder and sense amplifier that constitute the memory array and its selection circuit are shown, and the address buffer, data output circuit, timing generation circuit, and signal lines between these circuit blocks are omitted.

Although not particularly limited, the memory array may be MO or M3.
It consists of four parts like -. Memory array MO or M3
correspond to the memory array M-ARY shown in FIG. 1 above, respectively. Each memory array MO to M3 also includes, for example, eight memory blocks BO to B7, as shown by dotted lines. The above memory array M
X decoders XDCRO and XDCRI are arranged between O and Ml and between M2 and M3, respectively. These X decoder circuits XDCRO and XDCRI correspond to the X decoder circuit XDCR shown in FIG. 1 above.

In the figure, memory arrays MO to M3 each include the aforementioned Y gate circuit (column selection circuit). In the memory arrays MO to M3, read signals from the data lines respectively selected by the Y gate circuits are transmitted to the pair of common data lines CD as described above.
O, the pair of sense amplifiers S described above via CDI
AO, SA1 to SA6. It is supplied to SA7. Note that the sense amplifier SA3. SA4 and SA7 correspond to SAO, and sense amplifiers SA2. SA5 and SA6 correspond to SAI.

The Y gate circuits of each mesori array MO to M3 have Y decoder circuits YDCRO to YDCR3, respectively.
A selection signal formed by These Y decoder circuits YDCRO to YDCR3 correspond to the Y decoder circuit YDCH shown in FIG. 1 above.

Although not particularly limited, the X decoder circuits XDCRO and XDCRI select one word line each of the memory arrays MO and M1 and M2 and M3.

In addition, the above Y decoder circuits YDCRO to YDCR3
As a result, selection signals for a pair of data lines corresponding to sense amplifiers SAO, SAI to SA6, and SAT are formed for memory arrays MO to M3, respectively. As a result, from each of the above-mentioned memory arrays MO to M3.

Since read signals of 2 bits each are obtained, the read operation is performed in units of 8 bits in total.

In this embodiment, in order to reduce power consumption in the non-selected state and the read state, the memory arrays MO to M3 are
As shown by dotted lines in the figure, memory blocks BO to B
7, load circuits LO to L7 are provided.

As shown in FIG. 1, each load circuit LO to L7 has a plurality of depression deafness M08F corresponding to each data aD.
C consisting of ET and one MO3FET Q33 and Q34
It consists of a MOS inverter and one NAND gate circuit G1. Selection signals (predecode signals) SBO to SB7 formed by the predecode circuit PD are input to one input terminal of the gate circuit Gl of the load circuits LO to L7. In this example, each memory array M-AR
In order to divide Y into eight blocks, a complementary address signal based on the upper three bits of Y address signal AY is supplied to predecode circuit PD. Therefore, the data lines corresponding to the five Y address signals whose upper three bits are the same are treated as one block.

The predecoder circuit PD has the same configuration as a known decoder circuit consisting of a 0M08 circuit such as the X decoder selectively set to a high level. As a result, the power supply voltage is selectively supplied by the load ports MLO to L7. That is, among the eight memory blocks BO to B7, which are divided into eight blocks in each memory array MO to M3,
A high level voltage such as the power supply voltage Vcc is supplied to the drains of the depressed MO5FETs constituting the load circuits corresponding to one memory block to which each selected data line belongs.

In a read operation of storage MOSFET Qm, for example, when reading a pair of data lines provided in memory block BO, other memory blocks B1 to B
7, the bias voltage is not supplied from the corresponding load MOSFET, and the above bias voltage is not supplied from any of the load MOSFETs in the non-selected state, so the increase in power consumption due to leakage current is avoided. It can be prevented.

Furthermore, as described above, each of the memory arrays MO to M3 is divided into memory blocks BO to B7, and reading from one memory block is performed from each of the memory arrays MO to M3. Therefore, the number of sense amplifiers can be reduced. That is, in order to obtain a total of 8 bits of read signals for each memory array MO to M3, it becomes necessary to provide eight sense amplifiers for each memory array.

A dummy cell block consisting of a plurality of dummy cells, a dummy data line DD, and two dummy common source lines DSC is provided corresponding to each memory array MO-M3. Therefore, the load circuit of the dummy block, as shown in FIG.
, Q35, and an inverter consisting of Q36,
is also provided corresponding to each memory array. In a read operation, 2-bit memory cells are always selected from each memory array, so a bias voltage is always supplied to each dummy cell block during chip selection.

Note that in a read operation, when a memory cell is selected from only one memory array, the predecode circuit may supply a bias voltage only to the dummy cell block of the selected memory cell.

Note that in FIG. 2, the memory array, the good.

As explained above, according to the new technology disclosed in this application, the following effects can be obtained: (1) The drain and/or source region (data line and/or common By applying (biasing) a voltage lower than the power supply voltage to the source line (source line), leakage current can be reduced and the deterioration time of the MOSFET can be lengthened.

(2) The dose of impurities is 1x1o atom attack/d
or the threshold voltage of the MOSFET is 2.
0-3. By setting it to Ov, leakage current can be reduced and the deterioration time of the MOSFET can be lengthened.

(3) By (1) or (2) above, the standby voltage can be reduced, so power consumption can be reduced, and the latch-up voltage can be increased, so the occurrence of latch-up can be prevented. can do.

(4) The effects of (1) to (3) above can be similarly obtained for dummy cells.

(5) A depression v whose gate is given the ground potential of the circuit between the data line of the memory array and the power supply voltage.
Provide a7fli load MOSFET. Depression above! Since the threshold voltage of the MOSFET can be controlled with high precision and its process variation is small, the bias voltage of the data line can be stably set to a predetermined value. Common source 411. Similar effects can be obtained for the dummy data line and the dummy common source line.

(6) Between the data line of the memory array and the power supply voltage, a depletion transistor load MO5FET whose gate is supplied with the circuit ground potential is provided, and a depletion transistor load MO5FET whose gate is supplied with the circuit ground potential is provided. Type M08F
The readout is performed by an amplifying MOSFET that supplies current to the selected data line via the ET. The threshold voltage of the above depletion type MOSFET is
Since it can be controlled with high precision and its process variations are small, the bias voltages of the data line and the sense amplifier receiving the read signal can be made equal.

As a result, a true read current can be obtained together with the selection operation of the storage MOSFET, so that the read operation can be performed at high speed with a simple configuration.

(7) Memory MO configured to run parallel to the data line
By selectively grounding the common source line of SFETs using the Y (column) selection signal, unselected storage MOS
Since no current flows through the FET, it is possible to reduce power consumption during read operation.

(8) Since the common source line can be provided with a selection function by the power mentioned above, storage MOSFETs to which different Y addresses are assigned to the data lines can be connected in common. Since the number can be reduced, the effect that memory M08FETs can be formed in high density can be obtained.

(9) In the read operation, the operating voltage is supplied only to the depletion type load MOSFET provided in the memory block to which the selected data line belongs. As a result, bias voltage is not supplied from the corresponding load MOSFET to other memory blocks during read operation and to all memory blocks in the non-selected state, so power consumption due to drain leakage current of the storage MOSFET is not provided. can prevent an increase in

α [Bias voltage of data line and common source line
- By limiting the potential to a voltage lower than the power supply voltage, it is possible to apply a bias voltage of opposite polarity to the bias voltage to the substrate.

Although the present invention has been specifically described above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the spirit thereof.

For example, when reading in units of 1 bit, the sense amplifier SAO or SAI may be selectively operated according to the Y address signal and outputted from a common data output buffer. Furthermore, reading may be performed in units of 2 bits, such as 2 bits or 4 bits. The bias voltage may be supplied only to die cells corresponding to the memory array containing the selected memory cell.

The configuration of the memory array (memory block) is the storage MO
The SFET may have its source directly connected to the ground potential of the circuit. In this case, the memory MOS
The drains of the FETs are each coupled to one independent data line.

The conductivity type of each semiconductor region may be reversed. The impurity implanted into the substrate through the gate electrode is NW such as phosphorus or arsenic.
This may lower the threshold voltage. Memory cells and/or peripheral circuit elements are MIS (metal insulator SEM)
MISFET of the same conductivity type as the memory cell and/or the memory cell constituting the peripheral circuit is a well region formed in the substrate of the same or opposite conductivity type as the substrate. It may be formed inside.

The present invention can also be applied to a vertical mask ROM in which a plurality of MOSFETs serving as memory cells are connected in series between a power supply potential and a reference potential.

Any method may be used to write to the storage MOSFET. For example, as a memory MOSFET, FAMO5
(70-Tingate Appalanche Injection 1
The writing may be performed electrically using a MOSFET or the like.

The present invention relates to a semiconductor memory device, such as a ROM such as a mask-type ROM or an EFROM (erasable programmable read-only memory), which includes a memory element having two different threshold voltages according to stored information. It can be widely used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, between the data line of the memory array and the power supply voltage, a depletion type load MO3FET whose gate is given the circuit ground potential is provided, and a depletion type load MO3FET whose gate is given the circuit ground potential is provided. M
1 on the selected data line via OSFET! By performing the readout using an amplification MOSFET that supplies a current, the bias voltages of the data line and the sense amplifier receiving the readout signal can be made equal, thereby increasing the speed of the readout operation.

[Brief explanation of the drawing]

1 is a block diagram of a mask type ROM to which the present invention is applied, FIG. 3 is a plan view of a memory cell of the mask type ROM of FIG. 1, and FIG. 4 is a memory cell of the mask type ROM of FIG. 1. A cross-sectional view of the cell. Figure 5 shows the relationship between the amount of impurity introduced and leakage current, standby current, and latch-up voltage. Figure 6 shows the relationship between leakage current and time when a predetermined drain voltage is applied. , FIG. 7 is a diagram showing the relationship between the amount of impurity introduced and the threshold voltage. M-ARY, MO~M3...Memory array, XAD
B-DCR...X address buffer decoder, YA
DB-DCR...X address buffer decoder, S
AO~SA7...Sense amplifier, PAO, PAl...
・Preamplifier, AO, A1...Differential amplifier circuit, BO~
B7...Memory block, XDCRO~XDCR1・
・・Xf co-7 circuit, YDCRO~YDCR3...Y
Decoder circuit, LO-L7...load circuit, PD...
predecoder. Agent Patent Attorney Katsutoshi Ogawa Figure 1 Figure 3 Figure 5 Figure 60 AME M7 Figure QJ 1.0

Claims (1)

[Claims] 1. A memory array including a plurality of word lines, a plurality of data lines intersecting with these, and a plurality of memory cells provided corresponding to the intersections of the word lines and the data lines; a depletion type MOS connected between the data line and a power supply potential and having a ground potential applied to its gate electrode;
FET, and the plurality of depression type MOSs, each of which is a predetermined one.
a first switch means provided corresponding to the FET and connected between the power supply potential and the plurality of predetermined depletion MOSFETs; and a first switch means provided corresponding to each of the first switch means, the Ground potential and the depletion type MOSFET
A read-only memory comprising second switch means connected between said first switch means and operating complementary to said first switch means. 2. A memory cell consisting of a plurality of word lines, a plurality of data lines intersecting with these, and a plurality of N-channel MOSFETs provided corresponding to the intersections of the word lines and the data lines, and at least the same data said M connected to the line
a memory array including a common source line connecting the sources of the OSFETs; and a first depletion MO connected between the data line and a power supply potential and having a ground potential applied to its gate electrode.
A read-only memory comprising: an SFET; and a second depletion type MOSFET connected between the common source line and a power supply potential and having a ground potential applied to its gate electrode. 3. A memory array including a plurality of word lines, a plurality of data lines intersecting the word lines, and a plurality of memory cells provided corresponding to the intersections of the word lines and the data lines; a dummy cell array including a plurality of dummy data lines intersecting with the word line and a plurality of dummy cells provided corresponding to the intersections of the word line and the dummy data line; First depression type M in which ground potential is applied to the gate electrode
A read-only memory comprising: an OSFET; and a third depletion type MOSFET connected between the dummy data line and a power supply potential and having a ground potential applied to its gate electrode.