JPH02285595A - Non-volatile semiconductor storage - Google Patents

Abstract

PURPOSE:To improve the reliability of a cell and to sense data at high speed by directly inputting the data of a selected cell through a column selecting transistor to the input end of a sense amplifier and setting the threshold value voltage of this input end to a low value so as to detect the potential of a column line. CONSTITUTION:Since the column line is clamped lower than the power supply potential for reading by a transistor for column line potential clamp when the data are read, the reliability of the cell can be improved. The data of the selected cell are directly inputted through column selecting transistors CSa and CSb to the input end of the sense amplifier and the threshold value voltage for the input end of this sense amplifier is set the low value so as to detect the potential of the column line. Accordingly, data sense operation can be execut ed without using a double step sense system. Thus, when the data sense opera tion is executed, a transfer gate is not included in a route to discharge the charges of column lines BLa, BLb, BL''a and BL''b in a low level side and internal delay from the column lines BLa, BLb, BL''a and BL''b to the sense amplifier is reduced. Then, an access time is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor nonvolatile memory device, and particularly to a data sense circuit.

(Prior Art) FIG. 5 shows a conventional ultraviolet erasable and rewritable read-only memory (EPROM), which uses two cell transistors per memory cell.
A part of a transistor/1 cell type EPROM is shown. In this EPROM, MCa and MCb are a pair of cell transistors, one cell is set to a written state and the other cell is set to a non-written state. WL is a row line connected to each gate of cell transistors MCa and MCb, BLa and BLb are a pair of complementary column lines connected to each drain of cell transistors MCa and MCb, and C8a and C8b are a pair of column lines connected to each gate of cell transistors MCa and MCb. A pair of column selection transistors are inserted and connected in series to the column lines BLa and BLb, SLa and SLb are a pair of sense lines, and SA is a pair of sense lines S.
CM with a pair of input terminals connected to La and SLb
A sense amplifier consisting of an OS current mirror type differential amplifier, LDa and LDb are sense line load circuits connected between a pair of sense lines SLa and SLb and a read power supply vcc, and TP is a sense line load circuit connected between a pair of sense lines SLa and SLb and a read power supply vcc. This is a P-channel MOS transistor for column line equalization connected between input terminals (between a pair of sense lines), and sense line precharge No. 13 φp is applied to its gate.

In addition, in EPROM, even in the read state, there is a risk that the contents of the cell may be destroyed (erroneous writing) due to voltage stress during long-term continuous use.As a countermeasure, the drain voltage (column line potential) of the cell is set to the read power supply potential. (Vcc potential,
Clamp lower than (usually 5V) (e.g. 1.5V)
The reliability of the cell is improved by increasing the reliability of the cell.

That is, the column lines BLa" and BLb" on the sense amplifier side of column selection transistors C8a and C8b and the read power supply V
cc, N-channel MOS transistors Tea and TCb for column line potential clamping are inserted, respectively, and N-channel MOS transistors Tea and TCb for transfer gates are inserted between column selection transistors C5a and C8b and a pair of sense lines SLa and SLb, respectively. Channel MOS1 - transistor TG
a and TGb are inserted, and each of these transistors T
A bias potential generation circuit RAS is provided for applying a bias potential of, for example, about 1.5 .ANG. to the gates of Ca, TCb, TGa, TGb.

Note that N-channel MOS transistors Tea and TCb for column line potential clamping and N-channel MOS transistor Tea for transfer gate.

For TGb, a 0V threshold transistor having a threshold voltage of 0 is used.

Since the normal read operation of the EFROM is well known, it will be briefly explained below. FIG. 6 shows the read operation of the sense amplifier SA when the column line precharge signal φp is activated for a short time in synchronization with, for example, the transition of the address input or the input of the memory chip selection signal.

That is, when the sense line precharge signal φp becomes active (here, the inverted signal φp is 5V), the P-channel MO8 transistor TP for sense line equalization is turned on, and the pair of sense lines SLa.

The potential of SLb becomes the same potential (4, 0V). Further, the potentials of the pair of column lines BLa and BLb are the same potential (1.5 V). After this, when the sense line precharge signal φp becomes inactive (here, the inverted signal φp is 0V),
A pair of column lines BLa are connected by successive potentials from a pair of selected cells.
, BLb (for example, 0.IV) occurs (the potential on the high level side/low level side is 1.4V/1.3V, for example).
) is designed to be. In addition, this potential difference is amplified by a pair of transfer gate N-channel MOS transistors TGa and TGb, and a pair of sense lines S
The potential difference between La and SLb is, for example, 0.5V (for example, the potential on the high level side/low level side is 4.0V/
3.5V). In this case, the sense amplifier SA has a potential difference of, for example, 0. It is designed to allow sense amplification at the time when IV occurs.

However, the above-mentioned EPROM uses a pair of column lines BLa separated by a pair of transfer gates TGa and TGb during its data sensing operation.

A two-stage sensing method is used in which sense is amplified in two stages using BLb and a pair of sense lines SLa and SLb, and since a transfer gate is included in the path that discharges the charge of the column line on the low level side, its resistance Minutes slow down the discharge and slow down the access time.

Electrically erasable/rewritable read-only memory (EEP)
The same thing can be said about ROM) when using the two-stage sensing method as described in 1.

(Problems to be Solved by the Invention) As described above, in conventional semiconductor nonvolatile memory devices, in order to improve cell reliability, a column line potential clamp is installed between the column selection transistor and the read power supply. In addition to inserting a transistor, a two-stage sensing method is used by inserting an l transfer gate transistor between the column selection transistor and the sense line. The transfer gate is included in the path for discharging the charge, which increases the internal delay from the column line to the sense amplifier and slows down the access time.

The present invention has been made to solve the problems mentioned above, and its purpose is to provide a semiconductor nonvolatile memory device that can improve cell reliability and sense data at high speed. be.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a memory cell array in which nonvolatile memory cells are arranged in rows and columns, a row decoder for selecting a row line of the memory cell array, and a row decoder for selecting a row line of the memory cell array. A plurality of column selection transistors that select column lines, a column decoder that selects and controls the plurality of column selection transistors as a pair, and a connection between one end of each of the plurality of column selection transistors and a read power supply potential. It consists of a column line potential clamping transistor whose gate is given a potential lower than the readout power supply potential, and a current mirror type differential amplifier for detecting and amplifying the data of the selected cell that has passed through the column selection transistor. In a semiconductor non-volatile memory device equipped with a sense amplifier, the data of the selected cell via the column selection transistor 1 is directly input to the input terminal of the sense amplifier 1, and the threshold voltage at the input terminal of the sense amplifier is It is characterized in that the potential of the column line is set to a detectable low value.

(Function) Since the column line is clamped to a lower level than the read power supply potential by the column line potential clamping transistor at the time of continuous output, the reliability of the cell can be improved.

Then, the data of the selected cell via the column selection transistor is directly input to the input terminal of the sense amplifier, and the threshold voltage at the input terminal of this sense amplifier is set to a low value that can detect the potential of the column line. , data sensing operation is possible without using a two-stage sensing method. Therefore,
During a data sensing operation, a transfer gate is not included in the path for discharging charges in a column line on the low level side, and the internal delay from the column line to the sense amplifier is reduced, resulting in faster access time.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of an EPROM, for example, and compared to the conventional EFROM described above with reference to FIG.
a) MOS for transfer connected between column lines BLa, BLb and sense lines SLa, SLb) transistors TGa, TGb are omitted, sense line load circuits LDa, LDb are omitted, column selection One end side of transistors C8a and C8b (column line BLaBLb") is directly connected to the input end of sense amplifier SA, and (b
) The threshold voltage at the input end of this sense amplifier SA is set to a low value that can detect the potential of the column lines BLa BLb'', and (C) the P-channel MO for column line equalization.
5) The difference is that an N-channel MOS transistor TE2 for column line equalization is used in place of the transistor TP, and the same parts as in FIG. 5 are given the same reference numerals.

That is, in FIG. 1, MA is an EPROM cell M Ca consisting of a floating gate transistor.

MCb: memory cell array arranged in a matrix;
WL is a row line of memory cell array MA, RD is this row line W
A row decoder, BLa, that selects L.

BLb is a column line of memory cell array MA, CS a sC
8b is a column selection transistor inserted and connected in series to each column line BLa, BLb, and CD is a column selection transistor connected to this column line BLa, BLb in series.
・11 to select transistors C3a and C3b in pairs! I control the column decoder, BLa BLb'' and the sense amplifier S A (a pair of column lines of 1111, SA selects the selected pair of columns) and transistors C3a and C8b than a pair of column selection transistors C3a and C8b.
(a pair of column lines BL
a BLb" potential) is input to the pair of input terminals.
This is a sense amplifier consisting of a MOS current mirror type differential amplifier. This sense amplifier SA consists of a pair of N-channel MOS transistors N1 and N2 for input, and a pair of P-channel MOSFETs connected in a current mirror for load.
Consists of I-transistors P1 and P2.

TCla and TC], b is a pair of first column line potential clamp N-channel MOS transistors connected between the VCC potential and the pair of column lines BLa and BLb;
C2a and TC2b are connected to the VCC potential and a pair of column lines BL.
a pair of second column line potential clamp N-channel MOS) transistors connected between
I is a first equalizing N-channel MOS transistor connected between a pair of column lines BLa and BLb, and TE2 is a second equalizing N-channel MOS transistor connected between a pair of column lines BLa and BLb. Ranjistor, TE3
is the third terminal connected between the pair of output terminals of the sense amplifier SA.
N-channel MOS transistor for equalization, PR
la and PRlb are connected to the Vcc potential and a pair of column lines BLa,
A pair of first column line precharge circuits connected between BLb and PR2a and PR2b are a pair of second column line precharge circuits connected between Vee potential and a pair of column lines BLaBLb''. be.

Column line precharge circuits PR1a, PRI b and PR
In each of PR2a and PR2b, a P-channel MOS transistor P3 and an N-channel MO5I-transistor N3 are connected in series between the VCC potential and the corresponding column line.

A transistor TC1a for column line potential clamping,
TC1b, TC2a, TC2b and column line precharge circuits PR1a, PRI b, PR2a, PR2b (N channel MOS) transistor N3 has a voltage of V at each gate.
A predetermined bias potential lower than the CC potential (for example, 1.5 V, which corresponds to the maximum value within a range in which erroneous writing to the cell does not occur due to voltage stress during long-term continuous operation) is applied from the bias potential generation circuit BAS. Further, a precharge signal φp is supplied to each gate of the equalizing N-channel MOS transistors TE3 to TE3, and the column line precharge circuits P R1a %PR1b and PR2aX
An inverted signal φp of the precharge signal φp is supplied to each gate of the P-channel MOS transistor P3 of PR2b.

In the figure, each of the P-channel transistors P1 to P3 is an enhancement type transistor. In addition, each N-channel transistor N1. −
N3, TCla, TClb.

For TC2aSTC2b and TE1 to TE3, so-called ■-type 0■ threshold transistors (or depletion type transistors having negative threshold voltages) having a threshold voltage of approximately 0V are used. This 0V threshold transistor is one in which impurity ions are not implanted into the substrate (the substrate concentration remains unchanged).

Next, the second section regarding the data sensing operation of the EPROM will be explained.
This will be explained with reference to the figures. For example, a precharge signal φp and its inverted signal φp are generated for a short time in synchronization with a transition of an address input or an input of a memory chip selection signal. During this generation period, column line precharge circuits PR1a and PR
1b, PR2a, and PR2b are turned on, and the column line precharge circuit PR
]a, PR1b and PR2a, PR2b to column line B
LaSBLb, BLa BLb" are precharged. In this case, column line precharge circuits PR1a, PR
], b and P R2a −.

Since 1.5V is applied to each gate of the N-channel MO3 transistor N3 of PR2b from the bias potential generation circuit BAS, the column line potential is at its highest potential (approximately 1.5V).
5V).

Also, at this time, the N-channel MO3) transistors TEI to TE3 for equalization are turned on, and the column lines BLa and BL
b, BLa BLb" have the same potential, and the pair of output terminals of the sense amplifier SA also have the same potential. After this, the precharge signal φp and its inverted signal φp are no longer generated (if φp is Ov, φp or 5V) ), and column line precharge circuits PR1a, PRIb and PR2a.

P-channel MO3 transistor P3 and equalizing transistors TEI-TE3 of PR2b are all turned off, and the contents of the selected cell are read.

In this case, the column line potential clamping transistor TC1a
, TC1b, TC2a, and TC2b maintain the low-level side potential of the column line so that it does not drop too much.

In addition, the potential difference between the pair of column lines BLa and BLb is caused by the successive potentials from the pair of selected cells, and the potential difference between the pair of column lines BLa and BLb is increased.
The potential difference between "BLb" and "BLb" should be set, for example, 0.
It is designed to be approximately 5.5V (that is, the high level side/low level side of the column line potential is approximately 1.5V/1.0V).

In this way, even if the column line potential is low, an O2 threshold transistor with a threshold voltage of 0V (or a depletion type transistor with a negative threshold voltage) is used as the human transistor of the sense amplifier SA. , the potential of the column line can be detected. In this case, sense amplifier S
A is designed so that sense amplification can be performed when a potential difference of, for example, 0.1 mm occurs between a pair of input terminals,
Read data from the selected cell is sense-amplified at high speed.

Note that this is a case where the selection speed of memory cells by row line driving is slow, and as described above, by supplying the precharge signal φp, column lines BLa, BLb and BLa BLb"
If there is enough time for an equalization operation in which (a pair of input terminals of the sense amplifier SA) are set at the same potential and a pair of output terminals of the sense amplifier SA are set at the same potential, the above-mentioned equalization operation is performed. Since it becomes possible to reset the potential at the pair of input terminals and the potential at the output terminal of sense amplifier SA, it becomes possible to speed up the data read operation.

Further, as the bias circuit BAS, it is desirable to use a circuit that is not affected by fluctuations in the read power supply potential caused by peak currents associated with charging and discharging of the internal circuit of the EPROM and the data output buffer circuit, for example, as shown in FIG. 3(a) or (b). Alternatively, by configuring as shown in (C), a constant bias potential can be obtained without being influenced by the power supply voltage.

That is, the bias circuit shown in FIG. 3(a) consists of two depletion type N-channel transistors NDI and ND2 whose respective gates are connected to the ground potential VSS.
It is connected in series between the ce potential and the ground potential VSS, and the bias potential is taken out from the series connection point.

In the bias circuit shown in FIG. 3(b), a depletion type N-channel transistor ND whose gate and source are connected to each other and an enhancement type N-channel transistor NE whose drain and gate are connected to each other have a Vc
It is connected in series between the c potential and the ground potential VSS, and the bias potential is taken out from the series connection point.

The bias circuit shown in FIG. 3(C) includes a depletion type N-channel transistor ND whose gate is connected to the ground potential Vss, and an enhancement type N-channel transistor NE whose drain and gate are connected to each other.
It is connected in series between the VCC potential and the ground potential Vss, and the bias potential is taken out from the series connection point.

FIG. 4 shows a part of an EFROM according to another embodiment of the present invention, and the EPR shown in FIG.
Compared to OM, N-channel MOS with column line voltage clamping
Transistors TC1a and TClb.

TC2a, TC2b and column line precharge circuit PRI
The difference is that a depletion type N-channel transistor ND is used in place of the N-channel MO8I-transistor N3 of a, PRI b, PR2a, and PR2b, and the ground potential Vss is applied to each gate i. Since the other parts are the same, the same symbols as in FIG. 1 are used.

This EPROM provides substantially the same effects as the EFROM shown in FIG. 1, and also eliminates the need for the bias potential generation circuit BAS as described above.

It should be noted that the present invention can also be implemented in EEPROMs in the same manner as in the embodiments described in -.

[Effects of the Invention] As described above, according to the present invention, it is possible to improve the reliability of the cell, and moreover, during data sensing operation, the internal delay from the column line to the sense amplifier is reduced, resulting in faster access time. It is possible to realize a semiconductor nonvolatile memory device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of an EPROM according to an embodiment of the present invention, FIG. 2 is a voltage waveform diagram showing a data sense operation of the EPROM of FIG. 1, and FIGS. 3(a) to (C) are circuit diagrams showing different specific examples of the bias circuit in FIG. 1, FIG. 4 is a circuit diagram showing a part of an EPROM according to another embodiment of the present invention, and FIG. 5 is a circuit diagram showing a part of a conventional EPROM. FIG. 6 is a voltage waveform diagram showing the data sensing operation of the EPROM of FIG. MA...Memory cell array, MCa. MCb...EPROM cell, WL...row line, RD.
...Row decoder, BLa, BLb, BLa BLb''...Column line, C8a, C3b...Column selection transistor, CD...Column decoder, SA...Sense amplifier, N1-N3...N channel MO8 transistor, P1-P3...P channel MO5) transistor, T
C1a, T C1,b, T C2a, T
C2b--N-channel MO8 for column line potential clamp
) Transistors, TE1 to TE3... N-channel MO for equalization 8) Transistors, PRI a, PRI b. PR2a, PR2b...Column line precharge circuit, φp
. . . Precharge signal, BAS . . . Bias potential generation circuit, NDI, ND2, ND . Applicant's representative Patent attorney Takehiko Suzue

Claims (4)

[Claims] (1) A memory cell array in which nonvolatile memory cells are arranged in rows and columns; a row decoder that selects a row line of the memory cell array; a plurality of column selection transistors that select a column line of the memory cell array; a column decoder that selects and controls column selection transistors in pairs; and a column decoder connected between one end of each of the plurality of column selection transistors and a read power supply potential, and whose gate is given a potential lower than the read power supply potential. A semiconductor non-volatile memory device comprising a column line potential clamping transistor and a sense amplifier comprising a current mirror type differential amplifier for detecting and amplifying data of a selected cell that has passed through the column selection transistor. The data of the selected cell passing through the selection transistor is directly input to the input terminal of the sense amplifier, and the threshold voltage of the input terminal of the sense amplifier is set to a low value capable of detecting the potential of the column line. A semiconductor non-volatile memory device. (2) connected between a pair of input terminals of the sense amplifier,
A claim characterized by comprising equalizing means that is controlled to be turned on by a control signal that is temporarily generated in synchronization with a transition of an address input or an input of a storage device selection signal to set the pair of input terminals to the same potential. Item 1. The semiconductor nonvolatile memory device according to item 1. (3) The sense amplifier consists of a pair of N-channel MOS transistors for input and a pair of P-channel MOS transistors connected in a current mirror for load,
3. The nonvolatile semiconductor device according to claim 1, wherein the N-channel MOS transistor is a 0V threshold transistor having a threshold voltage of approximately 0V, or a depletion type transistor having a negative threshold voltage. Storage device. (4) The semiconductor nonvolatile memory device according to claim 1, wherein the column line potential clamping transistor is a bias depletion type N-channel transistor, and a ground potential is applied to the gate thereof. .