JPS63239689A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, particularly MOS ROMs of the electrically programmable type.

Electrically programmable F[1-Tingage-1] type ROM and EPROM devices are commonly used in Det. Sus Instruments Inc.'s 111 and Hc [Lroy U.S. Pat.
．． 112.509 and 4.112.544 and U.S. Pat. No. 3.984.822.

There are several manufacturers producing EPROM devices with 8, 16, 32, and recently 6/IK bit layouts. However, with the continuing desire for high speed and low cost, there is a need to reduce cell rise or increase bit density while maintaining process compatibility with existing dual-level polysilicon N-channel fabrication methods. It has arisen. One classic technique to increase the 7-ray density of the OM is to use a virtual ground configuration instead of providing a ground wire for the output line from each column.

Virtual ground memory is Tekinus Instrument's r
isher J3 and nogers US Pat. No. 3,9
No. 34.233j3 and U.S. Pat. No. 4,021,781 to E. R. Caudel. Temporary 1tt
A grounded EPROM layout is disclosed in Texas Instruments, Inc. (7) DaVid J, HC[1rOV, US Pat. No. 4.151.021. The high transient voltages and currents required to program floating gate EPROMs place more stringent requirements on the decode circuitry than circuits conventionally employed in virtual ground devices. Conventional EPROMs therefore used separate contacts and lines for each cell, thus requiring additional space on the chip. However, with the separate ground selection and column selection functions required for virtual ground memory operation, the column decoding employed has different complexities than dedicated ground memory devices.

This column and ground selection addressing of large high speed devices, along with row addressing, introduces new requirements into the decoding circuitry.
f J-Sl. Low power V of EPROM neck
The customer's request for 100% performance created the need to provide a power-down mode that is different from the normal standby mode of operation. While in power-down mode a3 does not respond to addresses, there should not be an excessively long period before a normal access is granted when power-down mode is exited.

Within these constraints and conflicting conditions, improved EPROM
5 is designed.

It is a principal object of the present invention to provide an improved electrically programmable ROM device with particularly low noise and high bit density. It is also an object of the present invention to provide an arrangement for accessing a memory array for reading and/or programming in an improved manner.

DESCRIPTION OF MEANS AND EMBODIMENTS FOR SOLVING PROBLEMS] In one embodiment of the present invention, an electrically programmable memory array having rows and columns of floating gate memories has alternate output lines and ground lines between columns of cells. The line is right and provides a virtual ground configuration. The row t is selected by one part of the address input, and the column by the other part. The output wire on one side of the selected column is energized and the ground wire on the other side is energized. A differential sense amplifier is responsive to the voltage on the selected output line and the reference voltage. The number of transistors required for the row selection function of the decoder is determined by adopting a predecoder that selects 1 to 4 for each address bit pair, and then using one of these selection outputs to activate the N multiplexer. , all others as decoder power and the N outputs as multiplexer inputs.

The predecoder is an AND10R circuit that receives two pairs of true and complementary address voltages for each address bit, eight pairs containing address voltages that are logically the same but separated by a low threshold Ill- transistor. I'm here.

The pre-decode circuit uses the higher of the 8 pairs and performs AND10
Speed-up is achieved by driving the input transistors of the R circuit between the output node and the output node, and using the lower of 8 to C to drive the input transistor of the AND10RIilD path between the output node and ground. The former input transistor has a lower capacitive loading than the latter.

FIG. 1 shows a block diagram of a memory system employing features of the present invention. Although the present invention can be used with various types and sizes of memory devices, the embodiment shown here is an 8X
It is an N-channel floating gate electrically programmable ROM, or EPROM, with 32 or 32.768 bits partitioned into 16x256 blocks. Commercial implementations further include column decoding to
Defining a 16 bit device partitioned 8X32X64 in 6 bits, 32 bits partitioned 8X32X128 and 64 bit devices partitioned 8X32 has been selected for. In FIG. 1, the cell array 10 has 25
It includes 32,768 floating gate cells arranged in 6 rows and 128 columns, with the columns divided into eight separate cell groups numbered 10-1 to 10-8.

Each group has a separate power/output terminal 11.

The 8-bit row address applied to the eight address input terminals 12 is decoded to activate only one of the 256 tree rows [ti13]. The cell array is of the virtual ground type, with only one ground line connected to the ground of each group 10-1 through 10-8, with adjacent column lines used as the outputs of selected cells in each city. The 4-bit column address applied to the integrated circuit device by the 4-terminal 14 is decoded by eight separate selected n-paths 15 to one of the nine ground wires in each group from 10-1 to 10-8. A book is selected, and one tree among the eight output column lines is selected by 8@ separate selection circuits 16. The differential sense amplifiers 17 in each group from 10-1 to 10-8 sense the data pin I for the selected cell and apply an output to one of the terminals 11 for a read operation. The data pin 1- on the terminal 11 is added to the selected bit in each group by the input buffer and selection circuit 16 of the integrated circuit device. It has a terminal. terminal 1
One +5v supply voltage vcc is applied by 8 and ground or vss is applied to terminal 19. A programming voltage vrJr, of approximately +25v is applied to terminal 20. A chip selection command C8 is applied to terminal 21 and a power down/program command PD/PGM is applied to terminal 22.

The latter three, C8, and PD/PGM are connected to a control circuit 23, which generates a control voltage to determine the mode of operation of the system.

In read mode vpE and PD/PGM are logic O
and C8 is active low, logic O.

These conditions are shown on the left side of FIGS. 2a-2e.

As shown in Figure 2a, C8 is low, and Figure 2d and
As shown in Figure C, if D and PD/PGM are low, address bit AO of 12i&l on terminal 12.14
-When Δ11 becomes valid at time 24 in FIG. 2, eight bits in array 10 are selected (10-1 to 10-
(one bit in each group of 8), these 8 bits occur on terminal 11 as shown in FIG. 2e.

The other state is standby mode, where all inputs are the same as in the read seventh mode except that C8 is high at logic one. Here, the depth is in a read state, but as shown in the center of FIG. 2, even if an address occurs, it is not selected as such, and the data out shown in FIG. 2e does not occur.

As shown on the right side of Figure 2C, the PD/PGM input is connected to logic I3.
! When 1, a power down mode of operation occurs. As shown in FIG. 2d, vpp is low and C8 can be either low or high, ie, a state that does not require attention. If the address occurs, no output occurs.

As shown in Figure 2'd (left side), the vpp input is +25.
v, and the second 'ff! ! +) D as shown in Ie
The programming mode of operation occurs when /PGM is active low and C8 is active low as shown in Figure 2'a. In this state, the row address applied to terminal 12 is high Tt on one 1j1113.
Pressure (V,, -Vl) @ Raw Sil (all others are low). 2nd'
The column address generated on terminal 14 as shown in FIG. 1 selects one of the eight columns for each city. Depending on the presence of a 0 or a 1 at each of the terminals 11 during the time shown in FIG. ) p-vt or low voltage is applied. This condition causes the eight selected pins I to be charged or uncharged depending on the data input on terminal 11.

When ① is high, the program mode occurs only when v and p of PD/PGM are both low. All other conditions generate a program inhibit mode as shown on the right side of FIG. 2'. Figure 2'a or 2nd
'As shown in Figure C, the inhibition mode exists when one or both of PD/PGM is high, as is the case with input C8.

Regardless of the address present on terminals 12 and 14 or the data present on terminal 11, the chip is now in power down mode.

The row selection circuitry in the system of FIG. 1 includes predecoding and multiplexing capabilities, which provide important advantages. 8 each row address pin l-A on terminal 12
0-A 7 is added to one of eight buffer circuits 30, each of which is connected to a pre-decoder 32 from A2 to A7 pins 1~ on a line 31 going to a row-dividing decoder 33 for AO and A1. Address J: and complementary voltages A and A are generated. A 3fJ predecoder 32 is used for six address bits A2 to A7, and each of these circuits produces four outputs on line 34, which is the input of a 1-of-64 row decoder 35. Decoder 35 has 64 tree outputs 1936, of which only one is high and all others are low for a given address A2-A7.

I! 36 is applied separately to 64 4111 selection circuits 37, each having an output 13 of 411JJ, which are the row lines of array 10 and extend to all eight groups 10-1 to 10-8. There is. Each selector 37 is an equity v1 decoder 3
Receives input 1!1138 from 3 to 4 tree and sets address A
It functions to select one tree among the four tree lines 13 according to the O and A1 bits.

2 ([3rd section showing a detailed circuit diagram of the buffer circuit 30 of Ia)
In the figure, there is J3, and the input terminal 12 is for two enhancement men! - Connected to the gates of transistors 40 and 41. The first human-powered transistor 40 has an impulse load 42 and is connected to ground via a C transistor 43 whose gate is at V2. The output 44 of the first stage is a natural L transistor 4 that shares the grounded transistor 43 as well as the second human-powered transistor 41J3 and its parallel grounded gate depletion transistor 46.
Connected to gate 5.

Thus, the current of all transistors 40, 41, 45, 46 flows through transistor 43. The node 44 is also connected in series with the input transistor 41 to the gate of the depletion transistor 47, J3, and the natural transistor 48 in series with these transistors has a C on the gate.
It has an E signal and works to enter power down mode. The source of transistor 47 provides output line 31-1 to
The drain of transistor 41 provides an output line 31-2. If input 12 is high, transistor 41 is on and Δ and 80 are low. One inverter transistor 49 with depletion load 50 receives the A signal on its gate, and this inverter drives the gate of depletion condenser load 51 in the final stage. 1st
The output node 44 of the inverter 40 is connected in this final stage to the gate of an emphasis 1 transistor 52 which, like the power down transistor 46, has a parallel grounded gate depletion mode transistor 53.

Natural transistor 54 with GE on its gate provides a pull-down function during power-down II, similar to transistor 48.

The purpose of transistor 45 is to balance the current through transistor 43 between 0 and 1, so that the voltage on node 55 remains approximately constant. The voltage on node 55 provides a small back bias to transistor 40,
■The operation for low input values is appropriate °r even when
TL margin is sufficient.

Transistor 47.51 has an inverted output from the previous stage on the gate 1 to speed up operation compared to a standard gate-to-source shorted depletion load case. In this way, the gate rises earlier than when connected to each source, and transistors 1 to 47 and 51 are turned on earlier.

In power down operation, transistor 48.54 is turned off by the GE large input shown in FIG. 2Q. The control circuit generates GE from PD/)'GM and this voltage is PD/
Complementary to PGM. When transistors 48,54 are off, A and A are both high during power down mode, and A8 and AI are 1cor. transistor 46.5
3 function is to leak to output during power down and 89
is to hold it low. In active read mode, GE is high and transistors 48 and 54 are fully conductive, so that A and A are at the same logic state as are A and A8 and 161.

FIG. 4 shows one of the three predecoders 32. This circuit consists of four parallel, low-threshold natural transistor pairs, five
6 and they are A on Game I.

A, [3, has 13 outputs. These four parallel pairs are in series with four natural transistors, A'' and A'' on the gate. Transistor pair 57 has B” on the gate.
and 8 are grounded through the transistor 58. The four outputs 34 are transistors 5
It is taken out at No. 59 of 6.57ff'J.

All A and BI communications] are below node 59,
A and B (A N is greater than or equal to node 59. This is advantageous for J3 in power-down operation.

At the 48th ffi, together with the row division decoder 33, AO and △
A 1-bit user cover 30 is shown. The input buffer circuit is similar to that of FIG. 3, except that transistor 48.54 is not present and depletion transistor 46.53 is omitted since the power down function is not used.

8" or does not occur on B* output.

Row division decoder 33 includes four NOR circuits with transistors 60, A, A from buffer 30 for the AO and A1 address bits.

B, 13 are connected to the output pair 31, respectively. Each NOR
The circuit has a depletion load 61 and an inverter stage 6
One of the four outputs 38 is generated by a push-pull output circuit with a push-pull transistor pair 63 and 64 fr.

FIG. 5 shows the 641111 decoder 35 along with the 1-of-4 decoder 37 and the 641111 path that applies the programming voltage 1)p to the row line. Three sets of 44134 extend along the decoder and provide inputs to the gates of three transistors 65 in the 64 NOR circuits.

A different combination of each of the three sets of lines is used in each NOR circuit, and only one is selected for a given code on line 34. Three parallel transistors with G on the gate
E and is connected in series with a power down IITl transistor 66 having a depletion load 67. In power down mode, GE is low and transistor 66 is off, so the output is high and no current flows through any of the 3×64 or 192 gA transistors 65. In normal mode GE is high and the drop is very small since it is a natural or low threshold transistor. For the selected NOR circuit, all gates of the three transistors are D- and line 36μ high. Also for all others, at least the gate input of 111Q is high and 36 is low. When line 36 is low, inverter 68 in decoder 37 outputs four transistors 6
This decoder 37 generates a high output to the gate 4 of the decoder 37.
Keep all rows 813 of the book at 0-. For one tree line 36 to be high, a set of four transistors 70 is turned on, connecting 41138 to the four row lines 13. Since only one tree among these 41138 is high, 25
Only one tree among the six rows l1113 becomes high. Depletion transistor 7 with vcc on the gate
1 serves to prevent the high voltage present during programming from destroying the driver transistor 69, and these devices 1 turn off with a high voltage on their drain.

For programming, one selected tree among the 256 row lines is set near v and p, and the rest are set low (vl).
, the input 20 includes several sets of three series transistors 72, 73.
．． 74 to each row fd13. v 1
The resulting VPRm command is connected to the gates of all transistors 72, so that C8 and PD/ '1
) VPR programming is possible only when GM is 0- and voo is high;
is low and transistor 72 is turned off.

Transistors 73, 74 are all unregulated depletion devices with a threshold of approximately -4 volts. The effect of series combination is argument 1! l! 1 line 13 to vI)p, and transistor 6 for all others.
Since 9 is on, it remains vss.

The row decoder circuits of FIGS. 3, 4, and 5 have several advantageous features. The slowest output A (or B) in the address buffer 30 is only the inversion of 2 gA from the address input terminal 12, and therefore the speed is good. The second human powered transistor 47 is also used to speed up the response of positive input transitions. separate A
By supplying outputs such as and AlA and 8, the buffer can be powered down to a minimum power state and the predecoder 32 can be brought to a zero power state at the same time.

By using the predecoder 32 together with the row decoder 35, a driver device f! You can halve the number of 65, and then add 1111 to each row line 13 of the 4 tree.
4 NOR circuits can be used to further reduce the required drivers by two.

Thus, a 1 in 256 decoder requires only 64 N01 circuits, each with 3 transistors 65.
Reducing the number of O-dings in the device compared to OR circuits is highly desirable. The row split or multiplex decoder 33 uses a simple NOR circuit with two input quadrant zeros employing a push-pull output stage 63,64 for improved driving. The row decoder 35 is a three-power NOR circuit, and each NOR circuit has another transistor 6 whose gate is connected to CEk to power down a, 11.
111 is performed and GE is low for power down.

In FIG. 1, the column select circuit includes a four-person buffer 30, which is the same input buffer used for the AO and A1 address bits. The eight addresses and complementary outputs from the four buffers on lines 75 are applied to a 1 of 9 decoder 76 which energizes one of nine output lines 77 to the ground selection circuit 15. . Thus, one of the nine ground wires in each group 10-1 through 10-8 is first selected before the output column line is selected. Line 77 is also an input to a column select decoder 78, which uses 88 and 88 on the two trees 670 as inputs to select one of the nine lines 77 on either side of the tree that is high. Select. One out of eight outputs on line 79 are connected to column selector 16.

It is important that the virtual ground selection on line 77 be decoded and obtained as quickly as possible to minimize access time. To activate column selection on line 79, press "
extension can be tolerated.

Virtual ground selection! The poor operation of a15 has a greater influence on the access time than the operation v111 of the column selector 16, which can tolerate delays. Thus, the virtual ground selection is directly decoded from 0-Δ11 to the address input and used to activate the ground selector 15, and then the ground selection on 11a77 is used in the decoder 78 along with the LSB and AO of the column address to select the column. Occur.

FIG. 6 shows the decoder 76 in detail. The address and complement of AO to A11 from buffer 3o on line 75 is a set of 9g! 4, two of the N Or< circuits are illustrated. To select one out of nine, seven of the NOR circuits have three transistors 80, and the remaining two have four transistors 80. The N0Rn path has a depletion load 81L1j and a power down transistor 82 that is continuously driven by CE. Output node 83 has an inverter transistor 84 driving one output transistor 85 and a direct drive threshold output 1
- connected to a modified push-pull circuit with transistor 86; Transistor 87 with GE on the gate
．． 88 provides a power down mode where all 1177 are held low. Transistor 89 provides the same function as transistor 71 in the row decoder. The circuit that applies the high voltage to 18177 of 9 selected during programming includes the three series transistors 72, 73, and 74 used in the row lines of FIG. However, in this case transistor 72 has V on its gate rather than V l) R.
It has a PC.

FIG. 7 shows the selector 78 in detail. Eight quadrants and/or logic circuits having input transistor pairs 90 are responsive to nine ground selection lines 77, and a transistor pair 91 common to all of these eight logic circuits is connected to A8 on line 75.
13 and A8.

Each logic circuit has a depletion load 92 and drives an output transistor 93. This output stage has a diplegcon load 94 and a common power down gate 95 common to all eight. Column select line 79 is connected to these output circuits via a series transistor 96 having PE on its gate.

The programming high voltage is generated by a series circuit including transistors 72, 73, 74 connected to each line 79 as before. Transistor 96 isolates the high voltage on line 79 that is high during programming to prevent the high voltage from discharging through depletion load 94 to vCC.

In FIG. 8, the cell array 10 is a matrix array of memory cells 10', each of which has a control gate 101, a source 102, a drain 103 J3, and a floating gate 104 in one field between the source and drain channel and the control gate 101. is a programmable insulating field effect transistor.

The υ1611 gates 101 of all cells in each row are connected to a set of row lines or x-rays 13. In the embodiment, there are 256 trees of l1113 from the X decode circuits, and as mentioned above, they select 1 out of 256 by exposing the 8-pit t-X or row address on line 12. In read mode, selected one tree of line 13 goes high and the other remains low.

The drains 103 of the adjacent cells 10' are commonly connected to the Y output ai05, and in the embodiment, 64 1a105 are partitioned to generate an 8-bit parallel output 11 from the bag type, and each line 105 connects two rows of cells. 10' output, so there are 8 groups of 16 cells in each group, each group containing 8 tree lines 105. Line 105 is load transistor 12
1 to vcc, and 8 transistors 16-1
~16-8, thus Y output line 106
connected to. (There are eight separate I!j 1108s, one tree in each group of 16 cells wide.) Transistor 16-
Gates such as 1.16-2 receive the column select voltage on line 79 (
1, and they apply a logic 1 voltage (immediately for programming v!, p) to one of these gates based on the 4-bit string address on input bin 14 and hold the rest at vss. 11 out of 16 pit addresses in a group act like this? 8I111! ! To select it, use the MSB 3 bits A9-A11 of the 4-bit Y address A8-811.
Only requires virtual contact! ! Depending on the configuration, LSB address pins 1-A8 are required.

The sources 102 of adjacent cells 10' are commonly connected to another set of column lines 107 which act as ground lines. Nine tree lines 107 are required for each group of 16 cells 10'. That is, MX
The number of ground wires for N arrays is (N/2)+1 trees. Each line is connected to vcc via a load device 1o8, and to ground, ie, vss, via ground selection transistors 15-1, 15-2, etc. The gates of all these transistors 15-1 etc. forming the ground selection 15 are 1i
177 to the selector 76.

Ground selection 76 acts to energize only one of lines 77 for a given Y address, so only one of transistors 15-1, 15-2, etc. is conductive.

A small portion of the cell array of FIG. 8 is shown in FIG.
cells 10', four x address lines 13, and Y output! 1
1105, ie, five metal pieces forming the ground wire 10'7. As shown in the cross-sectional views of FIG. 9 and FIGS. 10A to 10D, the source and drain regions 102
, 103 are formed by N+ diffusion regions in a continuous wear of an X-shaped moat region, said moat region including a channel region 109 between each source and drain and contact regions 110, 111 for contacting the metal and the moat. There is. Metal output 1
i1105 is a3 in contact area 110 and mote common N
The metal ground 11107 contacts the area 112.
1, the common N+ region of the motes is touched. Each common area 112 has 113 four transistors 10, respectively.
′ form the source or drain. The cell array is formed in the plane of silicon par 114, and a thick field oxide 15 covers the entire plane except for the moat region. A P+ channel stop region 116 overlies the field oxide in the conventional manner. The shallow N-arsenic implanted regions 102', 103' act as extensions of the source J3 and drain regions 102, 103 where the control gate 111 overlaps the 70-ing gate 104, and the P region 117 formed by rapidly diffusing boron. provides advantageous programming efficiencies over conventional P-tanks. A gate oxide 118 1t914 insulates 70-TEG-1 from channel 109, and a thin oxide layer 119 insulates 70-TEG-1 from control gates 1-101. A 'n layer of deposited interlevel oxide 120 separates the second level polysilicon forming X1113 and control gate 101 from gold jil lines 105,107.

The EPROM cells 10' are programmed by applying a tS voltage of approximately +18V to the drain 103 and source 102 and holding the control gate of one selected cell at V, . The high fri current flowing through the cell causes electrons to be emitted through gate oxide 118 to form floating gate 1.
Charge 04. This makes the threshold voltage of the cell approximately v
It acts to increase CC (usually +5V). The charge on the floating gate remains indefinitely. 5A
Erasing is performed by exposing the floating gate 104 to ultraviolet light and discharging the floating gate 104.

For proper operation, the selection circuit and cell matrix must comply with certain conditions. Programming the cell requires a voltage of approximately 118V on drain 103 and a voltage of 0.5V on drain 103.
~3.01^ source-drain current is required. E
15-60μ for reading P ROM matrix building
It is necessary to detect a current in the range of .

For example, in the read operation of the circuit shown in FIG.
When one of the transistors 13) is high (cc-vt), transistors 15-2 and 16-2 are turned on by ground and the column selector. The other transistors 15, 16 are all off. Transistor 15-2 is the load terminal fi10 on this line.
8a is pulled down, the current of transistors 10a' and 10c' is caused to flow to the ground, and the voltage of node 111a is approximately 0.2 to 0.3V.
The shift must be large enough to maintain the level at a very low level. Load 108b needs to charge node 111b to the point where cell 10'b is turned off. This eliminates the need for sense amplifier 17 connected to output 1i 1106 to charge to and beyond the capacitance of node 111b. Due to the body effect of transistor 10', cell 10'b turns off at a low voltage on node 111b.

The body effect is large due to the P+ region in the channel used in the fabrication of these transistors.

To program cell 10'a, use the same transistor 1
5-2.16-2 is turned on for a read operation (others are A)), in this case the on transistors 15-2.
16-2 is the transistor 72.73.7 as described above.
4, a large positive voltage vpI) developed in the circuit with 4 is on the gate. Transistor 15-2 must be large enough to hold node 111a at approximately 0.3 cm and pass 1 to 3 m8. Transistor 16-2 has a large voltage on its drain, 1v1. produces a large voltage on node 110a. Load 108b is again connected to node 111
In this case, cell 10'b does not program. The +3V voltage on node 111b is applied to cell 10'.
Prohibit program b.

Each column 11105 is connected to VCC by load transistor 121.
The gates of these load transistors have a reference voltage Rh. Column line 105 thus serves as the output node 122 of the inverter circuit, with a selected node 122 at a voltage level that depends on the ratio of 0-domain transistors to the selected storage cell 10'. For a programmed cell with a charged floating gate, transistor 10' is not conducting, line 105 (node 122) is at maximum voltage, and an erased cell 10' with a discharged floating gate is [ 11105 is the minimum voltage. The approximate midpoint between these two extremes is the difference! II t
? This is the reference point for the amplifier 17. Each sense amplification: S1
7's solo effort is selected by Y from node 122!・Run Rasta 1
6-1, 16-2, etc. and the line 106. The other input is from the reference voltage generator circuit described below.

FIG. 11 shows the reference voltage Rh used for the load 121 of the cell array, the voltage V rat of the differential sense amplifier, and the quasi-voltage R.
The sense amplifier 17 is shown along with the circuitry that generates V.

The base Q used as a single power source of the sense amplifier 17! ;
M voltage V raf is E P It OM transistor 1 manufactured similarly to transistor 10' in the cell array.
0'' and Q load transistor 121 (but channel width is 2ffS to create an intermediate point) from a circuit including a load transistor 121'.Load transistor 108' and ground transistor 15' are provided in a "virtual ground" string. Load 108 and grounding device Q to line 107
The voltage to the gate of a similut such as 15-1 is approximately (Voc-V,).

That is, it is the same as the selected voltage of one of the lines 77,
Therefore I! in the reference generator! ! 107' indicates exactly the same voltage, impedance, etc. as the selected line 107 in the array. Transistor 10'' has a voltage (generated by transistor 123) on its gate, which is also approximately (■.

, -Vt) and is equal to the voltage on the selected X-ray 13. The circuitry below node 122 in the cell array is thus simulated on one side of node 122', and the operation is the same as that of the cells in the array, with changes in supply voltage, temperature, aging, and threshold voltage processes. Track any fluctuations due to fluctuations, etc. Node 122' on the load side
is connected to Vcc through two load devices. On the load side, No. 1122' is connected to V via two load devices.

Connected to 0.

Initially, a load transistor 121' is used corresponding to one of the load transistors 121 of column line 105 of the array.

Transistor 121' has transistor 121 on the gate.
has the same reference voltage r<h. This reference voltage Rh on line 124 is . J for a device where = +5■
It is 3 and 4■. Rh is chosen to optimize the voltage change on node 122, and the voltage drop is not a full logic level sufficient to be sensed. Then different on the gate! 3m dog transistor 1 with voltage R1
25 is in parallel with the negative v11-transistor 121'.

In the example J3, the load transistor 121' has a channel twice as wide as transistor 121, so the impedance is half.61iii Another way to achieve the same effect is to connect two transistors 10'' in series instead of one. and use the same load transistor 121' as 121. Both have V rat at node 122'.
A voltage is generated that is half the voltage change on dark node 122 between the programmed and erased states for the selected transistor 10'. At time 126, select x-ray 13 goes high, as shown at Fi 127 in FIG. 11a.

×3 due to circuit design! ! The constant voltage can be S full wave V from V to Vcc or smaller from vss to C (VC, -V,). y1128
As shown by , the voltage on node 122 is at a level determined by the Rh voltage shown by lQ129 since transistor 10' is not turned on if the selected cell is programmed (flooding go 1 to charge). On the other hand, if the selected transistor 10' is erased, the node 122 starts discharging fi+ at time 130 when the voltage 127 on the selected row line 13 exceeds the threshold voltage j↓ of the transistor 10'. As voltage 127 continues to increase, the current through transistor 10' increases and the voltage on node 122 increases until it plateaus at a level dependent on the 1-<h level, as shown by curve 131. If R h is too low, node 122 will be grounded and the column line will have to be charged all the time, which is more than necessary and undesirable. If Rh is too high, level 128 is too high ■. , will be near. Vr
ef is the voltage level 132 (for programmed transistor 10') and especially erased transistor 10'.
level 13, which is the final level of node 122 for
It can be seen that it is at an intermediate level between 3 and 3.

The functions of the second resistor 1 to transistor 125 and the reference voltage R1 are performed during the time the device is in power-down mode.
This is to offset V ref to a level higher than the normal level 134 in the diagram. The reason for this is that in power down mode all rows 9113 and virtual ground selection 77 are at ■ss and all column lines 105 are at maximum level. Upon exiting the power-down mode, the selected column line 105 can be discharged or de-energized depending on the state of the selected cell 10'. If dead wire 105 is not discharged (if selected cell 10' is programmed), valid data is already present on wire 106.

Once select line 105 begins to discharge (if selected cell 10' is erased), there is no valid data on line 106 at the input of sense amplifier 17 until line 105 is below the yrer value. The function of R1 and load 125 is to make vrcr higher than normal, so that when column aios discharges along curve 131 it crosses V rat level 134 in period 9 and senses valid data at fi' 1111. Can be done.

In the power-up state, the load transistor 121' has Vrcf at a DC level smaller than the DC level υIIIL, R1 is Rh17). Thus under power-up conditions transistor 1 in the V rat generator
25 is cut off and Vrcf is controlled only by Rb. When the device is in power down mode, R1 is higher than the Rh level 129 and the load transistor 125 takes control and y - rer becomes more n. Upon exiting the power down mode, the second load 125 is slowly turned off as R1 becomes lower due to the RC delay. This gradual turn-off is necessary to prevent VrCt from returning to normal too quickly, but Vrer must be near the normal level 134 during the access time so that the low-to-high column line transition is The cycle after sensing must not be abnormally slow.

The 16 circuits used to generate RhJ3 and R1 are shown in FIG. Rtl is a fixed level 129 generated by a split circuit with three transistors, an impression load 135, a low threshold device 136, and a nymphancement transistor 137. Output node 124 is at Rh level. A set of similar transistors 13 with different sizes
5-137 generates the R1 level on spring 138, and for power down, transistor 139 in parallel with transistor 135 turns on and increases the voltage on R1.

Therefore, the signal QCE goes low, turning off transistor 140 and node 141 becomes the depletion load 14.
2 makes it vCc. MO8 diode pair 143 acts as a resistor and the gate of transistor 139 is kept near cc as long as the power down mode exists. At the end of power down, CEC goes high and node 1
41 becomes low, and the gate of the transistor 139 is discharged according to the time constant of the resistor 143 and the Re circuit of the MOS capacitor 144.

Sense amplifier 17 may be any of a number of differential amplifiers known to those skilled in the art. For example, a differential amplifier circuit is shown in FIG. 11, and the differential amplifier circuit can be used as a sense amplifier. The circuit consists of a balanced pair of driver transistors 145 along with depletion load transistors 146. transistor 14
7 grounds both driver transistors and has a bias on the gate to operate it as a current source.

One input 148' is connected by output line 106 to node 122 on select column line 105, and the other input 149 is connected to node 122', the yrer voltage. The outputs 150, 151 can be VCC or V depending on the polarity of the voltage on the human power 148°149 or 16°.Several stages of the circuit shown in Figure 11 are usually cascaded to form a high-interest 1;1 sense amplifier. do. The outputs 150, 151 are then connected to the inputs 148, 149 of the next stage 152, and so on. Final output 1
1 is one of the last lines 150 or 151 and indicates a full wave logic level.

It is important to note that differential sense amplifiers sense voltage rather than current. Node 122 or 122'
The above voltage only needs to charge the gate 1- of the input transistor 145, and other than this transition there is a large voltage? There is no first-class 0-ding. If we use different selection mechanisms in this way, Y
No voltage drop occurs in the selection transistor 16-2 or other decode transistors.

All I! j 105 is charged through load 121 and all grounds 1107 are charged through load 108. Only selected column lines 105 are discharged during a read cycle; they are not necessarily grounded.

In the bower 1 condition, all the X selections 113 are grounded and all the ground selection lines 77 are grounded, so that the column III 05 is not discharged and no DC power is dissipated. All columns 1i 1105 are steered to bias point 128 in Figure 11a, so there is no delay in precharging 7 rays at the end of power down.

The access time at the end of power-down must be the same as in normal operation.

It is a feature of the 7O-ring gate device 10' that it is programmed only when operating at sufficiently high drain 103 and gate 101 voltages in the saturation region. The device does not program in linear mode. When applying programming voltages to the virtual ground array, care must be taken to ensure that only selected Vt locations 10' to be programmed receive sufficiently high voltages in the saturation region.

A circuit diagram of the high voltage programming υ control circuit is not shown in FIG. When vrjl) on bin 20 reaches a high voltage level of approximately +21V, a voltage divider formed by five transistors 154 develops a voltage on node 155, which switches two inverters 156 to write on line 157. Generate enable command WE. Thus, if v and p are low, WE is low, and if vI)l) is high, WE is high. Further, the WE command is generated by another inverter. Logic circuit 158 selects chip C8 from bin 21.22 and power down/program PD/
Along with the PGM command, the WE (or WE> command is received, and in response, a program enable command PE is generated in [1159. ■ When o is high, the program enable command is active broached, C8 and PD
/ P G M HaaI! I! O tear 6, also bin 2
1.22 is high, a program inhibit condition exists and PIE is high. Transistor 160 receives the PE command on its gate and produces an output on node 161 with a series negative output, which is the VPR command used in the high voltage circuit of row address output 13 of FIG.

Thus, when P[E is low, node 161 vl)l
), and all transistors 72 of 2561111 of 256 row lines 13 are turned on. Also node 1
61 drives the gate of transistor 162 in series with 4wA transistor 163 in a voltage divider, which together with inverter 164 generates a voltage on the gate of transistor 165 to generate vPC. Natural depletion 1-transistor 166 in series with transistor 165 and shorting transistor 167 develops a voltage on node 168 that is high when PE is low and V, , (J
There is some delay because VPR is high. As shown in FIGS. 6 and 7, vPC is applied to each transistor on all lines 77, 79 for high voltage circuit ground selection and column output selection.

No n-gramming occurs. A programming circuit that applies high voltage input data to the select transistor 16 select column line 105 is shown in FIG. In-buffer 170 is enabled only when PE on 1159 is low. The output of the buffer 170 is connected to each J3 by a high voltage circuit comprising an inverter stage with a driver transistor 171 having a series negative 11172.173 of 211M to the gate of the transistor 174.175 when the data input is low. Generates high voltage. As a result, ■, the cape pressure is line 17
6 to line 106. Transistor 177 in the high voltage circuit operates similarly to transistor 71 described above. When the array discharge command ARD is high, the transistor 178
will ground 1i1176.

In operation, the programming circuit operates to apply a high voltage to only one cell in each group in the programming mode, but there is no high voltage in other modes. ■6. can be held high, so there is no need for external circuitry to rapidly switch this high voltage, and in high lii circuits this external circuitry is necessary, creating undesirable transients. When device δ is deselected (powered down and on), command P[ on node 159 is high and VPR
And vPC through Todranjisk 160.167? Maintain at ti pressure. Next, the high voltage supply is changed from the lco state to the high state s v pp, and this high voltage is applied to the node 1
A sensed WE occurs at 55. V110 remains high during the Jlivc period of the programming sequence. The device is selected (i.e. powered up) by C8 and PD
When /PGM is low and WE is high, programming mode is entered and PL is low. Before VPR goes high, all column lines 105 except the select line and virtual ground line 107 are at C normal bias near v due to a-to-dranges-9108,121. Selection line 13 is ■. , but all cells 10' on this line are performing triode operation, even if the data in bit is low and 1106 is ti1
Even if it is charged to high through 176, Boo 2 etc. [V on the gate. Since it has only 0, the line 105 is changed to ■8. Do not allow it to reach nearby voltages. Here, the vPR command on the node 161 begins to be charged 1i1 to the (DI) level via the depletion load, and vPC is held at the ground voltage by the transistor 165. When V P R on node 161 rises above approximately 10V, timing circuit 162-1
64 begins to release the vPC. It takes approximately 10 μs for VPR to reach v,p, which is 9II above VPR! The dlM from the beginning of iI until vPG starts to change is approximately 1.5μ.
It is s. Selected row l1113 is larger than selected column line 105♀
the programming voltage is reached, so that the source-drain paths of all transistors 10' in the selected row become highly conductive (regardless of whether the floating gates 10' are charged or not), and the The equilibrium charge sharing state is reached before becomes high. Next, when vPC is near V, assuming that the data input is low, that is, logic O, the selection line 79
The high voltage from line 106 can reach select line 105. This selection line 105'l
The pressure is v6. , the adjacent non-selected column line 105 and the virtual ground line ■. .

is pulled up by the high voltage of the control gate on line 13. However, only the selected cell 108' is saturated with sufficient voltage to perform programming, and the cell 10b' on the other side of the selected column 1i 1105 from the selected cell 108' is also saturated.
Since the source node 111b has a large voltage,
It cannot be conductive enough to make a gram. On the other hand, the source of cell 100' is grounded at node 111a via transistor 15-2, and the gate is vo via line 13, but the drain is near vCc via load 121, so this cell does not program. VPR and vPC are high up to 50-8, but tend to deprogram via mid-level oxide 119 (except for select node 111a).
This trend is significantly reduced because the charging of all nodes 111 causes the voltage across this oxide to be low except for cells 10' in a given row. The deprogramming effect will be reduced! This is because, since only node 11107 is grounded, other nodes can be charged, and the gate-to-source or drain voltages of cells other than the selected cell 10a' are reduced. The selected cell has enough time (maybe 10-5
PD/P when held at programming voltage (0+eS)
The GM (ie O8) voltage goes high, causing IT) E to go high, turning on transistor 160.167 and causing VPR and vPC to go low. At this point, the high voltage on selected column line 105 must be carefully removed. Discharging the large array capacitance through the unselected storage cells causes programming in the unselected cells. The bleeder transistor 178 thus provides a path for removing excess voltage from the common line via the select transistor 16-2, etc. and the common line 106. The extra voltage on virtual ground line 107 does not represent parasitic programming disturbances due to bias on the column lines. Array discharge voltage ARD is woody P
Complementary to D/PGM, but only occurs when VDD is high and therefore occurs in program inhibit mode of operation. The device is powered down during the program inhibit period.

A semiconductor device including all the systems shown in FIG. 1 is disclosed in the above-mentioned patent no.
It is made of 2Φ level polysilicon, N-channel, self-line process as described in 3, and employs a double diffusion step as described in patent application S. of Texas Instruments dated September 4, 1979. , N, 072.50
BD Gramming Enhancement 1 disclosed in No. 4
) Generate ten areas.

Standard enhancements generated in the process used
~Mode MOS transistor (40.41. in Fig. 5 etc.)
49) is ■. Assuming that , is +5v, +13 is +0.
8-1. The result of a normal blanket implantation of a natural transistor protected by a photoresist 1-4 with a threshold voltage of Ov and this threshold (1) is the result of a natural 1-run raster 45.48.54 etc. A third type of transistor has no implantation and has a threshold of approximately +0.2 to ←0.3 V, resulting in a low source-to-drain voltage drop, which is advantageous in many parts of the illustrated circuit. is 42.
A standard depletion con transistor such as 47.50, with a blanket boron implant for semi-enhancement devices, accepts selected N-type implants to achieve a threshold of approximately -3.4V. The fourth type is a ``natural depression'' device, which accepts an N-type implant rather than a boron implant, so it is approximately -3,8 to -4,
With a threshold value of Ov-, these devices are used, for example, as high voltage circuit transistors 73,74.

The decoding circuit described above can be used in other types of memory devices, such as ROMs and read/write memory devices, rather than just EPROMs. Similarly, input buffers as well as sense circuitry and power-down features are useful in other types of devices.

Therefore, although the invention has been described in terms of illustrative embodiments, this description is not to be construed in a limiting sense. Other embodiments and various modifications of the invention will be apparent to those skilled in the art upon reviewing this description. The appended claims are intended to cover all such modifications and embodiments as fall within the true scope of the invention.

1 Effect of the Invention 1 According to the present invention, it is possible to provide a small-sized semiconductor memory device in which the output line and the ground connection line of each adjacent memory cell are supplied.

[Brief explanation of drawings]

FIG. 1 is an electrical block diagram of a 70-gate EP ROM type semiconductor memory device using features of the present invention, and FIGS. 2 and 2' show voltages at various points in FIG. A timing diagram shown as a function; FIG. 3 is an electrical circuit diagram of the input horn buffer used in the device of FIG. 1;
4 is an electrical circuit diagram of a predecoder circuit used in the device of FIG. 1, FIG. 4a is an input buffer for Δ0 and A1 bits, and FIG. 5 is a row decoder and selection circuit used in the device of FIG. 1. 6 is an electrical circuit diagram of a decoder used for virtual ground selection in the system of FIG. 1, FIG. 7 is an electrical circuit diagram of a column selection decoder used in the system of FIG. 1, and FIG. The figure is an electric circuit diagram of the cell array of the device shown in FIG. 1, FIG. 9 is an enlarged view of a small part of the semiconductor chip without showing the physical layout of the cell array of the device shown in FIG. 1, and FIGS. Figure 11 is a cross-sectional α view along the lines -A, BB, CC, D-1) shown in Figure 1. Electrical diagram of the sense amplifier and reference voltage generator, Figure 11a
The bias point of the line, FIG.
．． FIG. 2 is a circuit diagram of the II i1 circuit. 15...Ground selection 16...Column selection 17...Sense amplifier and data in buffer 23
. . . Control and clock generator 30 . 1 ground selection 78...8+1 row selection

Claims (4)

[Claims] (1) (a) non-volatile memory cells arranged in a matrix, one of the memory buildings in each row being connected to a row line and the other being connected to an output line; (b) the row A storage device comprising: (c) means for selecting one of the output lines and connecting it to ground; and (c) means for selecting one of the output lines and connecting it to an output. (2) The row line connecting means receives an address input, selects one of the row lines in accordance with the address input, and selects one of the output lines. Storage device described in section. (3) The memory device according to claim 1, wherein the memory cell has an insulated gate field effect transistor whose first terminal is a source region and whose second terminal is a drain region. (4) The memory cell of claim 3, wherein the insulated gate field effect transistor is a floating gate electrically programmable read-only memory device having a control electrode and a floating gate thereunder. .