JPS6323743Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is for displaying input data through key operations on a multi-digit display equipped with a plurality of display tubes. The present invention relates to a display circuit that blinks to make it possible to recognize data input positions, overflows, erroneous operations, etc.

For example, in office processing equipment at agricultural cooperatives, a large amount of data such as agricultural cooperative codes, farmer codes, agricultural products codes, etc. is processed using code numbers. There are display devices that display many types of input data in a series without breaks.

At this time, different data are displayed in descending order of common frequency, and if input data at the head (for example, agricultural cooperative code number) is common, it is left as is and displayed, and input data at the rear that is different (for example, farmer code number) is displayed. ) can be replaced and displayed using key operations, making the operation even easier. In this case, it is necessary to display from which digit of the display the different input data will be input.

The present invention was developed in view of the above points, and includes a low-frequency oscillator for blinking the display tube in an ordinary display circuit, and uses NAND output of the output pulse of this oscillator and one or more specific pulses in the display circuit. The display tube of a specific one or more digits is blinked to display data and digit positions on the display tube.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

Reference numeral 1 denotes a clock generator that generates a pulse with a basic cycle timing of, for example, 1 kHz.A timing counter 2 is connected to this clock generator 1, and a numeric digit counter 4 is also connected via an AND gate 3. ing. 5 is the data input keyboard, "00""0""1" ~ "9"
A numeric keypad 6 and a function key 7 are provided. The output side of the numeric keypad 6 is connected to a number memory 9 via an AND gate 8. The output side of the numeric value memory 9 is connected to a central processing unit (CPC) (not shown) for calculation and control, and is connected to a central processing unit (CPC) (not shown) for arithmetic and control purposes, and is connected to an 8-digit display consisting of, for example, 8 display tubes via a display driver 10 and an AND gate 11. It is connected to the display device 12. The output side of the numeric digit counter 4 is connected to the other input side of the AND gate 8, and a pulse signal is sent every 8 cycles for storing the numeric digit of input data from the numeric keypad 6. pulses).

The output side of the timing counter 2 is connected to each digit of the display 12 via a digit driver 13, and is also connected to the number memory 9. The output side of the AND gate 8 is connected to the other input side of the AND gate 3 via a delay circuit 14 and an inverter 15, and the output side of the AND gate 8 is connected to the other input side of the AND gate 3 through a delay circuit 14 and an inverter 15. By removing one pulse, the timing of the pulse from the output side of the number digit counter 4 is shifted one digit to the right.

Next, 16 is a low frequency signal for blinking (for example, 10
This oscillator 16 is a low frequency oscillator that generates
is the display driver 1 via the NAND gate 17.
It is connected to the other input side of an AND gate 11 inserted between 0 and the display 12.

Further, the output side of the number digit counter 4 is connected to the other input side of the NAND gate 17.

Next, the operation of the present invention will be explained.

Pulses for digits of basic cycle timing are sent to the display 12 from the timing counter 2 via the digit driver 13 so as to sequentially shift the digits from the left side in the figure to the right side. This digit pulse is based on the output pulse of the clock generator 1. For example, in the case of 8 digits, the 1st, 9th, 17th, etc. pulses are used to create the timing pulse for the 8th digit. The 7th digit timing pulse is created using the 2nd, 10th, 18th, etc. pulses, and the timing pulses up to the 1st digit are created in the same manner. Here, when the numeric keypad 6 is not pressed, the display driver 10 outputs a "0" signal as input data to all digits, and the number digit counter 4 outputs a pulse synchronized with the pulse for the leftmost digit. is output. Together with the signal from the digit counter 4, a low frequency signal from the low frequency oscillator 16 is sent to the display 12 via the NAND gate 17 and the AND gate 11, so that the leftmost digit "0" blinks. This state indicates that when any one of the ten keys 6 is pressed, a number will be displayed in the flashing digit.

Therefore, assume that "1" is pressed on the numeric keypad 6 and "1" is entered. Then, the input data "1" of the numeric keypad 6 is input by the signal of the number digit counter 4.
is stored in the number memory 9 via the AND gate 8. Then, in the number memory 9, the target address (leftmost digit) is selected by the signal from the timing counter 2, and this data "1" is input to the leftmost digit via the display driver 10 and the AND gate 11 and displayed. . On the other hand, the input signal of numeric keypad 6 is AND gate 8
Since it also enters the delay circuit 14 via the delay circuit 14, a pulse corresponding to one timing pulse appears from the delay circuit 14 around the time when the numbering is completed. That is, since this pulse signal is inverted by the inverter 15 and input to the AND gate 3, one pulse is removed from the signal sent from the clock pulse generator 1 to the numeric digit counter 4. As a result, the number digit counter 4 counts "8", but since one digit has been removed,
The output of the digit counter 4 is shifted by one, and the output of the digit counter 4 is synchronized with the timing pulse of the second digit from the left end. The pulse signal of the digit counter 4 shifted by one digit is sent to the NAND gate 17 together with the 10Hz pulse signal from the low frequency oscillator 16.
, the NAND output is sent to the display 12 via the AND gate 11. Therefore, due to the pulse from the NAND gate 17, the display of the input data "0" inputted to the second digit from the left end from the display driver 10 repeatedly blinks at a cycle of 10 Hz. And the number digit counter 4
The output of is shifted one digit to the right, so that the leftmost digit "1" remains lit. Therefore, the key operator can easily recognize the position of the next digit.

Thereafter, the blinking position is shifted to the right every time a number is entered on the numeric keypad 6, and the operation is substantially the same as described above.

In the embodiment described above, the pulses from the clock generator 1 are directly counted by the preset digit counter 4, and a pulse is output every count "8" to make each digit blink sequentially. A frequency dividing circuit that divides the frequency into half, for example, is inserted between 1 and the number digit counter 4,
If this frequency-divided pulse is extracted by the inverter output after the delay circuit, the display tube can be moved by blinking two digits at the same time.

In the embodiment described above, an AND gate may be further inserted between the digit driver 13 and the display 12, and the output of the NAND gate 17 may be input to this.

Since the present invention is constructed as described above, in a display device that can display multiple digits, one or more specific digits can be blinked depending on the purpose of use, and the same display tube can display numbers, etc. and display the digit position. Can be used for both purposes. Also, when you enter a number using the keyboard, the data is entered into the flashing predetermined digit and the light turns on stationary, but the signal input to the keyboard becomes a signal to shift the number position by the delay circuit. The input data is sent to the digit counter, and the next digit starts blinking to indicate the data entry position. Furthermore, simply by inserting a delay circuit, the next input data digit is sequentially blinked to clearly display it, which simplifies the circuit configuration.

Furthermore, when a frequency dividing circuit is inserted between the clock generator 1 and the numeric digit counter 4, a plurality of digits can be blinked at the same time.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of a display circuit according to the present invention. 1...Clock generator, 2...Timing counter, 3, 8, 11...And gate, 4
...Place digit counter, 5...Keyboard, 6...
Numeric keypad, 7...Function, 9...Number memory, 10...Display driver, 12...Display device,
13... Digit driver, 15... Inverter, 16
...Flashing oscillator, 17...Nand gate, 14
...Delay circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A timing counter generates a timing pulse based on a clock signal from a clock generator, and this timing pulse is sent to each digit of a multi-digit display via a digit driver. A predetermined address in the numeric memory is selected by each signal of the timing pulse, and the data at the address in the numeric memory entered from the data input keyboard is sent to the display via the display driver to the specified digit. The display circuit configured to display the display includes a numeric digit counter that outputs a signal for designating a blinking digit among each digit of the display, and a low frequency pulse for blinking the designated digit of the display. a low frequency oscillator that outputs a low frequency oscillator; a gate that uses the output of the display driver as a blinking signal based on the output of the low frequency oscillator and the output of the predetermined digit counter; A display circuit comprising: a delay circuit that outputs a signal for moving a predetermined number of digits of a multi-digit counter; (2) In the utility model registration claim described in paragraph 1, the gate connected to the output side of the numeric digit counter and the low frequency oscillator is a NAND gate, and an AND gate connected to the NAND gate and the output side of the display driver. Consists of display circuit. (3) In the utility model registration claim described in paragraph 1 or 2, the timing counter and the preset digit counter are started by a clock generator, and the timing counter and the preset digit counter are controlled by a clock generator. Set the frequency to 1/n (n=2, 3,...)
A display circuit in which a frequency dividing circuit is inserted to make n digits blink at the same time.