JPS63236032A - Method for exposing resist - Google Patents

Method for exposing resist

Info

Publication number
JPS63236032A
JPS63236032A JP62070996A JP7099687A JPS63236032A JP S63236032 A JPS63236032 A JP S63236032A JP 62070996 A JP62070996 A JP 62070996A JP 7099687 A JP7099687 A JP 7099687A JP S63236032 A JPS63236032 A JP S63236032A
Authority
JP
Japan
Prior art keywords
resist
transparent substrate
light
substrate plate
prevent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62070996A
Other languages
Japanese (ja)
Inventor
Shigenari Takami
茂成 高見
Tatsuhiko Irie
達彦 入江
Jiro Hashizume
二郎 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62070996A priority Critical patent/JPS63236032A/en
Publication of JPS63236032A publication Critical patent/JPS63236032A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the resist from reflecting a light transmitted through a transparent substrate plate on the stage etc., of an exposing device and to prevent it from sensitizing again the resist by providing with a light absorbing means on the lower surface of a transparent substrate plate. CONSTITUTION:The formed resist 3 is exposed by an UV ray through a mask 6 printed with a prescribed pattern 5 on a glass plate 4 placed in the upper position of the resist 3. In this case, an UV absorbing tape 7 is stuck on the lower surface of the transparent substrate plate 1 as the light absorbing means whereby the UV ray is prevented from leaking out from the lower surface of the transparent substrate plate 1, and from the irregular reflection on the stage of the exposing device, thereby disappearing the pin hole of the resist film.

Description

【発明の詳細な説明】 [技術分野] 本発明は、透明な基板上に形成したレジストの露光方法
に関する [背景技術] 半導体素子形成プロセスにおいては、シリコン基板上に
レジストをスピナー等で均一な厚みに塗布し、この上に
所望のパターンが印刷されたマスクを載せ、紫外線を露
光し、露光された部分以外のレジストを現像工程で取り
除くことにより、エツチングやメッキのレジスト膜を形
成する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for exposing a resist formed on a transparent substrate [Background Art] In a semiconductor element formation process, a resist is deposited on a silicon substrate to a uniform thickness using a spinner or the like. A resist film for etching or plating is formed by applying a mask on which a desired pattern is printed, exposing it to ultraviolet light, and removing the resist other than the exposed areas in a development process.

プリント配線用基板上に回路を形成する場合においても
、レジストの塗布方法はロールコータ−を用いて行なう
ものの、露光〜現像工程によるレジスト膜を形成方法は
同様である。
Even in the case of forming a circuit on a printed wiring board, the resist coating method is performed using a roll coater, but the method of forming the resist film through the exposure and development steps is the same.

このような露光〜現像工程を透明な基板に適用し、透明
基板上にメッキやエツチングを選択的に行なう為のレジ
スト膜を形成するような場合(例えば、ガラス基板上に
透明導電膜を形成するような場合)には、つぎのような
問題がある。すなわち、シリコン基板やプリント配線用
基板ではマスクの開口部(透明部分)を紫外線は透過し
、レジストを感光させ基板に吸収されるか、たとえ基板
面で反射されたとしてもレジストの厚さが非常に薄い(
数ミクロン)為、不要な所に光があたる可能性は極めて
少ない。ところが、透明基板の場合、第4図に示すよう
に、マスク6を透過した光はレジスト3を通過後、基板
1をも通過し、露光装置のステージ8等で反射する。こ
の反射光の内、あるものは再び基板lを通過し、レジス
ト3にあたり感光させる。これが必要以外の部分にピン
ホールを発生させる原因となり、歩留り低下の−因にな
っている。
When such an exposure to development process is applied to a transparent substrate to form a resist film for selective plating or etching on the transparent substrate (for example, when forming a transparent conductive film on a glass substrate) In such cases, there are the following problems. In other words, in silicon substrates and printed wiring boards, ultraviolet rays pass through the openings (transparent parts) of the mask, expose the resist, and are absorbed by the substrate, or even if they are reflected from the substrate surface, the resist is extremely thick. Thin (
(several microns), so the possibility of light hitting unnecessary areas is extremely small. However, in the case of a transparent substrate, as shown in FIG. 4, the light transmitted through the mask 6 passes through the resist 3, then also through the substrate 1, and is reflected by the stage 8 of the exposure apparatus. Some of this reflected light passes through the substrate 1 again and hits the resist 3, causing it to be exposed. This causes pinholes to occur in areas other than those required, and is a cause of a decrease in yield.

[発明の目的コ 本発明は、上記問題点を改善するためになされたもので
、その目的とするところは、透明基板を透過した光が露
光装置のステージ等で反射し、再びレジストを感光させ
ることを防止し得る露光方法を提供するにある。
[Purpose of the Invention] The present invention has been made in order to improve the above-mentioned problems, and its purpose is to prevent the light transmitted through the transparent substrate from being reflected by the stage of the exposure device, etc., and to expose the resist again. An object of the present invention is to provide an exposure method that can prevent this.

「発明の開示] 本発明は、透明基板上に形成したレジストを、レジスト
の上方に配したマスクを介して露光する工程において、
上記透明基板の下面に光吸収手段を配したことを特徴と
する。
"Disclosure of the Invention" The present invention provides a step of exposing a resist formed on a transparent substrate to light through a mask placed above the resist.
The present invention is characterized in that a light absorption means is disposed on the lower surface of the transparent substrate.

以下、本発明を実施例に基づいて説明する。第1図は本
発明の一実施例を示すもので、図中、■はガラス等の透
明基板、2は透明基板1の上に形成された透明導電膜、
3はレジストであり、これらは周知の方法により形成さ
れる。このようにして形成されたレジスト3を、レジス
ト3の上方に配した、ガラス板4上に所望のパターン5
が印刷されたマスク6を介して紫外線UVで露光する工
程において、上記透明基板1の下面に光吸収手段として
の紫外線吸収テープ7を接着し、透明基板1の下面から
紫外線が外に漏れるのを防止し、露光装置のステージ8
(第3図参照)等で乱反射するのを防止したものである
Hereinafter, the present invention will be explained based on examples. FIG. 1 shows an embodiment of the present invention. In the figure, ■ indicates a transparent substrate such as glass, 2 indicates a transparent conductive film formed on the transparent substrate 1,
3 is a resist, which is formed by a well-known method. The resist 3 thus formed is placed in a desired pattern 5 on a glass plate 4 placed above the resist 3.
In the step of exposing to ultraviolet light through a mask 6 printed with UV light, an ultraviolet absorbing tape 7 as a light absorbing means is adhered to the lower surface of the transparent substrate 1 to prevent ultraviolet light from leaking out from the lower surface of the transparent substrate 1. Prevent and stage 8 of exposure equipment
(See Figure 3) etc. to prevent diffused reflection.

ここで、紫外線吸収テープ7を透明基板1の下面に接着
時に、透明基板1とテープ7の間に気泡が入ると、その
部分で乱反射が起きるので、第2図に示すような加圧用
ローラ9を用いて、基板1面に均一な圧力を加えテープ
7を接着するのが好ましい。
If air bubbles enter between the transparent substrate 1 and the tape 7 when adhering the ultraviolet absorbing tape 7 to the lower surface of the transparent substrate 1, diffuse reflection will occur in that area, so a pressure roller 9 as shown in FIG. It is preferable to apply uniform pressure to the surface of the substrate to adhere the tape 7 using a tape.

なお、本発明は上記実施例に限定されるものでないのは
勿論であり、例えば、光吸収手段7としては、透明基板
1の下面にクロム等の光吸収用材料を形成しても同様の
効果が期待できる。
It should be noted that the present invention is of course not limited to the above-mentioned embodiments. For example, the same effect can be achieved even if a light absorbing material such as chromium is formed on the lower surface of the transparent substrate 1 as the light absorbing means 7. can be expected.

[発明の効果] 本発明は上記のように、透明基板上に形成したレジスト
を、レジストの上方に配したマスクを介して露光する工
程において、上記透明基板の下面に光吸収手段を配した
ことにより、透明基板を透過した紫外線の乱反射を防止
でき、レジスト膜のピンホールをなくすることができる
。従って、本発明を用いれば製品の歩留りを向上させる
ことができる。また、本発明によれば透明基板上にメッ
キやエツチングを選択的に行なう為のレジスト膜を形成
するような場合でも、露光装置の改良を必要とせず、シ
リコン基板やプリント配線用基板の露光装置をそのまま
用いることができる利点もある。
[Effects of the Invention] As described above, the present invention is characterized in that in the step of exposing a resist formed on a transparent substrate to light through a mask placed above the resist, a light absorption means is arranged on the lower surface of the transparent substrate. This makes it possible to prevent diffuse reflection of ultraviolet rays transmitted through the transparent substrate, and to eliminate pinholes in the resist film. Therefore, by using the present invention, the yield of products can be improved. Furthermore, according to the present invention, even when forming a resist film for selectively plating or etching on a transparent substrate, there is no need to improve the exposure equipment, and the exposure equipment for silicon substrates and printed wiring boards can be used. There is also the advantage that it can be used as is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す簡略図、第2図は本発
明に係る光吸収手段の接着状態を示す簡略斜視図、第3
図は本発明の詳細な説明する簡略図、第4図は従来例の
作用を説明する簡略図である。 I・・・透明基板、2・・・透明導電膜、3・・・レジ
スト、6・・・マスク、7・・・光吸収手段。
FIG. 1 is a simplified diagram showing one embodiment of the present invention, FIG. 2 is a simplified perspective view showing the adhesive state of the light absorbing means according to the present invention, and FIG.
The figure is a simplified diagram explaining the details of the present invention, and FIG. 4 is a simplified diagram explaining the operation of the conventional example. I...Transparent substrate, 2...Transparent conductive film, 3...Resist, 6...Mask, 7...Light absorption means.

Claims (1)

【特許請求の範囲】[Claims] (1)透明基板上に形成したレジストを、レジストの上
方に配したマスクを介して露光する工程において、上記
透明基板の下面に光吸収手段を配したことを特徴とする
レジストの露光方法。
(1) A method for exposing a resist, characterized in that, in the step of exposing a resist formed on a transparent substrate to light through a mask placed above the resist, a light absorbing means is placed on the lower surface of the transparent substrate.
JP62070996A 1987-03-25 1987-03-25 Method for exposing resist Pending JPS63236032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62070996A JPS63236032A (en) 1987-03-25 1987-03-25 Method for exposing resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62070996A JPS63236032A (en) 1987-03-25 1987-03-25 Method for exposing resist

Publications (1)

Publication Number Publication Date
JPS63236032A true JPS63236032A (en) 1988-09-30

Family

ID=13447675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62070996A Pending JPS63236032A (en) 1987-03-25 1987-03-25 Method for exposing resist

Country Status (1)

Country Link
JP (1) JPS63236032A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007041448A (en) * 2005-08-05 2007-02-15 V Technology Co Ltd Exposure device
JP2012201973A (en) * 2011-03-28 2012-10-22 Seiko Instruments Inc Electrocasting mold

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007041448A (en) * 2005-08-05 2007-02-15 V Technology Co Ltd Exposure device
JP4679999B2 (en) * 2005-08-05 2011-05-11 株式会社ブイ・テクノロジー Exposure equipment
JP2012201973A (en) * 2011-03-28 2012-10-22 Seiko Instruments Inc Electrocasting mold

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