JPS6323516A - Instantaneous interruption and open-phase detecting circuit for multiphase electric source - Google Patents
Instantaneous interruption and open-phase detecting circuit for multiphase electric sourceInfo
- Publication number
- JPS6323516A JPS6323516A JP16538586A JP16538586A JPS6323516A JP S6323516 A JPS6323516 A JP S6323516A JP 16538586 A JP16538586 A JP 16538586A JP 16538586 A JP16538586 A JP 16538586A JP S6323516 A JPS6323516 A JP S6323516A
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- Prior art keywords
- phase
- output
- circuit
- detection
- open
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000001514 detection method Methods 0.000 claims description 34
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 244000145845 chattering Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
A、産業上の利用分野
本発明は、多相電源の瞬時停電・欠相検出回路に関する
。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an instantaneous power failure/open phase detection circuit for a multiphase power supply.
B1発明の概要
本発明は、多相電源の各相電圧信号から瞬時停電又は欠
相を検出する回路において、
各相電圧信号の高利得増幅と絶対値化した波形の論理処
理によって瞬時停電又は欠相を検出することによシ、
確実、容易に検出できるようにしたものである。B1 Summary of the Invention The present invention provides a circuit that detects instantaneous power outages or phase loss from each phase voltage signal of a multiphase power supply by high-gain amplification of each phase voltage signal and logical processing of absolute value waveforms. By detecting the phase, it can be detected reliably and easily.
C0従来の技術
無停電電源装置やインバータは、3相電源を電力源とす
ることが多いが、電源が瞬間的に停電あるいは電圧降下
(以下瞬停と呼ぶ)のとき、又は電源のある相の電圧降
下(以下欠相と呼ぶ)のと。C0 Conventional technology Uninterruptible power supplies and inverters often use three-phase power as a power source, but when there is a momentary power outage or voltage drop (hereinafter referred to as an instantaneous power outage), or when one phase of the power supply voltage drop (hereinafter referred to as open phase).
きに、装置保護又はスムーズな一転継続のためにこれら
瞬停・欠相を確実に検出できることが望まれる。同様に
インバータ等の出力の欠相等を検出してその保護及び負
荷保護を行うにもこれらの検出が望まれる。In some cases, it is desirable to be able to reliably detect these instantaneous power outages and phase failures in order to protect the equipment or ensure smooth continuation of one turn. Similarly, such detection is also desired to detect phase loss in the output of an inverter, etc., and to protect it and protect the load.
8g4図は従来の瞬停・欠相検出回路を示す。3相電源
1からインバータ等の装置2に給電するにおいて、該装
置2の保護手段の1つとして3〜6からなる検出回路を
設ける。電圧検出器3は3相電源1の3相電圧を変成し
、整流回路4は3相電圧を半波整流し、この整流波形を
コンパレータ5によって停電電圧設定器6の設定値V、
と比較し、この比較出力を瞬停・欠相検出信号として装
置2の運転停止等の保護動作を得る。Figure 8g4 shows a conventional instantaneous power failure/open phase detection circuit. When power is supplied from a three-phase power supply 1 to a device 2 such as an inverter, a detection circuit consisting of 3 to 6 is provided as one of the protection means for the device 2. The voltage detector 3 transforms the three-phase voltage of the three-phase power supply 1, the rectifier circuit 4 half-wave rectifies the three-phase voltage, and the comparator 5 converts this rectified waveform into the setting value V of the power outage voltage setting device 6,
This comparative output is used as an instantaneous power failure/open phase detection signal to obtain a protective action such as stopping the operation of the device 2.
この構成によシ、第5図に示すように、整流回路4の3
相電圧■U + vv + vwのうち電圧Vvに期間
T1の電圧低下が設定値vIを越えると、コンパレータ
5の出力反転によって該期間T1の瞬停又は欠相検出に
なる。With this configuration, as shown in FIG.
When the voltage drop in the voltage Vv of the phase voltage (U + vv + vw) during the period T1 exceeds the set value vI, the output of the comparator 5 is inverted, resulting in detection of an instantaneous power outage or an open phase during the period T1.
D1発明が解決しようとする問題点
従来の検出回路において、例えば第5図に示す期間T2
で瞬停又は欠相となるとき、コンパレータ5には整流波
形の特性から瞬停・欠相検出できない。このことは他の
2相についても言えることで、瞬停・欠相を検出できな
い期間が各相について半分以上ある。D1 Problems to be Solved by the Invention In the conventional detection circuit, for example, during the period T2 shown in FIG.
When an instantaneous power outage or phase loss occurs, the comparator 5 cannot detect the instantaneous power failure or phase loss due to the characteristics of the rectified waveform. This also applies to the other two phases, and there are more than half of the periods in which instantaneous power outages and phase loss cannot be detected for each phase.
この点について、整流回路4を全波整流とすれば検出不
可期間は減少するが、それでも検出できない期間が残る
ものであった。Regarding this point, if the rectifier circuit 4 is a full-wave rectifier, the undetectable period will be reduced, but the undetectable period will still remain.
E1問題点を解決するための手段と作用本発明は、上記
問題点に鑑みてなされたもので、多相電源の各相電圧検
出出力を夫に高利得増幅と絶対値変換する各相分の波形
処理回路と、前記各波形処理回路の出力の論理和出力で
瞬時停電検出出力を得るオアゲートと、前記各波形処理
回路の出力の論理積を取シかつこの論理積出力が一定時
間以上継続するときに欠相検出出力を得る回路とを備え
、高利得増幅と絶対値化によって各和琴りロス点近辺で
のみ零点になるパルス波形を得、この論理和によって各
相共に零点になる瞬時停電を検出し、パルス波形の零点
幅が一定値を越えることで欠相検出を行う。Means and Function for Solving the E1 Problem The present invention has been made in view of the above problems, and uses high gain amplification and absolute value conversion for each phase voltage detection output of a multiphase power supply. A waveform processing circuit, an OR gate that obtains an instantaneous power failure detection output by a logical sum output of the outputs of the respective waveform processing circuits, and a logical product of the outputs of the respective waveform processing circuits, and this logical product output continues for a certain period of time or more. The circuit is equipped with a circuit that sometimes obtains an open phase detection output, and by high gain amplification and absolute value conversion, a pulse waveform that becomes a zero point only near each Wakoto loss point is obtained, and the logical sum of this produces a momentary power outage that becomes a zero point for each phase. is detected, and open phase detection is performed when the zero point width of the pulse waveform exceeds a certain value.
F、実施例 第1図は本発明の一実施例を示す回路図である。F. Example FIG. 1 is a circuit diagram showing one embodiment of the present invention.
検出対象電源からの3相検出電圧vU + vV +
vwは夫に波形処理回路11U 、 11−v 、 1
.1wの入力信号にされる。波形処理回路11U 、
llv 、 1]、wは、1.1Hに代表して示すよう
に、入力信号を高利得増幅器12Uによって増幅し、こ
の出力を絶対値回路13Uによって絶対値波形に変換し
、この変換出力を2段縦続のヒステリシス付き論理イン
バータ14U 、 15Uによって波形整形する構成に
される。Three-phase detection voltage from the power supply to be detected vU + vV +
vw has waveform processing circuits 11U, 11-v, 1
.. It is made into an input signal of 1W. Waveform processing circuit 11U,
llv, 1], w, as represented by 1.1H, the input signal is amplified by the high gain amplifier 12U, this output is converted into an absolute value waveform by the absolute value circuit 13U, and this converted output is The waveform is shaped by cascaded logical inverters 14U and 15U with hysteresis.
波形処理回路11U 、 Ilv 、 11.wの各出
力U2 * ”2 *W2は、オアゲート16の論理和
入力にされて該オアゲート16の出力に瞬停検出信号と
して取出され、またナントゲート17の論理積入力にさ
れて該ナントゲート17の出力に次段のタイマとの協動
で欠相検出信号として取出される。ナントゲート17の
出力はタイマ18の入力にされ、タイマ18はその入力
が設定時間以上継続したときに欠相検出出力を得る。オ
アゲート16の出力とタイマ18の出力はアンドゲート
19の入力にされ、このアンドゲート19での論理和動
作出力が瞬停・欠相検出出力にされる。Waveform processing circuit 11U, Ilv, 11. Each output U2 * "2 * W2 of w is input to the logical sum of the OR gate 16 and taken out as an instantaneous power failure detection signal to the output of the OR gate 16, and is input to the logical product of the Nant's gate 17. The output of the Nant gate 17 is taken out as an open phase detection signal in cooperation with the next stage timer.The output of the Nant gate 17 is input to the timer 18, and the timer 18 detects an open phase when the input continues for more than a set time. The output of the OR gate 16 and the output of the timer 18 are input to an AND gate 19, and the logical OR operation output of the AND gate 19 is used as the instantaneous power failure/phase loss detection output.
こうした構成における各部波形は第2図に示すようにな
る。3相電圧■U、vv、vwの高利得増幅と絶対値変
換により、例えば増幅器12Uの出力は飽和値まで達し
、絶対値回路13Uの出力は相電圧の零クロス点近辺で
のみ急峻に立下る波形になる。これら波形の整形によシ
、例えば論理インバータ15Uの出力は零クロス点近辺
でのみ論理゛0”になるパルスになる。このパルスの論
理60″′期間T5は非常に短かく、各相−周期に対す
る比は無視できるほどの値である。これらパルスの論理
和をオアゲート16に得ると、その出力U+V+Wは検
出対象電源が正常であれば常時論理11#となり、瞬停
時には各相電圧が零となってその瞬停期間だけ論理゛O
”になって瞬停検出出力を得ることができる。Waveforms of various parts in such a configuration are shown in FIG. By high gain amplification and absolute value conversion of the three-phase voltages U, vv, and vw, for example, the output of the amplifier 12U reaches a saturation value, and the output of the absolute value circuit 13U falls sharply only near the zero-crossing point of the phase voltage. It becomes a waveform. By shaping these waveforms, for example, the output of the logic inverter 15U becomes a pulse that becomes logic "0" only near the zero crossing point.The logic period T5 of this pulse is very short, and each phase-period is The ratio is negligible. When the OR gate 16 obtains the logical sum of these pulses, its output U+V+W will always be logic 11# if the power supply to be detected is normal, and at the time of a momentary power failure, each phase voltage will be zero and the output will be logic ``O'' only during that momentary power failure.
” and you can get the instantaneous power failure detection output.
一方、パルス出力になる信号U2.v21w2の論理積
を得るナントゲート17の出力U・■・Wは、電源が正
常であれば期間T5のパルス列信号になシ、このパルス
に対してタイマ18に期間15以上継続するパルスに対
して出力を得る設定にすることで欠相時に期間15以上
のものであればタイマ出力に論理10#になる欠相検出
出力を得ることができる。On the other hand, the signal U2 which becomes a pulse output. The outputs U, ■, and W of the Nant gate 17 that obtain the logical product of v21w2 are not pulse train signals of period T5 if the power supply is normal, and for this pulse, the timer 18 is activated for pulses that continue for a period of 15 or more. By setting to obtain the output, if the period is 15 or more when the phase is open, it is possible to obtain the open phase detection output which becomes logic 10# as the timer output.
ここで、期間T5は、前述のように非常に短かい期間の
ため、タイマ18によって期間15以上のパルスを欠相
検出とすることは高い確率で欠相検出ができる。Here, since the period T5 is a very short period as described above, if the timer 18 detects a pulse having a period of 15 or more as an open phase, it is possible to detect an open phase with a high probability.
これら検出出力からアンドゲート19は瞬停検出出力と
欠相検出出力に対して論理和動作になり、一方の検出出
力が論理”0”で瞬停・欠相検出出力を得ることができ
る。From these detection outputs, the AND gate 19 performs an OR operation for the instantaneous power failure detection output and the phase loss detection output, so that one of the detection outputs is logic "0" and an instantaneous power failure/phase loss detection output can be obtained.
また、瞬停のときはタイマ18の出力も10#出力にな
るが、オアゲート16とタイマ18の出力を夫に単独に
引出して瞬停と欠相を個別に検出し、夫にに対応する保
護動作を得ることができる。In addition, in the event of a momentary power failure, the output of the timer 18 also becomes the 10# output, but the outputs of the OR gate 16 and timer 18 are individually drawn out to the husband, and instantaneous power failure and phase loss are detected individually, and the protection corresponding to the husband is provided. You can get the action.
なお、実施例において、波形処理回路1iUHIlv
111Wに設ける高利得増幅器(例えば12U)は、そ
の利得を無限大とするコンパレータ動作にするものでは
ない。この理由は仮シにコンパレータとすると、3相電
圧vU、■v、vwの零クロス近辺でチャタリングを発
生し易くなるし、このチャタリング防止に該コンパレー
タにヒステリシス回路を設けるときには第3図に示すよ
うに瞬停時にヒステリシス動作によって該瞬停検出出力
が得られないという誤動作となる。In addition, in the embodiment, the waveform processing circuit 1iUHIlv
The high gain amplifier (for example, 12U) provided in 111W is not intended to operate as a comparator with infinite gain. The reason for this is that if a comparator is used as a temporary comparator, chattering will easily occur near the zero cross of the three-phase voltages vU, ■v, and vw, and when a hysteresis circuit is provided in the comparator to prevent this chattering, as shown in Figure 3. When a momentary power failure occurs, the hysteresis operation causes a malfunction in which the instantaneous power failure detection output cannot be obtained.
また、実施例において、電圧検出信号は装置がインバー
タ等の位相制御に電源同期させるための検出トランスを
利用して得ることができる。Further, in the embodiment, the voltage detection signal can be obtained by using a detection transformer for synchronizing the power supply with the phase control of the device such as an inverter.
G1発明の効果
以上のとおシ、本発明によれば、各相電圧信号を高利得
増幅と絶対値化した波形処理後に論理処理によって瞬停
と欠相を検出するようにしたため、零クロス点近辺のパ
ルス期間を除いて瞬停・欠相を確実にしかも個別に検出
できる効果があるし、回路構成も複雑になることはない
。In addition to the effects of the G1 invention, according to the present invention, instantaneous power outages and open phases are detected by logic processing after each phase voltage signal is subjected to high gain amplification and absolute value waveform processing. This has the effect of reliably and individually detecting instantaneous power outages and phase failures except during the pulse period, and the circuit configuration does not become complicated.
第1図は、本発明の一実施例を示す回路図、第2図は第
1図の各部波形図、第3図は実施例における増幅器に代
えてコンパレータとする場合の検出波形図、第4図は従
来の検出回路図、第5図は従来の検出波形図である。
11U 、 llv 、 Ilw・・・波形処理回路、
12U・・・高利得増幅器、13U・・・絶対値回路、
14U 、 15U・・・論理インバータ、16・・・
オアゲート、17・・・ナントゲート、18・・・タイ
マ、19・・・アンドゲート。
4ビjヨコヨ[こ
第2図
大1旨枦1の各舒波ル日
第4図
従来の検出回路図
第5図
従来の検出;皮形困FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a detection waveform diagram when a comparator is used instead of the amplifier in the embodiment, and FIG. The figure is a conventional detection circuit diagram, and FIG. 5 is a conventional detection waveform diagram. 11U, llv, Ilw... waveform processing circuit,
12U...High gain amplifier, 13U...Absolute value circuit,
14U, 15U...Logic inverter, 16...
OR gate, 17... Nante gate, 18... Timer, 19... AND gate. Figure 4 Conventional detection circuit diagram Figure 5 Conventional detection;
Claims (1)
変換する各相分の波形処理回路と、前記各波形処理回路
の出力の論理和出力で瞬時停電検出出力を得るオアゲー
トと、前記各波形処理回路の出力の論理積を取りかつこ
の論理積出力が一定時間以上継続するときに欠相検出出
力を得る回路とを備えたことを特徴とする多相電源の瞬
時停電・欠相検出回路。a waveform processing circuit for each phase that performs high gain amplification and absolute value conversion on each phase voltage detection output of the multiphase power supply; and an OR gate that obtains an instantaneous power failure detection output by a logical sum output of the outputs of the respective waveform processing circuits; Momentary power outage/phase loss of a multiphase power supply, characterized by comprising a circuit that takes the logical product of the outputs of the respective waveform processing circuits and obtains a phase loss detection output when the logical product output continues for a certain period of time or more. detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61165385A JPH0785621B2 (en) | 1986-07-14 | 1986-07-14 | Instantaneous power failure / open phase detection circuit for multi-phase power supply |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61165385A JPH0785621B2 (en) | 1986-07-14 | 1986-07-14 | Instantaneous power failure / open phase detection circuit for multi-phase power supply |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6323516A true JPS6323516A (en) | 1988-01-30 |
JPH0785621B2 JPH0785621B2 (en) | 1995-09-13 |
Family
ID=15811382
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61165385A Expired - Fee Related JPH0785621B2 (en) | 1986-07-14 | 1986-07-14 | Instantaneous power failure / open phase detection circuit for multi-phase power supply |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0785621B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5265836U (en) * | 1975-11-12 | 1977-05-16 | ||
JPS5385360A (en) * | 1976-12-30 | 1978-07-27 | Hokushin Electric Works | 33phase power supply fault detector |
JPS5610021A (en) * | 1979-06-30 | 1981-02-02 | Omron Tateisi Electronics Co | Failure phase detector |
-
1986
- 1986-07-14 JP JP61165385A patent/JPH0785621B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5265836U (en) * | 1975-11-12 | 1977-05-16 | ||
JPS5385360A (en) * | 1976-12-30 | 1978-07-27 | Hokushin Electric Works | 33phase power supply fault detector |
JPS5610021A (en) * | 1979-06-30 | 1981-02-02 | Omron Tateisi Electronics Co | Failure phase detector |
Also Published As
Publication number | Publication date |
---|---|
JPH0785621B2 (en) | 1995-09-13 |
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