JPS58221452A - Computer device for parallel processing - Google Patents

Abstract

PURPOSE:To detect the generation of an accident precisely by taking out output signals from corresponding circuits respectively during no calculation period of computers, differentiating these signals, uniforming their polarity and then discriminating coincidence or inconsistency between these signals and an inverted clock pulse. CONSTITUTION:Output signals are taken out from main circuits ak, bk constituting the computers in A and B systems respectively during no calculation period. These output signals are differentiated by differential circuits 21, 22, their polarity is uniformed by polarity coincidence circuits 23, 24 and the outputs of the circuits 23, 24 are inputted to AND circuits 25, 26. Clock pulses CL are supplied to the inverted input terminals of the AND circuits 25, 26, so that the coincidence or inconsistency of both inputs is discriminated and the generation of an accident of the circuit in each system.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention performs the same processing in parallel and synchronous operation on two systems of computers with the same configuration, and also compares the calculation results to ensure high reliability of the processing. The present invention relates to a parallel processing computer device that is maintained, and in particular, to a device that can prevent accidents caused by changes in the calculation results of both limiters due to the penetration of radiation.
[Technical background of the invention and its problems] Figure 1 shows a well-known parallel processing computer device.
11 and 1:l are A-system and B-system computers, respectively, which have the same configuration. These computers 11 and 13 are operated in antiparallel synchronization with clock pulses and perform the same processing.

Also, '1+h...Ak...1n and bLtbm
...bk...bn are each computer 11, 1:l
This is the main circuit that makes up the Output signals of these same circuits AI+A3...Ak...tags and Bl, B,...
・Bk...Bn are respective comparison circuits c1tC
2...ck...Cn, and this comparison circuit c
1. The υ Tozan force signal is compared with c, ...ck...Cn. The result of this comparison is AI “Bl t
A, =13. ...Ak=Bk...A, =Bn, if they are all equal, it is determined that the two-hand counter 11.12 is operating normally, and AI = 131 t
Am = 131...AkNBk...tag = courtesy If even one of these sets of output signals does not match, it is determined that an accident has occurred, and, for example, a repair command is immediately issued and recalculation is performed. Otherwise, the calculation result will be replaced with the value before the accident.

By the way, in the above configuration, if radiation such as cosmic rays penetrates one of the corresponding circuits operating in parallel and the state of the fritsunofrog circuit consisting of semiconductor elements constituting the circuit is reversed, both of the circuits in the comparison circuit Since the output signals of the circuits are different, it can be determined that an accident has occurred. However, this comparison circuit cannot determine which of the A and B systems an accident has occurred in. Therefore, as mentioned above, it is necessary to recalculate using values before the accident, which reduces the efficiency of calculation processing.

[Purpose of the invention]

This invention was made based on the above circumstances, and its purpose is to be able to detect which of the two systems of computers has experienced an accident, and to detect the output signal of the normal system. The object of the present invention is to provide a parallel processing computer device that can be used to perform efficient calculation processing.

[Summary of the invention]

This invention extracts the output signals of the circuit corresponding to the non-calculation periods of the computer, differentiates these signals, aligns the polarities, and determines whether the signals match or do not match the inverted clock pulse. This detects which circuit system an accident has occurred in.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals. FIG. 2 shows the main part of the present invention. For example, when controlling the attitude of aerospace equipment using this type of parallel processing computer device, the attitude control of aerospace equipment is performed once every second or once every 10 seconds. Intermittent control such as once is performed. Since computers that perform such processing have longer non-calculation periods than calculation periods, most radiation penetration accidents occur during non-calculation periods. Therefore, the occurrence of an accident can be detected by determining the output signal of each main circuit during the non-calculation period. Further, the accident occurs as a result of the reversal of the 7-rig frog circuit, which is made up of semiconductor elements constituting each main circuit.

In FIG. 2, a signal different from the signal Ak t Bk supplied to the comparator circuit Ck from the main circuits □ and bk constituting the computers 11 and 12 of the A system and B system is used for calculation periods and non-calculation periods. are taken out respectively. Since the main circuit 11 has the same configuration as @bk, only the configuration of &□ will be explained.

In FIG. 3, an AND circuit 31 is provided in the main circuit 1, and this AND circuit 31 includes an output signal tag such as a F'Jy7' frog circuit (not shown) and an output signal tag (not shown) in FIG.
, ) is supplied, and the signal tag is output in response to the calculation period T1 of this clock/clock CL.

Further, an AND circuit 3'2 constituting a first simultaneous circuit is provided within the main circuit Ak. This AND circuit 32
The signal Ak is supplied to the non-inverting input terminal of , and the clock pulse CL is supplied to the inverting input terminal. Therefore, the AND circuit 32 outputs the inverted clock pulse OL shown in FIG. 4(b), that is, the signal corresponding to the non-calculation period Tna of the clock pulse CL shown in FIG. 4(IL). Here, during the non-calculation period, for example, radiation penetrates the main circuit ζ, and the output signal Ak of the graph frog circuit becomes the fourth one.
Assume that the signal Ak is inverted from the ``'0# level to the @12 level as shown in FIG. Further, since the output signal of the Fritznow frog circuit in the main circuit bk remains at the 10'' level, the output signal Bk of the main synchronizing path bk is at the ``0'' level. Therefore, since the comparator circuit Ck determines that AkNBk, an accident can be detected.

On the other hand, the signal Sk output from the AND circuit 32 of the main circuit during the non-calculation period is as shown in FIG. #level. These signals are connected to differentiating circuits 21.2 and 21.2 shown in FIG.
2 and is differentiated and waveform shaped. Among these, the output signal of the differential circuit 22 is at the 10# level. The output signals of these differentiating circuits 21 and 22 are respectively supplied to polarity matching (absolute value) circuits 23 and 24. Each of these polarity-number circuits 23 and 24 is an inverter circuit 23A.
, amplifier with a gain of 1, 2Jb, diode 23a
, 23d, and an OR circuit 23. Here, one of the polarity-number circuits 23 to which the output signal of the differentiation circuit 21 is supplied will be explained. The output signal of the differentiating circuit 21 is branched and supplied to an inverter circuit 23 and an amplifier 23b, respectively. The output signals of the inverter circuit 23a and the amplifier 23b are as shown in FIGS. 4(g) and 4(h), and the negative side of these signals is removed by the diodes 23a and 23d. These signals are each supplied to an OR circuit 23, and this OR circuit 23
As shown in FIG. 4 (1), only the positive side signal 1''1 is output from . On the other hand, the t polarity-number circuit 24 outputs a ``''0#0# level signal. The output signals of these polarity-number circuits 23 and 24 are respectively supplied to non-inverting input terminals of AND circuits 25 and 26 constituting the second simultaneous circuit. A clock signal CL is supplied to the inverting input terminals of the AND circuits 25 and 26, respectively, and the output signal of the polarity-number circuit 23 is inverted from the AND circuit 25 as shown in FIG. A signal Dk(=CLIS+)t corresponding to the clock signal τ is extracted. Further, the AND circuit 26 outputs a @0'' level signal.The difference in this output signal Dk indicates that an accident has occurred in the main circuit.

With the above configuration, the output signal of the main circuit is extracted during the non-calculation period of the main circuit, and this signal is combined with the inverted clock signal 4.
If a matching signal is obtained as shown in Figure 4 (j), it is determined that an accident has occurred in the main circuit of the system from which the signal was obtained. . Therefore, it is possible to detect whether an accident has occurred in the collapsed system, and when the operation of the abnormal system is stopped, an accident can be displayed on this system and processing can be continued using the output signal of the normal system. , processing efficiency can be improved compared to the conventional case where recalculation is performed.

However, in the conventional configuration, if radiation penetrates the corresponding main circuits of both systems at the same time and the output signals are similarly inverted, the comparator circuit cannot detect an accident because the two systems are the same.

However, according to the present invention, when the output signals of both systems are inverted, the output signals of the AND circuits 26 and 26 are both @1#
◎ In the above example, the main circuit extracted during the non-calculation period is
Although the output signals of klbk are shown as one each, 'kl
A configuration may also be adopted in which a plurality of AND circuits 32 are provided in bk to extract a large number of signals. In this case, it goes without saying that a differentiating circuit and a polarity-number circuit are required for each output signal.Also, to avoid flip-flow and instability of the circuit due to radiation penetration during the calculation period, the input signal is By making the size sufficiently large, accidents can be prevented. [Effects of the Invention] As detailed above, according to this invention, accidents can occur in either system of Ft'l' calculation of the two systems of computers. It is possible to provide a parallel processing computer device that can detect whether a problem has occurred and can perform efficient calculation processing using the output signal of a normal system.

FIG. 3 is a diagram showing the configuration of the main circuit ak in FIG. 2, and FIGS. 4(A) to (j) are diagrams shown to explain the operation of FIG. 2.

11.12...A system, B system computer, le 1~an,
bl~bn... Main circuit, 21.22... Differential circuit, 23.24... Polarity matching circuit, 25.26... AND circuit.

Applicant's agent: Patent attorney Takehiko Suzue Figure 1 1 n 2 Figure 2 1 Figure 3 k Figure 4 a j)-m-”-111

Claims (1)

[Scope of Claims] A parallel system in which two systems of computers with the same configuration are operated in anti-parallel synchronization using clock pulses to perform the same processing, and detect accidents by comparing required output signals of these two systems of computers. In the processing computer device, a means for opening a gate during a non-calculation period when an inverted signal of the clock pulse is supplied to take out required output signals of the two-hand counter, and a circuit for differentiating the extracted signals. Means for aligning the polarities of the differentiated signals, the signals of both systems with the aligned polarities, and the inverted signal of the clock pulse are supplied to detect inversions of the output signals of the two hand counters during the non-calculation period. A parallel processing computer device characterized by comprising a non-simultaneous circuit.