JPS63231791A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten an operation time and to reduce the area of a chip by guiding a memory signal which is led out of a memory cell to a data line to a differential amplifier without being passed through a switching circuit by an MOSFET. CONSTITUTION:The input buffer circuit 121 of a memory device shapes the waveform of an input address and guides the result to a decoder circuit 117 and when a word line is at a high level, the signal of a memory cell A1 is read out to a couple of data lines 113 and 114 by MOSFETs 119 and 120. The potentials of those data lines 113 and 114 are shifted in level by bipolar transistors TrQ1 and TrQ2 which are fed electrically by MOSFETs 107 and 108 and then guided to the differential amplifier composed of a feeding MOSFET 109 and Trs Q3 and Q4. The color selection signal Vy of a decoder 118 is transmitted to the common collector lines CC and the inverse of CC of the Trs Q3 and Q4 as current signals only when said signal is at a high level and then amplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device that is designed to stabilize operation and improve reliability by speeding up circuit operation and improving latch-up resistance. It is related to the device.

[Conventional technology]

In recent years, memories that operate at high speed and consume less power have been developed by combining MoS transistors and bipolar transistors.

FIG. 6 is a block diagram of a memory combining MOS transistors and bipolar transistors. Such memories have a function of reading and rewriting information in memory cells in response to input signals.

That is, as shown in FIG. 6, an input signal is amplified by an input buffer circuit, this is decoded by a decoder circuit, one of the word lines is selected, and a Y switch is operated by a drive circuit (not shown). , select one of the data lines. Thereby, information is read from one memory cell, the read information is amplified by the sense amplifier via the data line and the common data line pair, and is output to the data output terminal via the output buffer circuit. Looking at the access time, which represents the speed of conventional memory with this configuration,
The input cover sofa circuit, decoder circuit, and sense/output cover sofa circuit each account for approximately 1/3 of the delay time, and in order to increase the speed, it is necessary to shorten the delay time of each circuit. Further, in order to stabilize the operation, the chip size of the memory LSI should be kept in mind when making improvements, and it goes without saying that it is desirable to suppress the increase in the chip size. As a guideline, when looking at the proportion of memory area occupied by each circuit, memory cells account for over 70%, and if this memory cell area did not increase, the increase in the area occupied by other circuits would mostly be due to the chip size. It can also be seen that there is no contribution.

Incidentally, the recent trend toward higher speeds and higher functionality of electronic devices is no exception in the case of memory LSIs, and even higher speeds, higher integration, and lower power consumption are desired.

An example of a related patent is Japanese Patent Application No. 1982-239244, which was previously proposed by the present inventors.

[Problem that the invention seeks to solve]

Conventional semiconductor memory devices have the following circuit characteristics, which limits their ability to increase speed.

In a memory designed with a minimum processing size of 2-, the access time is about 12 ns.

(a) A MOS type current mirror circuit is used for the input buffer circuit, (b) A sequential decoding circuit is used for the decoder circuit, (c) M is used for the data line load element.
(d) The read data is collected from the data line to the common data line and then sent to the sense amplifier.

Due to the delay time of these circuits, it has been difficult to further improve the high-speed operation of memory using conventional circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device which can reduce the delay time of such a conventional circuit, can operate at high speed and stably, and can have a small chip area.

[Means for solving problems]

In order to achieve the above object, the present invention provides a memory using an input buffer circuit that shifts the input signal level, a decoder circuit that decodes the output signal of the input buffer circuit, and a MOSFET in which only the decoded address is selected. A semiconductor memory device comprising a cell, a data line load circuit connected to the memory cell, a sense circuit that amplifies a signal read from the memory cell, and an output buffer circuit that outputs the output of the sense circuit to the outside. , the memory signal taken out from the memory cell to the data line is M
A feature of the memory signal is that it is led to a bipolar differential amplifier without going through a switching circuit using an OSFET, and its collectors are connected in parallel to further collect the memory signal.

[Effect]

In the present invention, (a) a combination circuit of bipolar transistors and MoS transistors that operates only when the input signal of the input buffer circuit is switched is used; therefore, a large driving capacity is exhibited only when the signal is switched, and the delay time is shortened; At the same time, in a steady state other than when signals are switched, no power is consumed and power reduction can be achieved at the same time.

(b) Since a collective decoding circuit in which MOSFETs are connected in series is used in the decoder circuit, the decoder circuit can be simplified and the number of logic stages can be reduced.

As a result, the time required for decoding is also shortened.

Furthermore, since the address signal paths are equivalent in all cases, variations in decoding time are reduced, and effective decoding time can also be shortened.

(c) By using an N-type MOSFET as the data line load element and optimizing its supply potential and threshold voltage, a faster data line response speed can be obtained compared to when using conventional MOS transistors. .

(d) Connecting the sense amplifier directly to the data line eliminates the delay time of the common data line.

As described above, by improving each circuit, the delay time in each circuit can be shortened and memory operation can be made faster. It has also been confirmed that this circuit makes memory operation more stable.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, improvements in each circuit in the semiconductor memory device of the present invention will be briefly listed.

(a) The input buffer circuit uses a combination circuit of bipolar transistors and MOS transistors that exhibits large driving capacity only when the input signal is switched.
In addition, a circuit provided with a steady-state current suppression circuit is used. (B)
As a decoder circuit, a batch decoding circuit in which MOSFETs are connected in series is used. (c) Use an N-channel MOSFET as the data line load element, and its supply potential and MOSFET
Aim to optimize the threshold voltage of SFET. (d) By directly connecting the sense amplifier to the data line, the common data line is omitted and its delay is eliminated. Hereinafter, a specific circuit obtained by such an improvement will be described in detail. In addition,
Regarding the decoder circuit, the "semiconductor memory device" previously proposed by the present inventors (Japanese Patent Application No. 61-297030
(Refer to the explanation of FIG. 2 in the specification of the above specification), so the explanation will be omitted in this embodiment.

FIG. 1 is a basic configuration diagram of a data line load and a sense circuit section of a semiconductor memory device showing one embodiment of the present invention.

This shows a data signal detection circuit (sense circuit), which is important for increasing the speed of semiconductor memory, and a data line load circuit required to operate the circuit.

The operation of this circuit will be briefly explained. Address input signal 1
20 is waveform-shaped by the input buffer circuit 121 and then guided to the decoder circuit 117, and when the word line WL is raised to a high level, the signal of the memory cell A1 becomes M
Data line pair 113,
114. The potential of the data line at this time is
High level is the supply potential V□, and low level is MOSF
The potential is lower than the supply potential v1 by the voltage drop due to the effective resistance of ET103, 104, 101, 102, and 105 and the current of memory cell A1. Although the current shunting by MOSFET 105 is omitted, its inclusion lowers the high level of the data line and raises the low level, thereby reducing the signal amplitude applied to the data line pair. The potential of these data lines is MOSFETLO7,10
Bipolar transistor Q□t powered by 8
After the level is shifted by Q2, the power supply MOS
Common collector line CC2σ is led to a differential amplifier consisting of FET109° bipolar transistors Q, Q4.
It is then transmitted as a current signal. Here, V, / are column selection signals generated by the decoder 118, and only when VV is high level, the data line signals Q3. Q.

It is then transmitted to cc and cc. The amplification of the signal transmitted to the common collector line will be explained in detail later with reference to FIG. 2, but for this signal amplification, it is desirable that the potential of the common collector line is 1.5 V or more lower than the ground potential. Therefore, even if the amount of level shift due to Q, , Q2 is considered, V□ is set to be 0.5 V or more lower than the ground potential.

On the other hand, if vl is set too low, information in the memory cell AI etc. is likely to be destroyed, so it is desirable that the value be close to the maximum allowable value. Furthermore, in order to improve the data read speed, it is desirable that the amplitude of the signal applied to the data line pair is small;
, Q, etc. The highest speed and stable operation were achieved by setting the offset voltage of the differential amplifier to 2 to 5 times, which is determined from the variation in the forward voltage of the base.

By operating the circuit shown in this figure under the above conditions, the time from when the word line is selected and raised to a high level until the data in the memory cell is read, that is, the data output terminal shown in FIG.

The time it takes for data to be read is 3 times longer than that of conventional circuits.
, 5 ns, it was shortened to 1,8 ns, which is about 1/2.

Next, the operation of writing data to a memory cell, which is an essential function for memory operation, will be explained.

Data line 113 is used to write data to memory cell A1.
This is done by lowering the potential of V66 to near the power supply potential V66. For this reason, during writing, the MO
5FETs 101, 102, 105 are made non-conductive, 111°112 are made conductive by the decoder 118, and D
□Or by lowering the voltage to the power supply potential.

Here, the gates I- of the MOSFETs 103 and 104 are connected to the power supply potential V and are always kept conductive to prevent a voltage drop on unselected data lines. This writing operation is MO
By optimizing SFET III and 112 at the time of design, it is possible to write at a sufficiently high speed.

After writing data, it is necessary to quickly raise the potential of the data line to vl before the next read cycle, but the recovery time of the data line at this time is
It is determined by the effective resistances of lines 01, 103, and 105 and the capacitance of the data line 113.

This situation is shown in FIG. 5 as a change in each terminal over time.

From this result, it can be seen that the time required for the data line 113 to recover after the write signals WE and D reach 12V is approximately 1.5 ns. Such a fast recovery characteristic is based on the fact that the N-type MOSFETIO I, 1.02°105 exhibits a large conductance when the data line is at a low potential, and is a characteristic suitable for high-speed memory circuits.

Also, looking at the power consumption of this circuit, Q l l Q
21Q3. Q has a circuit configuration in which current flows only when selected by the decoder 118, and among the memory circuits, current flows only in one set of circuits B1 selected for data reading, and B2 Since almost no current flows through the circuit, it can be seen that it is a low power consumption circuit.

If the circuit shown in FIG. 1 is used in a highly integrated memory LSI, the number of bipolar transistors connected to the common collector line will increase, increasing capacitance and causing problems in high-speed operation. A high-speed multiplexer circuit that divides the common collector line, reduces the capacitance of each common collector line, and extracts only the desired data signal from the divided common collector line signals at high speed is required. will be explained in detail later using FIG. The characteristics of the memory circuit shown in FIG. 1 will be explained below in comparison with a conventional circuit. The fact that the response speed of the data lines becomes faster when the potential difference between the data line pair is reduced is described, for example, in Figure 6 and its explanation in 1984 Proceedings of the International Society for Solid State Devices, page 697. Although omitted here, as the potential difference between the data line pair is reduced, the response speed of the data line also increases in proportion to this. However, in the conventional circuit, for example, as shown in FIG. 1 of Japanese Patent Application No. 59-239244, the MOS transistor 16.6
The potential of a predetermined pair of data lines is guided to a common data line by the Y switch 6, and a signal is sent to a sense amplifier, and the signal is amplified by the sense amplifier and taken out. In this case, the capacitance of the common data line becomes approximately the same value as the capacitance of the data line, resulting in a delay time, which hinders high-speed operation. Therefore, to further improve the response speed of the common data line,
It is necessary to reduce this capacitance. A semiconductor memory device meeting this purpose has been previously proposed by the present inventors (see Japanese Patent Application No. 61-297030). In this memory device, the number of data line pairs connected to the common data line has been reduced to about 1/4, whereas conventionally a pair of common data lines were provided from the 32nd to 64th memory cell rows, and 4 pairs of data lines are connected to the common data line. By arranging the common data lines to lead to their respective sense amplifiers, we have adopted a method that reduces the capacitance of each common data line to about 1/3 and shortens the delay time of the common data lines to about 1/3. (See Figure 10 of the above specification). This embodiment can also be said to be a circuit that further advances this. That is, by directly connecting a sense amplifier to each data line, the common data line is omitted and the delay time is shortened accordingly.

FIG. 2 is a configuration diagram of a multiplexer circuit showing one embodiment of the present invention. This circuit performs an operation of quickly summarizing the outputs of the sense amplifiers provided on each data line. In FIG. 2, Q71Q, , Qg, Q□0. Q1□
, Q15 is a bipolar transistor, 205 to 210
is a resistor, and constitutes a circuit that supplies a constant current by supplying a predetermined voltage to the terminals 220 and 221. Each current is Q 71 Q Il+ Q 91
Q x 1 + Q12 is about 1mA, Q10 is 5
Although about mA was suitable for obtaining high-speed performance, it is also possible to reduce these currents to about 100 μA in order to reduce power consumption. The operation of this circuit will be explained below.

The process up to where the data line signal is transmitted to the common collector lines cc and cc has been explained with reference to FIG. The signal current flowing through this CC9 is caused by the potential difference between the data line pair.
This is the value obtained by dividing the current supplied from the ET109. This current flows through bipolar transistor Q5. Q, through MOSFET201, resistor 203 and MOSFET2
02. Flowing through the resistor 204, the collector potentials of Q, . Here, the diodes placed in parallel with the resistors 203 and 205 are Q
9. This is for clamping the collector potential of Q6. The transmitted signal is passed through the bipolar transistor Q
, r Q 1o, bipolar transistors Q, 3. The waveform is shaped by a Q□4 differential amplifier and output through Qts.

Next, the operation of MO5FETs 201 and 202 will be explained. Here, if the potential of the terminal 230 is the power supply potential VE□, then Q
5. The collector potential of Q is MOSFET201, 202
The effective resistance and the resistors 203 and 204 are connected in parallel to reduce the voltage drop. When the terminals 230, 231 reach the ground potential, the MOSFETs 201, 202 are cut off, leaving only the resistors 203, 204, and the voltage drop increases. Circuit C
Circuits similar to those shown in 1 are arranged in parallel, and C2...
- Shown closed. For example, in circuit C1, MOSFE
If the gate potential of T is set to the power supply potential V, and all gate potentials of C2 are set to the ground potential, the voltage drop across the resistors 203 and 204 in the circuit C1 will be smaller than the voltage drop across the resistors in other circuits. For this reason, the transistor Q, ,
Since the base potential of Qlo is higher than the potential of the same terminal of circuit C2..., the potential of signal lines 335 and 336 is Q9+.
It changes depending on the signal from Qxo. That is, circuit C
It can be seen that the signal transmitted to 1 is guided to the output terminal D○.

If this circuit is used, a multiplexer circuit that extracts a predetermined signal from the circuits C1, C2, . . . by controlling the gate potential of the MOSFET can be obtained. By using this circuit, it was possible to reduce the increase in delay time caused by the multiplexer circuit that collects signals to 0.5 ns or less. Although FIG. 2 describes a circuit in which MOSFETs 201 and 202 are arranged in parallel with a resistor, it is also possible to install a circuit similar to circuit C1 between the output of circuit C1 and an output buffer to form a multiplexer circuit. Needless to say. In this case, the delay time increases slightly compared to the circuit shown in FIG. 2, but the power consumption decreases.

FIG. 3 shows a conceptual diagram of a circuit configuration of a highly integrated memory LSI of 256 bytes or more.

An X decoder circuit and a driver circuit for the parent word line MWL are provided in the center. A word line WL is selected by signals from the parent word line MWL and the word line selection signal line. Here, A4 is the data line load circuit shown in FIG. 1, B4 is the array of memory cells A1, C4 is a write circuit, and the sense circuit is shown as an amplifier. D4 represents these circuits collectively, indicating that two or more of them are arranged in parallel within the LSI. For simplicity, the multiplexer circuit is represented as an amplifier, a bipolar transistor, and a constant current source.
The signals to the gate terminals of MOSFETs 201 and 202 in FIG. 2 are shown as sense amplifier selection signals. If you configure it as shown in Figure 3, B4 will have 256 columns x 32
A row memory array is provided, 16 circuits D4 are installed on the left and right, and a multiplexer circuit selects an output signal from the 16 signals, thereby outputting desired data to the output terminal Do. With this configuration, the access time of the 256 kb memory LSI is increased by approximately 1.5 ns compared to a memory using a conventional common data line.

Next, the arrangement of circuits, signal lines, etc. in FIG. 3 will be explained.

First, a signal for a parent word line is placed on a memory cell in parallel with the word line. Here, one signal line is provided for every two word lines, so that on the memory cell column through which this signal line does not pass, there is a power supply wiring, a grounding line, an input signal line, and an output line. It is characterized by the ability to pass signal lines, etc. Furthermore, when the load on the parent word line becomes too large due to the selection of two word lines, it is also effective to provide a driver circuit between the parent word lines. When this driver circuit is provided, it is also possible to further reduce the number of parent word lines. In this way, a word line selection signal can be created by providing one stage of decoding circuit for each memory cell array, and the peripheral part of the memory LSI chip, which was conventionally used for power supply wiring and signal lines, can be created. It has been confirmed that it can be used for other purposes or deleted, and that by arranging power supply wiring and grounding wiring in a mesh pattern over memory cells, it is possible to reduce the voltage drop caused by wiring, which was a problem in the past. It was done.

FIG. 4 is a block diagram of a high-speed input buffer circuit of a semiconductor memory device showing one embodiment of the present invention.

The operation will be explained along the flow of signals from the input terminal.

The signal input to the input terminal IN is level-shifted by the bipolar transistor Q3□ supplied by the MOSFET 301, and then guided to the base of the bipolar transistor Q33 of the current switch circuit, and is shifted to the MOSFET 302 by the potential difference with the constant potential VBB. The current supplied from Q33 to Q34 is distributed. The input signal is amplified to about 2V by this current switch circuit. At this time, if the amplified voltage becomes too large,
If the voltage at the input terminal rises above -0.5V,
Bipolar transistor Q3 of current switch circuit
3 saturates, sometimes causing a latch-up phenomenon and disabling memory operation. To prevent this, bipolar transistor Q3□ is connected. Here, bipolar transistor Q3□
A multi-emitter type bipolar transistor Q3 whose base terminal is common to the base and collector of the input terminal.
Although the case where the transistor is connected to the emitter terminal of 1 is shown, it goes without saying that a normal bipolar transistor structure may be used, or an independent bipolar transistor may be used to make the connection. . However, especially when the base of transistor Q32 is connected to the emitter of transistor Q31 as shown in this embodiment,
Even if the output signal amplitude of the current switch exceeds 2V, the bipolar transistor Q33 depends on the input signal voltage.
The collector potential is not clamped, making it suitable for obtaining a large output amplitude. However, increasing the signal amplitude too much increases the delay time of the current switch circuit. For this reason, an output amplitude of about 1.8 V for this circuit was most suitable from the viewpoint of speed. By adding this bipolar transistor Q32, even when the input signal voltage rises above the standard value or the output amplitude of the current switch circuit becomes large, saturation of the transistor Q33 is prevented and stable operation of the circuit is obtained. Ta. Here, a constant current source or a resistor may be connected between the emitter of the bipolar transistor Q3□ and the negative power supply. The positive and negative signals amplified by the current switch circuit are M○
Lead to an emitter follower circuit with an S transistor as a load resistance. This emitter follower circuit.

This is provided to lighten the load on the current switch circuit and drive the subsequent circuit with high driving ability. Here, applying a constant potential to the gates of MO3FETs 303 and 304 and using them as constant current sources is because the output amplitude of the emitter follower circuit is as large as approximately 2V, so the output amplitude is lower than when a pure resistor is used as a load. This is based on the fact that it consumes less power, can operate at high speed, and occupies a smaller area than a circuit that uses a bipolar transistor and a resistor in a constant current circuit. The negative signal output of the emitter follower circuit is led to the gates of MOSFETs 312 and 317, and the positive signal output is led to the gates of MOSFETs 311 and 318, and the signal amplitude is amplified to the power supply voltage by this booster circuit. At this time, a flip-flop circuit (7) MO5FETs 305, 306 (7) gates 2, which are separately provided with positive and negative signals, is also guided to produce a signal with a high-speed rising waveform.

Also, the signals at the output terminals 340 and 341 of this circuit are
A delayed signal is also generated by an inverter composed of SFETs 327, 328, 329, and 330. In this circuit, for example, the current flowing through MOSFETs 313 and 315 is the MOSFET supplied from the flip-flop circuit.
MO5FET31 supplied from an inverter composed of the gate potential of 313 and MOSFETs 329 and 330.
This is only when the gate potential of No. 5 is at a high level. That is, in a steady state, it is non-conducting. During the transient, both MOSFs
It is conductive only while the gate potential of ET is at a high level, and serves to lower the base potential of bipolar transistor Q41. MOSFET319.321,314,316
, 320, and 322 perform similar operations.

In this way, MOSFET311, 312.31
The current path of 7,318 is conductive only when the input signal changes, and as the steady state is approached, the current path is no longer conductive and no current flows through the bipolar transistor. However, in order to operate the circuit stably, MOSFET313,3
A resistor or MOSFET may be provided in parallel with 15 to allow a slight steady current to flow. That is, it can be seen that this circuit exhibits driving ability only when the output switches from high level to low level or from low level to high level, and has no driving ability at other times. Also, this circuit is
It operates with low power consumption and consumes no power except when switching signals. MOSFE attached after this circuit
T325 and T326 are circuits provided in order to provide this circuit with driving ability and stabilize the output potential except when the signal is switched. The gate terminals of MOSFETs 325 and 326 use signals from the circuit described above, in which the positive and negative input signals are switched.

Therefore, the signal to the gate of this MOSFET arrives after the switching of this circuit, so the signal to the gate of this MOSFET is
If the drive capability of the FET is large, the delay time may increase. Normally, it is desirable that the ratio of their driving capacities be 10:1 or more. When this circuit is designed using the same standards as the conventional circuit, the delay time is 2 ns, which is about 1 ns compared to the conventional circuit.
ns shortened.

In FIG. 4, the output of the flip-flop circuit and the output terminal 341 are connected to a circuit in which MOSFETs 313 and 315 are connected in series.
However, the circuit is not limited to this circuit, and may be a circuit that lowers the base potential of a desired bipolar transistor or the gate potential of a MOSFET only during a transition. Ba,
It goes without saying that the object of the present invention can be achieved.

By using the input buffer circuit, data line load circuit, and sense circuit configured as described above, the time required to read memory information (access time) is reduced to 7 ns, which is 2/3 of the delay time of 12 ns of the conventional circuit. The time required for recovery after writing can be shortened to 172 seconds.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to further reduce the delay time of the conventional circuit, and to realize a memory LSI that operates stably at high speed and has a small chip area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the data line load and sense circuit section of a memory LSI according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a multiplexer circuit section according to an embodiment of the present invention. Figure 3 is a schematic diagram of the configuration of a highly integrated LSI.
FIG. 5 is a diagram showing the configuration of an input buffer circuit according to an embodiment of the present invention, FIG. 5 is a diagram showing how data line potential is recovered after information is written, and FIG. 6 is a block diagram showing the basic configuration of a memory LSI. . 111.112, 119, 120: MOSFET, 11
3.114: Data line pair, Q, , Q2: Bipolar transistor, cc, cc: Common collector line, A1:
Memory cell, Q5-Q□5: Bipolar transistor, 201, 202: MOSFET, 203-210: Resistor, Q3□-Q34: Bipolar transistor, 30
1 to 306: MOSFET, 340.341: Output terminal.

Claims (1)

[Claims] 1. An input buffer circuit that shifts an input signal level;
A decoder circuit that decodes the output signal of the input buffer circuit, and an MO in which only the decoded address is selected.
A memory cell using SFET, a data line load circuit connected to the memory cell, a sense circuit that amplifies the signal read from the memory cell, and an output buffer circuit that outputs the output of the sense circuit to the outside. In a semiconductor memory device, a memory signal taken out from the memory cell to a data line is guided to a bipolar differential amplifier without passing through a switching circuit using a MOSFET, and the collectors of the amplifier are connected in parallel to further consolidate the memory signal. What is claimed is: 1. A semiconductor memory device characterized in that: 2. In the semiconductor memory device according to claim 1, an element of the data line load circuit includes an N-channel MOSFET.
SFET is used, and its drain has (gate voltage -
A semiconductor memory device characterized by supplying a potential lower than a threshold voltage.