JPS63228854A - Communication controller for id system - Google Patents

Abstract

PURPOSE:To always carry out communication despite arrival of any data carrier by outputting a special initial signal via each data carrier and demodulating the carrier signal to produce a synchronizing clock signal in response to the transmitting speed for execution of the subsequent communication tasks at the ID controller side. CONSTITUTION:A data carrier 40 receives the electric power from an ID controller 20 and outputs an initial signal which is modulated by a code having an 1:1 ON/OFF ratio. The controller 20 receives said modulated signal to demodulate it and divides this demodulated signal to output a demodulated signal having a double cycle via a decoding circuit. The counter of the controller 20 is replaced with reception of a pulse signal of a fixed frequency. Furthermore a synchronizing clock signal is outputted from a synchronizing clock signal generating circuit 26 in response to the contents of replacement of the counter. The controller 20 carries on the subsequent communication tasks by said synchronizing clock signal. Thus the proper communication is carried out with the data carriers regardless of their transmitting speeds.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field This invention provides an ID (
(identification) system communication control device.

(B) Conventional technology In recent years, for example, as an ID system for identifying the type of articles or tools transferred on a conveyor, an element called a data carrier containing a memory is attached to the article or tool. A system in which specific data is written into the memory from the controller, or vice versa, is being considered. In this type of ID system, many data carriers arrive and read/write data to one ID controller depending on the system aspect, but communication between the ID controller and data carriers is carried out in the same transmission. It is based on the premise that different transmission speeds are used, and to date, there has been no proposal that allows communication with multiple data carriers having different transmission speeds using the same controller.

(c) Problems to be Solved by the Invention As mentioned above, there is no system yet that allows communication between a plurality of data carriers having different transmission speeds using the same controller. However, as ID systems become more popular, it is inevitable that various types of data carriers, that is, data carriers with different transmission speeds, will appear on the market. There is an urgent need to provide a communication control method that allows communication with the same controller regardless of the data carrier having any transmission speed without being subject to any restrictions.

In view of the above, an object of the present invention is to provide an ID system that allows various data carriers with different transmission speeds to communicate with the same controller.

(d) Means for solving the problem Performance φ=f=1 The communication control device for the ID system of the present invention includes a controller,
A device that is supplied with power from the controller without contact and includes a data carrier with a built-in memory, and that performs communication between the controller and the data carrier in order to write data to or read data from the controller to the memory of the data carrier. In the data carrier, when receiving power from the controller, the data carrier includes means for outputting a modulated signal modulated by a code with on/off of 1=1; a demodulation circuit that demodulates the modulated signal, a decoding circuit that divides and decodes the output of this demodulation circuit, an edge detection circuit that detects the rise and fall of the output of this decoding circuit, and a fixed frequency a counter that counts pulse signals of and is updated in response to the output of the edge detection circuit; and a synchronous clock signal generation circuit that generates a synchronous clock signal in response to the output of the counter; , and is configured to proceed with subsequent communication operations.

(e) Function In the communication control device of this ID system, when the data carrier receives power from the controller, it outputs a modulated signal, that is, an initial signal, which is modulated with a 1:1 on/off code. The controller receives and demodulates the modulated signal from the data carrier, further divides the frequency of this demodulated signal, and outputs a decoded signal with twice the period from the decoding circuit.

Then, the edge detection circuit detects the rise and fall of the output of this decoding circuit. These rising and falling signals become input decoded signals, that is, signals generated in accordance with the transmission speed on the data carrier side. The counter of the controller receives and counts pulse signals of a constant frequency, and is reset and updated in synchronization with the rising and falling signals. Furthermore, a synchronous clock signal is outputted from the synchronous clock signal generation circuit in accordance with the updated content of this counter. The controller then proceeds with subsequent communication operations based on this synchronized clock signal. Therefore, in this ID system, no matter what the transmission speed on the data carrier side is, the controller can always be controlled by a synchronized clock signal that matches this transmission speed, and data of any transmission speed can be controlled. Appropriate communication can also be performed in response to carriers.

(f) Examples The present invention will now be explained in more detail with reference to Examples.

FIG. 2 is a schematic block diagram of an ID system in which the present invention is implemented.

In this ID system, the ID controller 20 is
It is configured to write data to a data carrier 40 approaching the read/write head 30 via a connected read/write head 30, or to read data, in response to a command from a host controller 10.

The data carrier 40 is attached to, for example, an article or tool transferred on a conveyor, stores data corresponding to the article or tool, is composed of a one-chip IC, and has an EE
- It has a storage means such as FROM, and stores data corresponding to the article or tool attached to it.

Here, it is assumed that a plurality of read/write heads 30 are provided and various data carriers 40 arrive at the read/write heads 30 in independent systems.

The read/write head 30 is fixedly installed, and when a data carrier 40 approaches the read/write head 30, an auto-read command is given to the ID controller 2.0 via the host controller 10.
For example, the stored contents of the data carrier 40 are read.

As shown in FIG. 1, the ID controller 20 includes an upper communication interface 22 for communicating with the upper controller 10, and a controller control interface 22 for communicating with the upper controller 10. 117' A ROM 25 that stores a program, a CPU 21 that executes control operations according to this program, and a data carrier 4.
Protocol groups A, B, C, and D, which are grouped by classifying and defining the communication protocols of the communication control unit 23 and data carrier 40 for exchanging data with 0 at the physical level and data link level. The transmission speed detection/synchronization clock signal generation circuit 26 detects the data read speed of the data carrier 40, etc., and the like. These 10
As explained in FIG. 2, the controller 20 is configured to exchange data with the data carrier 40 via the read/write head 30.

As shown in FIG. 3, in the table memory 24 for protocol storage of the ID controller 20, A, B,
C and D are stored as examples. data carrier 4
The EE-PR of the data carrier 40 determines which type of protocol, ASB, C, or D, is used by the data carrier 40.
It is stored in the first address area 46a of the OM 46 as protocol identification information.

As shown in FIG. 7, the data carrier 40 includes a modem circuit 41 that is electromagnetically coupled to a read/write controller 30 connected to the ID controller 20.
A decoding circuit 42 that decodes carrier signals, a serial input circuit 43, a command decoder 44 that decodes input commands, a data buffer 45, and an EE-PR that writes, stores, or reads data.
It is comprised of a serial output circuit 47 for outputting data from the OM 46 and the EE-PROM 46, an encoding circuit 48, and the like. Data can be written to the EE-PROM 46 using a data buffer 45, for example, in units of 1 page (8 bytes).

In the EE-PROM 46 of the data carrier 40, identification information, that is, self-type data indicating what communication protocol this data carrier 40 uses is stored in the leading address area 46a. As shown in FIG. 4, the format of this identification information is a protocol classification code, that is, a code indicating the distinction between A, BSC, and D in FIG.
Further, the memory range, that is, the starting address and memory capacity are stored, and finally the type of memory, such as read-only, read/write, presence/absence of battery, etc. is stored.

As shown in FIG. 5, the transmission speed detection/synchronous clock signal generation circuit 26 of the ID controller 20 detects the rise of the output pulse signal of the modulation/demodulation circuit 51, the decoding circuit 52, the encoding circuit 53, and the decoding circuit 52. and an edge detection circuit 54 that detects a falling edge, an oscillator 55 that oscillates a pulse signal with a constant frequency fc, and a pulse signal outputted from the oscillator 55. A counter 56 that is cleared, a latch circuit 57 that latches the output of this counter 56 every time a pulse from the edge detection circuit 54 is obtained, and an arbitrary input signal from the CPU 21, such as 17 of the output of the latch circuit 57.
A latch circuit 58 that latches a binary signal, derives the output of the counter 56 corresponding to the contents of this latch circuit 58,
Multiplexer 59 outputting a predetermined synchronized clock signal
It consists of

Next, with reference to FIG. 8, the operation when an auto read command is input from the host controller 10 in the ID system of the above embodiment will be described. This auto read command is used when a data carrier arrives.
This command instructs to read the data at the address attached to this command from the data carrier.

When the ID controller 20 receives an auto-read command from the host controller 10 and detects the arrival of the data carrier 40, the ID controller 20 reads the auto-read command via the read/write head 30.
The initial signal from the data carrier 40 and the protocol identification information of the data carrier 40 are read, the corresponding communication protocol is selected from the table memory 24, and thereafter, the data carrier 40 is
It is used to communicate with

In FIG. 8, when an auto-read command is issued from the host controller IO (step 5Tl), the ID controller 20 receives this auto-read command, and the determination at step ST2 becomes YES, where the ID
The controller 20 first starts with the read/write head 30.
Turn off the head drive signal of the read/write head 30, turn off the power supply to the data carrier 40, and reset the data carrier detection flag at the same time (step 5T4), then turn on the drive signal of the read/write head 30 again, and at the same time The signal is also turned on (step 5T5).

Thereafter, when the data carrier 40 arrives and is electromagnetically coupled to the read/write head 30, the data carrier 40 receives power supply and outputs a predetermined initial carrier signal (see carrier signal A in FIG. 6). This initial carrier signal has an 8-bit configuration. The transmission speed of the data carrier 40 is detected from several bits of the first carrier signal from the data carrier 40.

This transmission speed is detected by the transmission speed detection/synchronous clock signal generation circuit 26. To explain its operation with reference to FIG. 5, first, carrier signal A is input to the modulation/demodulation circuit 51, and
Demodulation is performed at , and demodulated signal B is output (see demodulated signal B in FIG. 6).

This demodulated signal B is a special signal with an on/off period of 121, and this signal is further frequency-divided and sent to the decoding circuit 5.
2 (see sixth decoded signal C). The edge detection circuit 54 detects the rising and falling points of this decoded signal C. Then, a pulse signal E is outputted as an output of the edge detection circuit 54 for each rising point and falling point. This pulse signal E has a repetition period corresponding to the transmission speed of the data carrier 40.

On the other hand, the oscillator 55 continuously oscillates an fc pulse signal at a predetermined frequency, and its output D (see Figure 6) is input to the counter 56 and counted. The count content of the counter 56 is cleared by the output E of the edge detection circuit 54, restarts, and repeats the count I. Further, the count value of the counter 56 is launched in the latch circuit 57 by the output pulse E of the edge detection circuit 54. Therefore, the update content of the counter 56 is outputted to the output of the latch circuit 57, and this pulse number Cn becomes a signal corresponding to the transmission speed of the data carrier 40. You can know the transmission speed of Therefore,
The CPU 21 of the ID controller 20 inputs a number corresponding to this signal, for example, a count value of 172, to the launch circuit 58, and outputs the count output of the counter 56 from the multiplexer 59 at a timing corresponding to the content latched by the latch circuit 58. and outputs a synchronous clock signal. Thereafter, the communication data signal from the data carrier 40 is taken in according to this synchronized clock signal, and the communication data signal is sent to the ID controller 20.
The data carrier 40 is synchronized with this clock signal.
Communication will be conducted with Therefore, data carrier 4
It becomes possible to perform communication in accordance with the transmission speed of o.

By processing the waveform of several bits of the decoded signal, the transmission speed is detected as described above, and a synchronized clock signal is created.Then, the ID controller 20 receives communication data from the data carrier 40, so the data carrier 40 is Set detection flag.

As a result, the determination in step ST7 becomes YES, and then the protocol identification information transmitted from the data carrier 40 is saved in the buffer of the CPU 21 (step 5T8), and to which group in the table memory 24 the identification information belongs is determined. Select step 5T9),
From then on, depending on the selected protocol, the data carrier 4
For example, if the protocol of the data carrier 40 is group B, the various protocols of group B in the table memory 24
After that, data communication will be performed.

In step 5TIO, it is determined whether the protocol exists or not. If the protocol exists, in step 5Tll, the ID
The controller 20 side transmits a read command to the data carrier 40, and the data carrier 40 performs a predetermined read in response to the read command and performs a read response (step 5T12). On the other hand, if the protocol does not exist, that is, if the identification information of the data carrier 40 does not exist in the table memory 24,
The determination in step 5TIO is No, and an auto-read response indicating that is sent back to the host controller 10 (step 5T13). Furthermore, even if a normal read response is responded to, an auto read response indicating that response is returned to the upper controller 10 side.

In the above embodiment, the operation was explained when an auto read command was input from the host controller 10 to the ID controller 20, but which communication protocol to select is not limited to the auto read command. , the same operation occurs when a normal read command from the host controller 10 is input.

That is, when a read command is input from the host controller 10, the drive signal for the read/write head 30 is turned off under the control of the ID controller 20, and then the read/write drive signal is turned on and the power is turned off. By turning on, by reading predetermined identification information data from the data carrier 40, it is possible to select any one of protocols A, B, C, and D, as in the case of auto-read described above.

In addition, in the above embodiment, the communication protocols that are classified and defined are four types: A, BSC, and D, and the physical level and data link level are also illustrated in FIG. 3, but the definitions and types of protocols that can be selected are It goes without saying that it can be selected arbitrarily and is not limited to the examples.

(g) Effects of the Invention According to this invention, even when a plurality of data carriers with different transmission speeds arrive at one ID controller, each data carrier is transmitted with a 1:1 on/off signal. A certain special initial signal is output, and the controller side demodulates this carrier signal to obtain a predetermined decoded signal, outputs a count value according to the transmission speed, and creates a synchronized clock signal according to this count value. Even if the data carriers have different transmission speeds, we create a synchronized clock signal that matches the data carrier transmission speed, and use this to proceed with subsequent communication operations, so that no data carrier arrives. It is possible to realize an ID system in which communication can be performed at all times even when the data carrier is used, and the system configuration is flexible without being limited by the type of communication speed of the data carrier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an ID controller of an ID system in which this invention is implemented, FIG. 2 is a schematic block diagram of an ID system in which this invention is implemented, and FIG. 3 is an embodiment ID system. FIG. 4 is a diagram showing the format of protocol identification information stored in the data carrier, and FIG. 6 is a circuit waveform time chart for explaining the operation of the transmission speed detection/synchronization clock signal generation circuit, and FIG. 7 is a block diagram showing the internal configuration of the data carrier of the ID system of the embodiment. , 8th
The figure is a flow diagram for explaining the operation of the ID system of the embodiment when an auto-read command is input. 10: Upper controller, 20: ID controller, 26: Transmission speed detection/synchronous clock signal generation circuit,
40: Data carrier, 54: Edge detection circuit, 55: Oscillator, 57/58:
Latch circuit, 59: multiplexer. Patent applicant Tateishi Electric Co., Ltd. Agent
Patent Attorney Shigeru Nakamura Figure 3 Figure 4 Figure 6 Figure 8

Claims (1)

[Claims] (1) It includes a controller and a data carrier which is supplied with power without contact from the controller and has a built-in memory, and which is used to write data from the controller to the memory of the data carrier or to read data from the memory. In an ID system that performs communication between a controller and a data carrier, the data carrier includes means for outputting a modulated signal modulated with a 1:1 on/off code when receiving power from the controller; The controller includes a demodulation circuit that receives and demodulates the modulated signal from the data carrier, a decoding circuit that divides and decodes the output of this demodulation circuit, and detects rising and falling edges of the output of this decoding circuit. a counter that counts pulse signals of a constant frequency and is updated in response to the output of the edge detection circuit; and a synchronous clock signal generation circuit that generates a synchronous clock signal in response to the output of the counter. A communication control device for an ID system, which is equipped with a synchronous clock signal, and is configured to proceed with subsequent communication operations based on this synchronized clock signal.