JPS63228491A - Dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a reference voltage generating circuit for precharging by making both dummy cells an active condition only for a prescribed period at the time of inputting the selecting signal of a dummy cell or at the time of balancing the potential of a bit line pair. CONSTITUTION:Even when the memory information of either of the low and high of memory cells C1 and Q5 is sensed and amplified, both bit line pair potentials after keeping the balance of potential of bit line pairs BL and BL' following the above information can be made constant regardless of the memory information of memory cells C1 and Q5. By adjusting the threshold voltage of the transfer transistor of dummy cells Q7', C3; Q8', C4, and the high potential impressed to the gate and a dummy cell capacity, the bit line pair balancing voltage can be made coincident with a reference voltage VBP. Namely, in a usual operation, a power source for a reference voltage VBP (power source voltage/2 or value a little lower than it) of a large capacity is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to a circuit constituting a sense amplifier for reading out the contents of a memory cell.

2. Description of the Related Art In recent years, there has been a remarkable increase in the degree of integration of semiconductor devices, and in particular, the increase in the degree of integration and capacity of semiconductor memory devices. Dynamic semiconductor memory devices are at the cutting edge of increasing storage capacity because the memory element that makes up the memory circuit for each bit is one capacitor and one transistor, so-called one transistor cell. The unit price per bit is also low, and it has a wide range of applications from personal computers to large-scale computers.

In a dynamic semiconductor memory device, data is written into a memory cell by storing charge in a memory cell capacitor via a transfer gate transistor in response to a word line signal from a bit line.

In addition, for reading, the charge accumulated in the memory cell capacitor is transferred to the bit line that has been precharged to a reference voltage, and at that time, the slight potential change that appears on the bit line is amplified by a sense amplifier and transmitted to the output circuit. Do by doing. The operation of a conventional dynamic semiconductor memory device during sense amplification will be described below.

FIG. 2(a) is an equivalent circuit diagram of a main part of a conventional dynamic semiconductor memory device, and is a dynamic semiconductor memory device consisting of a memory cell consisting of an N-channel MOS transistor and a capacitor, a complementary sense amplifier, and a dummy cell. FIG. 2(b) schematically shows signal waveforms at various nodes in FIG. 2(a).

In FIG. 2(a), N-channel type MOS transistors QINI Q2N, Q3N, P-channel type M
A sense amplifier consisting of O3 transistors QIP, Q2PI Qsp is connected to a pair of bit lines BL, BL, and one bit line BL is connected to a capacitor CI, a transistor Q
A memory cell consisting of a capacitor C2 and a transistor Q8 is on the other bit line BL.
are connected to each other, and the transistor Qi
A dummy cell consisting of a Q131 capacitor C3 for balancing the capacitance during sensing amplification, and a dummy cell consisting of a transistor Qs r Q+41 capacitor C4 are also connected to the respective bit lines BL, BL.

Although a plurality of memory cells are generally connected to each bit line pair, here, for simplicity, explanation will be given using a diagram in which a unit of memory cells is connected to each bit line. In addition, each capacitor C3, C4 of the dummy cell
The capacitance Cd of is equal to the capacitance Cs of the memory cell capacitor ct I C2. Furthermore, each bit line BL has a bit line precharge transistor QllIQ10.
A transistor Q4 is also connected for bit line pair balancing. Transistors Q13I are also connected to the dummy cell capacitors Cs and C4, respectively.
Q' port is connected for precharging.

The transfer gate is opened and closed by the column selection signal φ2.
Transistors Qs and Q+o are connected between the bit line pair BL and the data line pair DL and DL, respectively.

Next, let us trace the clock waveforms applied to each part using FIG. 2(b). In Fig. 2(b), φIN+φIPsφ
21φ3Iφ4IφWL+φWR, φ0-L, φDWR
A lock signal as shown in FIG. 2(a) is applied to each node indicated by a corresponding symbol in FIG. 2(a). The bit line pair BL and a BL precharge signal are applied to the node φR, and the dummy cell capacitors C3 and C4 precharge signal are applied to the node φ3. Here, the reference voltage ver, which is the precharge power supply, is set slightly lower than the power supply voltage /2 in order to improve soft errors if the memory section is an N-channel MO8, so the levels of the three signals are In particular, it does not need to be higher than the power supply voltage. Nodes φWL, φWR, φDWL and φDWR have nodes φ
A signal boosted to a voltage higher than the power supply voltage is applied to W as a row selection signal/dummy cell selection signal in response to an address input. A sense amplifier driving clock is applied to the node φIN+φIP. The sense amplifier is connected to node φ when on standby.
3. A power supply voltage is applied to φR, and at this time, bit line pair BL, BL and dummy cell capacitor C3e
C4 is precharged to reference voltage V8P. When activated, first node φ3. After setting the level of φR to low, the boosted node signal φW is used as a row selection signal and a dummy cell selection signal, respectively, according to the address input signal to connect the node φ.
Apply to WL, φ ridge, φ'DWL, φ' DWR.

Now, when an address is given to select the memory cell C+ side and a boost signal is applied to the node φWL and the node φ'DWR, the memory cell capacitor C+ is connected to the bit line BL.
and a dummy cell capacitor C4 are respectively connected to the bit line BL. In the bit line BL, a change in potential appears due to the charges accumulated there. Figure 2(b)
Then, the memory cell capacitor C+ is high (power supply voltage Vc
The solid line indicates the case where c=5V) is stored.
The ratio of bit line capacitance to memory cell capacitance, i.e., cb
/ Cs ratio is 10/1, it becomes higher than the reference voltage potential VBP by about 0.25V. Also, the memory cell capacitor C+
If a low (ground potential=OV) is stored in , as shown by the broken line in FIG. 2(b), it becomes lower than the reference voltage potential vop by about 0.25V.

On the other hand, a dummy cell capacitor C4 is connected to the bit line BL to balance the capacitance of the bit line pair during sensing amplification. That is, if a high or low level is stored in the memory cell, the dummy cell capacitor C
The potentials of No. 4 are shown by solid lines and broken lines in the figure, respectively.

Next, by applying a high signal to the node φIN, the N-channel side transistors QIN, Q2N, Q3
The sense amplifier consisting of N is operated, and then the node φI
By applying a low signal to P, the sense amplifier consisting of P channel side transistors QIP, Q2P, and Qsp is operated to amplify the slight potential difference, and one is set to ground potential and the other to VCC potential, and a series of sense amplification is performed. I do. The signal of this column amplified by the sense amplifier in this way is transferred to the transfer gate by the column selection signal φ2.
The signal is transmitted to the data line pair DL and D via the transistors Q) and Q8, and then to the output terminal.

Then, at the end of the data read cycle, first, node φ2
After making low and separating the data line and bit line, the node φ- is made low, and the bit line BL and memory cell capacitor CI, the bit line BL and dummy cell capacitor C
Separate 4. Further, the node φ1N is set low and the node φ1P is set high, stopping the operation of the sense amplifier. After this, by making nodes φR2φ3 high, the circuit enters a precharge state, shortens the distance between the bit lines, and further connects the bit line pair and dummy cell capacitors c3 and c4.
is precharged to the reference voltage VBP.

Here, the amount of charge flowing in and out from the reference voltage ver will be considered with respect to the bit line pair BL, B, and dummy cell capacitors C3*C4 connected thereto. The respective capacitances are assumed to be Cb and Cd. First, in the precharge state, the total charge multiplied by these capacitors is 2VBP・(Cb+'
Cd).

Next, if high is written to memory cell CI,
Immediately after sensing amplification, it is cb-vcc+cci-vep, and if a row has been written to memory cell C+, immediately after sensing amplification, (Cb+Cd)-Vcc+cci-v,
p, and the total amount of charge accumulated in these capacitors at the time of completion of sensing amplification differs depending on the storage content of the memory cell, and also differs from the total amount of charge at the time of precharging. Therefore, this different total charge amount appears as a current with respect to the reference voltage VBP, and this current changes depending on the storage content of the memory cell.

Although the memory cell C1 has been described above, the same can be said about other memory cells. Generally, in a dynamic semiconductor memory device, a plurality of circuits as shown in FIG. 2(a) are arranged, and the plurality of circuits operate simultaneously. For example, in a general-purpose 1 megabit dynamic semiconductor memory device, it is common for about 2000 circuits as described above to operate simultaneously. Here, bit line capacitance c
b is 0.5 pF, dummy cell capacitance Cd is o, ospF'
.

A trial calculation is made assuming that the power supply voltage VCC is 5V and the reference voltage Vep is 2.45V, which is slightly lower than Vcc/2.The amount of inflow from the reference voltage VBP changes depending on the information stored in the memory cell, and is -0.36nQ to +0. It becomes 16nQ. Furthermore, considering the precharge period, this charge can be reduced to, for example, a number +
If an attempt is made to completely replenish the supply within nS, the reference voltage VBP
The equivalent power supply impedance of the circuit is several ohms.

Problems to be Solved by the Invention In the conventional circuit system as described above, the load on the reference voltage power supply vap fluctuates depending on the information stored in the memory cell, and the standard has a very large power supply capacity with an equivalent power supply impedance of several ohms or less. It was necessary to incorporate a voltage generation port. Furthermore, it is extremely difficult to create such a reference voltage generation circuit within a semiconductor integrated circuit with low power consumption and stability against process variations. Furthermore, in the layout, dummy cells require extra precharging transistors (transistor Q+3. It has become very difficult to create a compact layout, and the need to match the memory cell pitch has forced a redundant layout.

The present invention solves the above-mentioned conventional problems, does not require a reference voltage generation circuit, allows dummy cells and memory cells to be treated in the same layout size, has low power consumption, is stable in terms of process, and is compact. The present invention provides a dynamic semiconductor memory device that enables flexible layout.

Means for Solving the Problems The present invention comprises a plurality of memory cells arranged in a matrix in the form of rows and columns, and bit line pairs connected to the memory cells in each column via transfer gates. a sense amplifier having a dummy cell connected to each of the bit line pairs via a transfer gate, address input means, means for reading a signal of the sense amplifier to a data output terminal, and writing data of the data input signal terminal. The dynamic semiconductor memory device has a function of activating both the dummy cells for a predetermined period when a selection signal for the dummy cell is input or when the potential of the bit line pair is balanced.

According to the present invention, regardless of whether low or high stored information of a memory cell is sensed and amplified, the potentials of both bit line pairs after the potentials of the bit line pair are balanced regardless of the stored information of the memory cell. , can be constant. Also, the threshold voltage of the transfer gate transistor of the dummy cell,
By adjusting the high potential applied to the gate and the dummy cell capacitance, the bit line pair equilibrium voltage can be made to match the reference voltage VBP. That is, in normal operation, there is no need for a large-capacity power source for the reference voltage VBP (power supply voltage/2 or a value slightly lower than that) as described above.

Embodiment An embodiment of the dynamic semiconductor memory device of the present invention will be described below with reference to the circuit diagrams and timing diagrams shown in FIGS. 1(a) and 1(b). FIG. 1(a) is a circuit diagram of one embodiment, and compared to the conventional example of FIG. 2(a), the bit line precharge transistor Qll,
Q12, precharge transistor Q in dummy cell section
This is a configuration without Is*014. Also, Figure 1 (
In the timing diagram of this embodiment shown in FIG. 2(b), the waveform of the dummy cell selection signal φDWL *φDWR is as shown in FIG. 2(b).
This is different from the conventional example. The circuit operation of this embodiment will be explained below using these figures.

In FIG. 1(a), φIN, φIP+ φ2. φR2φW
L.

Each node corresponding to each input signal denoted by φWR is shown in Fig. 1 (
Each clock signal shown in b) is applied. node φ
A boost signal similar to the conventional example is applied to WL and φl,
Further, the high potential applied to the nodes φOWL and φDWR is related to the threshold voltage of the transfer gate transistor of the dummy cell, the dummy cell capacitance, and the reference voltage VBP, but here, for simplicity, it is assumed to be the power supply voltage VCC. First, when the sense amplifier is on standby, power supply voltages V and cc are applied to nodes φR, nodes φDWL and φDWR, bit line pair BL and dummy cell capacitor C3.

It is assumed that C4 has become the reference voltage VBP due to bit line potential balancing. Here, transistor Q'7~+
Set the threshold voltage of each Q'8 t to be lower than the value obtained by subtracting the reference voltage vap from the power supply voltage. After setting the level of the node φR to low, apply the address signal to select the memory cell C1. According to the address input signal, a high signal is applied to the boosted node φWL and the node φDWR as a row selection signal and a dummy cell selection signal, respectively.This connects the memory cell capacitor C1 to the bit line BL and stores the data there. A change appears in the bit line potential due to the electric charge that had been stored in the memory cell capacitor C1 in FIG. 1(b).
) is stored, the potential VCI is shown by a solid line, and is slightly higher than the reference voltage potential vop. In addition, when a low (ground potential = OV) is stored in the memory cell capacitor C1, as shown by the broken line, it becomes slightly lower than the reference voltage potential vap.On the other hand, since a signal is applied to the node φDWH, The dummy cell capacitor C4 is connected to the bit line BL and balances the capacitance of the bit line pair during sensing and amplification.Assuming that the memory sensor is high or low = 8, the potential VC4 of the dummy cell capacitor C4 is This is shown by solid lines and broken lines in FIG.

By operating the sense amplifier consisting of Q 2N and Q 3N and subsequently applying a low signal to the node φIP, the P-channel side transistors QIP and Q2P are activated.
.

A sense amplifier consisting of Q3P is operated to amplify a slight potential difference, and one side is connected to the ground potential and the other side is connected to the power supply voltage VCC.
potential and perform a series of sensing amplifications. During this sense amplification, the unselected dummy cell signal line φ0%4L is set to the power supply voltage to activate this unselected dummy cell. However, the timing of this activation should be set to avoid the initial stage of sensing amplification so as not to cause noise to the sensing amplification. By doing so, it is possible to charge one dummy cell capacitor with a high potential and the other dummy cell capacitor with a low potential during sensing amplification. However, the high potential charged to the dummy cell capacitor is the power supply potential minus the threshold voltage of the transfer gate transistor. The column signal amplified by the sense amplifier is transferred to the transfer gate transistor Qs v Q by the column selection signal φ2.
+o to the data line pair DL, DL, and then to the output terminal.

At the end of the data read cycle, first, the node φ2 is set low, the data line and the bit line are separated, and then the node φ-R is set low, and the bit line BL and the memory cell/capacitor CI are connected to each other, and the bit line BL and the dummy cell are connected to each other. - Isolate capacitor c4.

Further, the node φIN is set low and the node φIP is set high, stopping the operation of the sense amplifier. After this, the node φR is made high, the bit line potential is balanced, and after being balanced, the node φD%4L+φDWR is made low, completing the precharge and entering a standby state. In this embodiment circuit, there is no reference voltage power supply, so the total amount of charge within the circuit system must be preserved before and after the bit line potential balancing. Bit lines BL, BL, dummy cell capacitor c3 in the circuit system
, c4. Let the respective capacitances be Cb and Cd. First, after the bit line potential is balanced, the total charge stored in these capacitors is 2Vep.
・It is given by (Cb+Cd,). Next, just before bit line potential balancing, according to this embodiment, regardless of whether high or low is written to the memory cell capacitor CI, the total charge amount is Cb-vcc+cd(vcc+
vT). (However, vT is a transfer gate
(Threshold voltage of transistors Q7 and Qa) To equalize the total amount of charge of both transistors, the threshold voltage vT of the transfer gate transistor should be appropriately selected, and the reference voltage V at that time
ap is Vcc/2-Cd-Vt/(Cb+Cd)/
It is given by 2. Under the same conditions as the conventional example, for example, if the threshold voltage vT is 1.1V, the reference voltage ver is 2.4V.
It is possible to make it 5V.

Effects of the Invention According to the present invention, the precharge potential of the bit line pair can be set to be slightly lower than half of the power supply voltage only by equalizing the bit line pair potential, thereby eliminating the need for a precharge reference voltage generation circuit. Furthermore, dummy cells and memory cells can be treated in the same manner in terms of layout dimensions. The present invention provides such a dynamic semiconductor memory device.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are circuit diagrams of an embodiment of the present invention,
FIGS. 2(a) and 2(b) are a circuit diagram of a conventional example and a schematic diagram of signal waveforms. Q+N* Q2Nl-Q3N, QIPI Q2PI
Q3P/Old...Transistor that makes up the sense amplifier, C
+, Qs...Capacitor and transistor forming memory cell A, C2* Qe...Capacitor and transistor forming memory cell, Q゛7*
C3...Transistor and capacitor forming a dummy cell, Q's, C4-=transistor and capacitor forming a dummy cell, BL,
B L ・−・−・Bit line pair, DL, DL・・・・
...Data line pair. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 (7) I/n~p Figure 1 (b) LL. 2nd m (7th floor) (υ 2nd Fl! J (b)

Claims (1)

[Claims] a sense amplifier having a plurality of memory cells arranged in a matrix in rows and columns, and a bit line pair connected to the memory cells in each column via a transfer gate;
a dummy cell connected to each of the bit line pairs via a transfer gate, address input means, and means for reading out a signal from the sense amplifier to a data output terminal;
and means for writing data of a data input signal terminal, and is characterized in that both the dummy cells are activated for a predetermined period when a selection signal is input to the dummy cell or when the potential of the bit line pair is balanced. Dynamic semiconductor memory device.