JPS63228338A - Data altering system for double system - Google Patents

Abstract

PURPOSE:To shorten a time for restarting a process at the time of switching a system since trouble occurs by providing a means for rewriting the memory data of an address informed by accessing the memory of a spare processing device in terms of direct memory access at the time of receiving packet data in the spare system device into updated data. CONSTITUTION:An altered data information reception part 8 of the spare system side obtains the address information and the data value of the altered data from the packet data received from a transmission line 7 and outputs a bus holding request to a spare system device main body part 14 through a bus holding request signal line 12 in order to alter the memory data on the spare system device main body part 14. At the time of receiving an answer through a bus holding answer signal line 13, it respectively outputs the address information of the altered data, altered data value and a write signal to an address line 9, a data line 10 and a write signal line 11 and the contents of the memory of the spare system device main body part 14 is rewritten to the altered data value. Thus, the spare system can take over the normal data before starting the process and restart the process if the trouble occurs in an operational system.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for changing data in a redundant system, and in particular, the present invention relates to a method for changing data in a redundant system, and in particular, the present invention relates to a method for changing data in a redundant system. The present invention relates to a data change method for a redundant system in which data in a standby device is changed at the same time as data in a device is changed.

[Conventional technology]

Conventionally, data modification methods for this type of duplex system include a processor bus coupling method and a disk coupling method. In the processor bus coupling method, the active and spare memories are connected to the active processor bus, so when the active processor writes to memory, data is written to both memories at the same time. . In addition, in the disk combination method, a disk that can be accessed from both systems by switching is installed between the active system and the standby system, and the memory data of the active system is written to the disk in a timely manner.
When a failure occurs, the contents of the disk are read into the spare memory and processing can continue.

[Problem that the invention seeks to solve]

The conventional processor bus coupling method described above has the disadvantage that the number of connection points between the active system and the backup system is large because it is bus-coupled, and all data written on the active system is also transferred to the backup system at the same time. Since the data is written, if the active system fails and writes incorrect data, the fault is that incorrect data will also be written to the standby system, and correct processing will not continue when processing is transferred to the standby system. The conventional disk combination method described above has the disadvantage that when a failure occurs and the system is switched, data from the disk is sucked up into memory in the standby system, so it takes time to restart processing.

[Means for solving problems]

In the data change method of the duplex system of the present invention, the active device has means for generating memory data change information only when a change notification instruction is received from the processing device, and address information of the changed memory in the memory data change information. means for serially transmitting to the standby system device in the form of packet data consisting of two pieces of information: and a data value after the change, and when the standby system device receives the packet I data, it stores the memory of its processing device. It is equipped with means for directly accessing the memory and rewriting the memory data at the notified address with updated data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system block diagram showing one embodiment of the present invention.

In FIG. 1, an address line 2 of a processor bus is connected to an active device main unit 1. Data line 3. Write signal line 4. A change data information transmitter 6 connected via a change notification instruction signal line 5 generates information regarding data changes in the operational system,
Converts information into packet data and transmits the information to the backup system. When the change data information transmitter 6 receives a change notification instruction from the active device main unit 1 via the change notification instruction signal line 5, the change data information transmitter 6 transmits the address line 2. Data line 3. The write signal line 4 is monitored to obtain the address information and data value of the data written in the memory, which is packetized and serially transmitted to the transmission line. The changed data information receiving unit 8 on the standby side obtains the address information and data value of the changed data from the packet data received from the transmission path 7, and sends the address information and data value to the standby system main unit 14.
In order to change the memory data of
4 via the bus hold request signal line 12, and when a response is returned via the bus hold response signal line 13, the address line 9. The address information, the changed data value, and the write signal of the changed data are sent to the data line 10 and the write signal line 11, respectively, and the memory contents of the standby device main body section 14 are rewritten to the changed data values.

〔Effect of the invention〕

As explained above, the present invention generates and notifies memory data change information only when a change notification instruction is received from a processing device in the active system, thereby allowing a certain unit of processing to be completed normally in the active system. Once this is confirmed, the backup system can change the data necessary to continue processing when the system is switched over, and if a failure occurs in the middle of a process on the active system, the backup system can This has the effect that the normal data before the start of the process can be taken over and the process can be restarted. Furthermore, by serially transferring the data change information, the number of connection points between the active system and the backup system is reduced, so there is an effect that the active system and the backup system can be installed at a distance. Furthermore, by writing data using the direct memory access method on the standby side, the standby processor can check the normality of the operation of the active system without rewriting memory data in the same area as the memory area used by the active system during standby. It has the effect of processing such things as

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing one embodiment of the present invention. 1...Operational device main unit, 2, 9...Address line,
3.10...Data line, 4,11...Write signal line, 5...Change notification instruction signal line, 6...Change data information transmitter, 7...Transmission line, 8... Changed data information receiving unit, 12... bus hold request signal line, 13...
Bus hold response signal line.

Claims (1)

[Claims] In a data change method of a redundant system in which the memory contents of the standby system are changed at the same time as the memory data of the active system is changed in order for the standby system to operate and take over processing when a failure occurs in the active system, the active system apparatus is means for generating memory data change information only when a change notification instruction is received from a processing device; means for serially transmitting the packet data to the standby system device in the form of a direct memory access to the memory of the processing unit when the standby system device receives the packet data, and converts the memory data at the notified address into updated data. A data change method for a duplex system, characterized by comprising a means for rewriting data.