JPS63228209A - Optical coordinate detector - Google Patents

Abstract

PURPOSE:To reduce a time to occupy a host computer, etc., and to improve the activity efficiency of the host computer, etc., by repeating scan in a device itself, and outputting only an input coordinate detected finally when a coordinate input operation is canceled. CONSTITUTION:A clock signal (a) is supplied from the host computer to a counter circuit 1, and the counter value (b) of the counter circuit 1 is supplied to a pulse generator 3, a coordinate detecting part 4, and a comparison part 5. The coordinate input operation is performed and the scan is repeated until the input coordinate is detected, and when the input coordinate is detected, the storage of a coordinate storing means 17 is rewritten, and the scan is repeated until no more input coordinate is detected. And when no detecting signal is detected by more, the input coordinate detected finally and stored in the coordinate storing means 17 is outputted to the host computer, etc. In such a way, it is possible to reduce the time to occupy the host computer, etc., and to improve the activity efficiency of the host computer, etc., using with another usage in common.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an optical coordinate detection device in which, when a coordinate input operation is performed, only the last input coordinate detected in the coordinate input operation is output. It is related to.

(Prior Art) Generally, an optical coordinate detection device has a plurality of pairs of light sources and corresponding light receiving elements arranged at a predetermined pitch, and sequentially drives the light sources according to a counter value output from a counter circuit. When the optical path is blocked by the coordinate input operation and the corresponding light receiving element cannot receive light, a detection signal is output, and a counter value corresponding to this detection signal is detected as the input coordinate. In addition, X
A device that performs coordinate detection using the -Y coordinate includes a plurality of pairs of light sources and corresponding light receiving elements arranged in the X-axis direction and the Y-width direction.

In the case of conventional optical coordinate detection devices, an undetected code indicating that the detected input coordinates or coordinates were not inputted manually is output to the host computer etc. every time - scans are completed. Ru. Further, the next scan is started by a signal from a host computer or the like.

(Problems to be Solved by the Invention) In the conventional optical coordinate detection device described above, a certain signal is output every time − scans are completed, and the scans are performed at short intervals. Since this is repeated, the host computer, etc., which receives and receives the signal and outputs the signal to start the scan, is occupied for a long time, resulting in a problem that the host computer, etc., which is used for other purposes, is inefficiently used.

In addition, since the input coordinates are output every time they are detected, the input coordinates will also be output if the coordinate input operation is performed incorrectly, resulting in a large burden on the host computer etc. that processes these outputs. There is.

An object of the present invention is to solve the problems of the conventional optical coordinate detection device described above, and to provide an optical coordinate system that outputs only the last input coordinate detected in a coordinate input operation. The object of the present invention is to provide a detection device.

(Means for Solving the Problems) In order to achieve the above object, the optical coordinate detection device of the present invention includes a plurality of pairs of light sources and light receiving elements corresponding thereto, and a counter output from a counter circuit. The light source is sequentially driven and scanned according to the value, and when the optical path is blocked by the coordinate input operation and the corresponding light receiving element cannot receive light, a detection signal is output and the input coordinate corresponding to the counter value is detected. In the optical coordinate detection device, the detection presence/absence determination means determines the presence or absence of the detection signal, the coordinate storage means rewrites and stores the input coordinates corresponding to the detection signal, and the scan end determination means detects the end of the scan. and a detection signal storage means for storing the detection of the detection signal in the scan, and a detection signal storage means for storing the detection of the detection signal when the end of the scan is detected by the true scan end Y determination means. In the state where the detection signal is not detected, the counter circuit is reset and starts counting to repeat the scan, and the detection signal is detected by the detection presence/absence determination means with the detection signal storage means storing the detection signal. and an operation control means for rewriting the input coordinates stored in the coordinate storage means and outputting the input coordinates stored in the coordinate storage means if the input coordinates are not detected;
It is configured with.

(Function) Scanning is repeated until the input coordinates are detected after a coordinate input operation is performed, and when the input coordinates are detected, the memory of the coordinate storage means is rewritten and the scanning is repeated until the input coordinates are no longer detected, and the detection signal is detected. When the input coordinates are exhausted, the input coordinates detected last and stored in the coordinate storage means are outputted to a host computer or the like.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block circuit diagram of an embodiment of the optical coordinate detection device of the present invention, and FIG. 2 is a block circuit diagram of a comparison section of FIG. 1.

First, the overall structure will be explained with reference to FIG. In FIG. 1, a clock signal a is applied from a host computer to a counter circuit 1, and a counter value of this counter circuit 1 is applied to a switch 2, a pulse generator 3, a coordinate detector 4, and a comparator 5. Further, a reset signal C is given from the host computer to the counter circuit 1, the comparator 5, the detection start coordinate memory 6, and the continuous counter circuit 7.

Then, the drive signal d from the pulse generator 3 is transmitted to the coordinate detection section 4.
The detection signal e is sent to the comparator 5 via the amplifier circuit 8.
given to. Furthermore, a detection accuracy switching signal f is transmitted from the host computer to four interlocking switching switches 9.10.11.
given to 12. The counter value of the counter circuit 1 is applied to the detection start coordinate memory 6 via the switch 2, and the counter value g stored in the detection start coordinate memory 6 is applied directly or via the switch 9 to the double multiplier I3. is applied to the switch IO via the switch IO, and is applied to the adder 14 via the switch IO. Further, the counter value of the continuous counter circuit 7 is applied via a switch 11 to a 1/2 divider 15 or directly to a switch 12, and via this switch 12 to an adder 14. It will be done. The calculated value i of the adder 14 is applied to an output code memory 17, which is a coordinate storage means, via a switch 16, where it is converted into a code and stored. Further, an error code is applied from the error code memory 19 to the output code memory 17 via the switch 20 and is stored therein. Furthermore, the output of the output code memory 17 is given to the output control section 18 via the switch 21. Then, from the comparator 5, the signal j is given to the switch 2, the signal k is given to the continuous counter circuit 7, the signals JZ, m, and n are given to the switches 16, 20, 21, respectively, and the signal 0 is given to the counter circuit 1. Then, an output control signal p is given to the output control section 18 from the host computer, and output data q is given to the host computer.

Next, the comparing section 5 will be explained with reference to FIG. In FIG. 2, a detection signal e is given to a detection presence/absence comparator 31 which is a means for determining presence/absence of detection, and if a detection signal exists in one scan, a signal "e" is given to a detection start comparator 32; In this case, the signal S is given to the continuous flag memory 33. Then, the detection start comparator 32 inputs the signal S to the continuous flag memory 33.
4 is in a reset state or a set state, and if it is in a reset state, the detection start flag memory 34 and the continuous flag memory 33 are set, the independent counter 35 is incremented by 1, and the switch 2
A signal j that temporarily closes is output, and a signal t is provided to the continuous detection comparator 36 if it is in the set state. The continuity detection comparator 36 to which this signal t is applied determines whether the continuous flag memory 33 is in a reset state or a set state, and if it is in a reset state, it increments the individual counter 35 by 1; For example, a signal k is given to the continuous counter circuit 7.

Further, the scan end counter value memory 37 stores in advance a counter value at which one scan ends, and this scan end counter value U is given to the scan end comparator 38. The scan end comparator 38 is given a counter value S, and when the scan end counter value U and the counter value S match, a signal V is given to the error non-detection comparator 39 and the detection start flag memory 34. Note that the scan end counter value memory 37 and the scan end comparator 38 form a scan end determination means. Then, the error undetected comparator 39 to which the signal V is applied gives the signal It is applied to the switch 16 connected to the adder 14, the counter circuit 1, the individual counter 35, and the detection flag memory 41, and
If the above is the case, the signal m is applied to the switch 20 connected to the error code memory 19 and the counter number 1, 7, 7, 7, and 7 to 41. Further, the detection flag comparator 40 outputs the signal n to the switch 2 in the state of the detection flag memory 41 when the signal X is applied.
1 or a signal 0 to the counter circuit 1. The detection flag memory 41 forms a detection signal storage means, and the individual counter 35, the error undetected comparator 39, and the detection flag comparator 40 form an operation control means. Note that the reset signal C is given to the detection start flag memory 34 and the independent counter 35.

The operation of such a configuration is as follows. Reset signal C
When the counter circuit 1 is released, the counter circuit 1 starts counting, and the light sources are sequentially driven in the coordinate detection section 4 to start scanning. Then, when the coordinate input operation is performed and the first detection signal e is provided from the coordinate detection section 4 to the comparison section 5, the detection presence/absence comparator 31 operates the detection start comparator 32. Here, the detection start flag memory 34 is in a reset state, and the signal j is output and the detection start flag memory 34 is in a reset state.
4 and the continuous flag memory 33 are set, the individual counter 35 is incremented to 1, the switch 2 is temporarily closed, and the counter value of the counter circuit 1 is stored in the detection start coordinate memory 6. be remembered. When the detection signal e is continuously given to the comparator 5 in one scan,
Since the detection start flag memory 34 is in the set state, the detection start comparator 32 applies the signal t to the continuous detection comparator 36 to operate it. The continuity detection comparator 36 supplies the signal k to the continuity counter circuit 7 since the continuity flag memory 33 is in the set state. When the detection signal e is continuously applied to the comparator 5, this signal is applied to the continuous counter circuit 7 and counted by the number of consecutive detection signals minus 1.

Here, if the detection signal e is not given to the comparator 5 in one scan, the independent counter 35 remains at 0. Further, when only one detection signal e is given, the independent counter 35 becomes 1 and no signal is output from the continuous detection comparator 36. Then, after − scans, the detection signal e
When the detection signal e is interrupted once and is given to the comparator 5 twice or more, when the first detection signal e is interrupted, a signal S from the detection presence/absence comparator 3 is given to the continuous flag memory 33 to set it in a reset state. Therefore, in response to the next detection signal e, an incrementing signal is given from the continuous detection comparator 36 to the single counter 35, and the single counter 35 takes on a value of 2 or more.

By the way, according to the detection accuracy switching signal f, the switching devices 9 and 1
0, the counter value g is directly given to the adder 14, and the counter value is multiplied by 1/2 by the divider 15 and given to the adder 14 via the switchers 11 and 12.
The counter value g stored in the detection start coordinate memory 6 is A,
If the number of consecutive detection signals e is N and the calculated value of the adder 14 is B, then the counter value of the continuous counter circuit 7 is (N-1
), and (N-1) B = A + □ By rounding off the decimal point, etc., the average value of the input coordinates from which the detection signal e is continuously obtained is equal to the pitch at which the light source and light receiving element are arranged. Calculated with precision.

Further, the counter value g is doubled by the multiplier 13 via the switchers 9 and 10 by the detection accuracy switching signal f, and the counter value g is doubled by the adder 14.
When the counter value is directly applied to the adder 14 via the switches 11 and 12, the adder 1
If the calculated value of 4 is B', then B' = 2A+ (N-1
) becomes.

In addition, the calculated value B corresponds to the light source and the light receiving element,
The coordinates are set at the arrangement pitch of light sources, etc., but the calculated value B'
are coordinates whose pitch is 1/2 of the arrangement pitch of light sources, etc.

Here, for the scan performed after the reset signal C is released, if no coordinate input operation is performed and no detection signal is output, the independent counter 35 is 0, and the scan end comparator 38 outputs the signal V. Then, the error undetected comparator 39 supplies No. 43 X to the detection flag comparator 40. Note that the detection start flag memory 34 is reset by the signal V. Then, since the detection flag memory 41 is in the reset state, the detection flag comparator 40 to which the signal X is applied supplies a signal 0 to the counter circuit 1 to reset it and start counting. Therefore, scanning is repeated until a detection signal is detected.

Then, when the detection signal is output, the counter value of the independent counter 35 becomes // 1 // or "2 or more".

Here, when the scan is completed and the signal V is given to the error non-detection comparator 39, if the counter value of the individual counter 35 is 1, the signal 2 is output and the switch 16 is temporarily closed. and stores the calculated value i of the adder 14 in the output code memory 17, sets the individual counter 35 in a reset state, sets the detection flag memory 41 in a set state,
Further, the counter circuit 1 is reset and counting is started. Similarly, if the counter value of the individual counter 35 is 2 or more, the signal m is output and the switch 20
is temporarily closed and the error code in the error code memory 19 is stored in the output code memory 17, the individual counter 35 is reset, the detection flag memory 41 is set, and the counter circuit 1 is roughly reset. and start counting. When the detection signal is detected continuously for each scan, the switch 16.
20 is temporarily closed and the memory in the output code memory 17 is rewritten.

Furthermore, if the detection signal is not detected after scanning, the error undetected comparator 39 to which the signal V is applied supplies the signal X to the detection flag comparator 40.
0 determines that the detection flag memory 41 is in a reset state and applies a signal n to the switch 21 to temporarily close it, and the memory in the output code memory 17 is applied to the output control section 18. Then, the output control signal p from the host computer
Accordingly, the output control unit 18 provides the host computer as output data q.

Note that the above embodiment shows a device that detects coordinates by scanning in the -axis direction, and in order to detect coordinates in the X-Y coordinates, the block circuit surrounded by the dashed line in FIG. Two block circuits are provided, one block circuit is scanned as an X-axis coordinate detection device, and when the scanning of this one device is completed, this block circuit is made inactive, and the other block circuit is scanned as a Y@ coordinate detection device. Just let it happen.

(Effects of the Invention) As explained above, according to the optical coordinate detection device of the present invention, until a coordinate input operation is performed and after a coordinate input operation is performed until this operation is canceled, The device of the present invention repeats scanning, and when the coordinate input operation is canceled, only the last detected input coordinates are output, so if the input position is correct when the coordinate input operation is canceled, accurate coordinate input can be performed. Can be done. In addition, since no signal is output until a coordinate input operation is performed or after a coordinate input operation is performed and until this operation is canceled, there is less time to occupy the host computer, etc. It has the excellent effect of being able to be used for other purposes for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the optical coordinate detection device of the present invention, and FIG. 2 is a block circuit diagram of a comparison section of FIG. 1. 1: Counter circuit, 4: Coordinate detection section, 5: Comparison section, 17: Output code memory, 3I: Detection presence/absence comparator, 35: Individual counter, 37: Scan end counter 38 Niscan end comparator, 39: Error not detected Comparator, 40: Detection flag comparator, 41: Detection flag memory. Patent Applicant Alps Electric Co., Ltd. Agent Patent Attorney Tetsuto Moriyama■

Claims (1)

[Claims] A plurality of pairs of light sources and corresponding light-receiving elements are arranged, and the light sources are sequentially driven and scanned according to the counter value output from the counter circuit, and the optical path is interrupted by coordinate input operation, and the corresponding light-receiving elements are In an optical coordinate detection device that detects input coordinates corresponding to the counter value by outputting a detection signal when light cannot be received, the apparatus includes a detection presence/absence determining means for determining the presence or absence of the detection signal, and an input corresponding to the detection signal. A coordinate storage means for rewriting and storing the coordinates, a scan end determination means for detecting the end of the scan, a detection signal storage means for storing the detection of the detection signal in the scan, and a scan end determination means for determining the end of the scan. When the detection signal is detected and the detection signal is not stored in the detection signal storage means, the counter circuit is reset and counting is started to repeat the scan, and the detection signal is stored in the detection signal storage means. In the state where the detection is stored, when the detection signal is detected by the detection presence/absence determining means, the input coordinates stored in the coordinate storage means are rewritten, and when the detection signal is not detected, the input coordinates stored in the coordinate storage means are output. An optical coordinate detection device characterized by comprising: operation control means for controlling.