JPS63226126A - Carrier jitter canceller - Google Patents

Abstract

PURPOSE:To apply the titled canceller even to a carrier phase jitter control system including a delay in its control loop by using an output of an adder adding outputs of multipliers as a phase jitter correction signal. CONSTITUTION:The titled jitter is provided with a Fourier coefficient generating means 101, a coefficient correction means 102, a multiplier 103 and an adder 104. That is, the Fourier coefficient generating means 101 applies Fourier transformation to a signal of an extracted phase jitter to generate a Fourier coefficient group, and the coefficient correction means 102 generates adaptively a complex number coefficient group from a signal of residual phase jitter. Moreover, plural multipliers 103 multiply the complex number coefficient group of the coefficient correction means 102 with the Fourier coefficient group of the Fourier coefficient generating means 101, the adder 104 adds outputs of each multiplier 103 to generate a phase jitter correction signal. In case of applying the phase jitter correction in this way, the canceller is applied even to a carrier phase jitter control system whose control includes a decoder having a delay in its decoding.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 6 to 8) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Effects Embodiments (Figs. 2 to 5) Effects of the invention [Summary] Carrier jitter that multiplies a received signal to create a phase jitter correction signal for removing carrier phase jitter in a carrier phase jitter control system in a voice band modem. In the canceller, the jitter components extracted from the received signal are sequentially converted into the frequency domain by determining Fourier coefficients via a frequency sampling circuit, etc., and then the Fourier coefficients are multiplied by the coefficients adaptively determined from the residual jitter components. By obtaining a phase jitter correction signal that matches the phase relationship with the jitter component to be canceled, accuracy can be improved even in a carrier phase jitter control system that includes a delay such as a decoding delay in a decoder for an error 9 correction code in the control loop. To be able to cancel jitter well.

[Industrial application field]

The present invention relates to a carrier jitter canceler for removing carrier phase jitter from a received signal in a voice band modem, and particularly to a carrier jitter canceler that can be applied even when a control loop includes a delay due to a decoding delay of an error correction code. It is related to.

In the case of a data transmission method using a telephone line using a modem,
Various deterioration factors (noise, etc.) in the transmission path.

amplitude distortion, 1 group delay distortion, 1 phase jitter, phase hit, instantaneous interruption, etc.)
This causes deterioration of transmission quality. Of these, phase jitter occurs on the carrier due to the influence of the commercial power supply.
z, 601 (phase fluctuation at the frequency of z and its harmonics, which is a major deterioration factor in high-speed modems with high signal multilevel levels.

Therefore, in high-speed modems, it is necessary to suppress the phase jitter of the received signal with high precision, so a carrier phase jitter control system is used. Therefore, it is desired that the method be applicable even when the control loop includes a delay.

[Conventional technology]

FIG. 6 shows an example of the configuration of a conventional carrier phase jitter control system. In the figure, reference numeral 1 denotes a multiplier circuit which multiplies the demodulated signal input by a phase jitter correction signal to produce an output in which the phase jitter of the demodulated signal (carrier) is canceled.

Reference numeral 2 denotes a determination circuit which receives a phase jitter compensated demodulated signal as input and correctly determines and decodes the input signal even when its amplitude deviates from a specified value, for example, and generates a determined output. Reference numeral 6 denotes a subtraction circuit which extracts residual excess components in the input signal by subtracting the judgment output from the phase jitter-compensated demodulated signal. A jitter component extraction circuit 4 extracts a carrier jitter component from the residual excess component of the subtraction circuit 3 to generate the above-mentioned phase jitter correction signal.

In the carrier phase jitter control system shown in FIG. 6, it is unavoidable that the jitter component extraction circuit 4 feeds back the effects of noise other than jitter components and judgment errors as a phase jitter correction signal. Phase jitter correction cannot be performed well.

FIG. 7 shows another example of the conventional carrier phase jitter control system. In the same figure, 51 * 5 meaning + 5a
.

Number 5 is a band pass filter (BPF) with 507, 60, 1007, and 1207 outputs, respectively, which extracts the commercial power frequency and its harmonic components from a signal having an input phase θK. lH+ 61163.64 are jitter component extraction units, which extract residual jitter components weighted by the adaptively determined coefficient g. These respective jitter components are added by an adder circuit 7 H+ 71 + 71 to generate a correction signal θX. By subtracting the correction signal θK from the signal having the residual jitter θ in the subtraction circuit 8, a signal having the residual jitter θK is obtained.

In the methods shown in FIGS. 6 and 7, jitter components are extracted using general output determination results. Therefore, when the line condition deteriorates and the number of judgment errors 9 increases, it becomes impossible to correctly correct jitter using the correction signal.

However, if the decoding result corrected for the error 9 is used for extracting the phase error signal and controlling jitter cancellation, the influence of the erroneous decision can be reduced. However, in this case, since a delay is involved during decoding, the phase jitter component extracted from the decoding result is delayed by the decoding delay MT (T is the symbol interval), and therefore cannot be used as it is as a correction signal.

FIG. 8 shows another example of a conventional carrier phase jitter control system, which is also applicable when using an error correction code. In the same figure, 1 is a multiplication circuit similar to that in FIG. 6, which cancels the phase jitter of the demodulated signal by multiplying the demodulated signal input by a phase jitter correction signal. Reference numeral 11 denotes a Tobi decoder which inputs the phase jitter-compensated demodulated signal, performs error correction, and outputs a decoded signal. Reference numeral 12 denotes a dividing circuit which generates a residual phase jitter signal by dividing by the decoding result signal, which is the phase jitter corrected demodulated signal delayed through the delay circuit 13. Reference numeral 14 denotes a divider circuit which generates an extracted phase jitter signal by dividing by a signal of the decoding result, which is a demodulated signal delayed through the delay circuit 15. Here, delay circuits 13 and 15
This is provided to compensate for the delay time during error correction decoding in the gate and decoder 11.

16 is a transpersal prediction filter, M
Linearly predict the jitter component at the symbol destination and extract the phase jitter. A jitter canceller 17 generates a phase jitter correction signal from the phase jitter extracted from the prediction filter 16 by being controlled by the residual phase jitter signal. Here, the prediction filter 16 constitutes a bandpass filter tuned to the commercial power frequency.

[Problem that the invention seeks to solve]

In a carrier phase jitter control system using a conventional error-9 correction code as shown in Fig. 8, a transparsal prediction filter with a long number of taps is generally required as a bandpass filter to extract low-frequency jitter. be. Furthermore, in order to suppress even the harmonic components of the commercial power supply frequency, it is necessary to provide a bandpass filter for the harmonic components in parallel with the power supply frequency filter. Therefore, such a front carrier phase jitter control system has a problem in that the circuit scale becomes large.

In addition, since the circuit scale of the Trans-Sal type filter becomes large, in order to avoid this, I
R(Infinite Imputse Re5pon
If a se) filter is used, it may cause characteristic deterioration due to waveform distortion.

[Means for solving problems]

The present invention aims to solve the problems of the prior art, and as shown in FIG. 1, the basic configuration of which is shown in FIG. The jitter-compensated demodulated signal is added to the decoder and decoded to obtain the decoded signal, and the phase-jitter-compensated demodulated signal is delayed by the decoding delay time of the demodulator and the decoded signal. The residual phase jitter signal is extracted by the difference between the input demodulated signal and the decoding result signal, and the extracted phase jitter signal is generated by the difference between the input demodulated signal delayed by the decoding delay time of the decoder and the decoding result signal. In a jitter canceller of a carrier phase jitter control system that generates a phase jitter correction signal by adding a signal and an extracted phase jitter signal to a jitter canceller, a Fourier coefficient generating means 1
01, a coefficient correction means 102, a multiplier 103, and an adder 104.

The Fourier coefficient generating means 101 performs Fourier transform on the extracted phase jitter signal to generate a group of Fourier coefficients.

The coefficient correction means 102 adaptively generates a complex coefficient group from the residual phase jitter signal.

The plurality of multipliers 103 multiply the Fourier coefficient group of the Fourier coefficient generation means 101 by the multiple coefficient group of the coefficient correction means 102.

The adder 104 adds the outputs of each multiplier 103 to generate a phase jitter correction signal.

[For production]

After receiving, the m signal is multiplied by a phase jitter correction signal and its phase is inverted, thereby canceling phase jitter in the received demodulated signal. At this time, the phase jitter correction signal used for correction is obtained by Fourier transforming the phase jitter component extracted from the received demodulated signal, that is, the extracted phase jitter.
The Fourier coefficients of each component frequency are generated and converted into the frequency domain, and then the complex coefficients of the ninth component frequency are adaptively calculated from the phase jitter component extracted from the demodulated signal after phase jitter correction, that is, the residual phase jitter. By multiplying by and finding the sum of the multiplication results, the optimum phase is obtained for the phase jitter to be canceled in the received demodulated signal.

Since such phase jitter correction is performed, the carrier jitter canceller of the present invention can also be applied to a carrier phase jitter control system including a decoder with a decoding delay in the control loop.

〔Example〕

FIG. 2 is a block diagram showing a configuration example of a carrier phase jitter control system according to the present invention, in which 21 is a multiplication circuit, 22 is a decoder, 23 and 24 are subtraction circuits, 25 and 26 are delay circuits, 27 and 28 2 is a phase error extraction circuit, and 29 is a carrier jitter canceller.

FIG. 3 shows one embodiment of the present invention.
The figure shows an example of the configuration of the carrier jitter canceller 29, in which 31 is a frequency spring/spring circuit;
326.321 + 321 +...+32N-t is a multiplication circuit, 63 is a coefficient correction circuit, and 34 is an addition circuit.

FIG. 4 is a diagram showing an example of the circuit configuration of frequency sampling circuit 610 in the carrier jitter canceller shown in FIG. 3.

In FIG. 2, the demodulated signal is multiplied by a phase jitter correction signal in a multiplication circuit 21 to produce an output with phase jitter canceled. The decoder 22 decodes this signal and outputs a decoded signal. The subtraction circuit 23 outputs a residual excess component signal by subtracting the decoding result signal from the demodulated signal whose phase jitter has been canceled and is delayed through the delay circuit 25. Extract the residual phase jitter signal from the signal.

Further, the subtraction circuit 24 outputs an excess component signal by subtracting the decoding result signal from the signal delayed from the input demodulated signal via the delay circuit 26.
extracts the phase jitter from this signal and generates a signal of the extracted phase jitter.

Here, the delay circuits 25 and 26 are used to match the phase of the demodulated signal or its phase jitter-cancelled signal with the decoded signal by delaying it by the delay time in the decoder 22, that is, M symbols.

The jitter canceller 29 generates a phase jitter correction signal from the extracted phase jitter signal by being controlled by the residual phase jitter signal.

A configuration example of the jitter canceller 29 is shown in detail in FIG. In FIG. 6, the frequency sampling circuit 31 converts the extracted phase jitter signal of the phase error extraction circuit 28 into Fourier coefficients X6, Xl, X1+...-XI.
Convert to -1. On the other hand, the coefficient correction circuit 63 receives the signal of the residual phase jitter and outputs a complex coefficient H6+H1*Hl+... that minimizes its root mean square value.

Generates HN-1. Multiplier 32°, 321.321
+..., 32N-.

are the Fourier coefficients X6 + Xl + Xl, respectively,
... + XN 1, coefficient H6r Hl + H
The adder 34 generates and outputs a phase jitter correction signal by adding the outputs of the multipliers 32@, 321132, . . . , 32N-1.

The above coefficients Ho(t), Hs(A), · at time t
..., HN-! In order to minimize the root mean square value of the (t)1'' SS residual jitter, it can be determined by performing successive calculations using the following LMS (least mean square) algorithm.

Hz(A+1)=Hz(A)-β・Xi(t-M)
・s(t-M) ・= 11)e(A) = x
(t)-)'(t) Here, e(L): Residual phase jitter x(t): Extracted phase jitter y(t): Phase jitter correction signal M: Decoding delay β: Control coefficient for the received signal at time tT If the Fourier transform value of the phase jitter component actually included is 5x(t), then the value calculated by the frequency sampling circuit is ax(t-M
). However, since the phase jitter signal is considered to be a periodic waveform, from the time axis shift theorem in Fourier transform, 8x(t) = Sc(LM) -e=Xic(t)
, . It can be expressed as jmMT. Therefore, the phase difference caused by the decoding delay disappears by multiplying each 7-lier coefficient XK by e, returning to the original phase state. Further, by increasing the weighting of the frequency component of the phase jitter and decreasing the weighting of other Fourier coefficients, it is possible to reduce erroneous control due to noise and judgment errors.

In addition, as shown in FIG. 4, the frequency sampling circuit in this case is provided with a plurality of cyclic filters in parallel, and extracts the extracted phase jitter x(t) from each Fourier coefficient Xo (t
, (Figure 4(b)
) etc. can be used. Since these circuits are all well known, detailed explanation will be omitted.

FIG. 5 shows a specific example of the structure of the carrier jitter canceller of the present invention.

The input extracted phase jitter x(t-M) is a phase jitter component extracted from the decoding result and a value obtained by delaying the received signal by M symbols, which is the decoding delay in the decoder. The frequency sampling circuit 31 extracts phase jitter x (A-M
) as input, the 7-lier coefficient X6 r Xl +...
, Xl-1 (here, N is the number of points of the discrete Fourier transform DFT) and outputs it. Each Fourier coefficient X6 +
XI +...* XN-1 is each arithmetic circuit 36
゜.

361, .

For example, in the arithmetic circuit 36°, the 7-lier coefficient X0 is M
It is input to the shift register 37 of the stage to produce an output delayed by M symbols. On the other hand, residual phase jitter @(t-M)
is multiplied by the weighting coefficient β in the multiplication circuit 38, and then multiplied by the output signal of the shift register 37 in the multiplication circuit 38A. The multiplication result signal is sent to adders 39 and 1.
By sequentially updating the signal through a circuit including the symbol delay circuit 40, the calculation of equation (1) is performed to produce a complex coefficient H.

The multiplier coefficient HO is the Fourier coefficient X in the multiplication circuit 32°.
, is multiplied by

Arithmetic circuit 661. ..., 36) Similarly, in lt, the 7-lier coefficients X1+...+XH-1 and the complex coefficients H8,..., Ht.

are respectively multiplied by Each arithmetic circuit 360°36
Multipliers 32.m, . . . , 316M-t. ,3
2. ,-. 32. The signal of the multiplication result of −8 is sent to the adder circuit 3.
4 to produce a phase jitter correction signal y (t).

〔Effect of the invention〕

As described above, the carrier jitter canceller of the present invention can be applied to a carrier phase jitter control system that includes a delay in the jitter component extraction process of a decoder or the like and in the control loop of the jitter canceller.

Furthermore, since the optimal correction value is predicted in the frequency domain using Fourier transform, it is not necessary to use a bandpass filter for extracting the power frequency and its harmonic components in the previous stage, as in conventional carrier jitter cancellers. Therefore, when an IIR filter is used as such a filter, characteristic deterioration due to waveform distortion does not occur.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an example of the configuration of a carrier phase jitter control system according to the present invention, Fig. g3 is a diagram showing an embodiment of the present invention, and Fig. FIG. 5 is a diagram showing a specific configuration example of the carrier jitter canceller of the present invention, and FIGS. 6, 7, and 8 are diagrams showing a configuration example of a frequency sampling circuit, respectively. It is a figure showing an example of composition. 21.32°, 321, 32 9..., 32 □, 3
8.38A: Multiplication circuit 22: Decoder 23, 24': Subtraction circuit 25, 26.40: Delay circuit 27, 28 Two-phase error extraction circuit 29: Carrier jitter canceller 31: Frequency sampling circuit 33: Coefficient correction circuit 34. 39: Addition circuit

Claims (3)

[Claims] (1) The demodulated signal obtained by multiplying the input demodulated signal by the phase jitter correction signal is applied to the decoder and decoded to obtain a decoded signal, and the phase jitter is compensated for. A signal of residual phase jitter is extracted from the difference between a signal obtained by delaying the demodulated signal by the decoding delay time of the demodulator and the signal of the decoding result, and a signal obtained by delaying the input demodulated signal by the decoding delay time of the demodulator. carrier phase jitter control that generates an extracted phase jitter signal based on the difference between the residual phase jitter signal and the extracted phase jitter signal, and adds the residual phase jitter signal and the extracted phase jitter signal to a jitter canceller to generate the phase jitter correction signal. The jitter canceller of the system includes a Fourier coefficient generating means (101) that generates a group of Fourier coefficients by Fourier transforming the extracted phase jitter signal, and a coefficient correction unit that adaptively generates a complex coefficient group from the residual phase jitter signal. means (102), and a plurality of multipliers (10
3) and an adder (104) that adds the outputs of each multiplier (103).
), wherein the output of the adder (104) is used as the phase jitter correction signal. (2) The carrier jitter canceller according to claim 1, wherein the Fourier coefficient generating means (101) comprises a frequency sampling circuit. (3) The coefficient modification means (102) generates a complex coefficient group that is adaptively controlled so as to minimize the root mean square value of residual phase jitter. The carrier jitter canceller according to item 2.