KR100261180B1 - Carrier recovery circuit - Google Patents

Abstract

PURPOSE: A carrier recovery circuit is provided to improve the capacity for restoring a signal by compensating an error between a frequency and a phase according to a jitter generated from a transmission channel and the like. CONSTITUTION: A composite multiplication unit(31) receives composite input signals of the first receiving data received from the outside and the first image data received from a Hilbert transform. In addition, the composite multiplication unit(31) adds the signals and multiplies the signals. An equalization unit(32) receives an output of the composite multiplication unit(31) and corresponds the size and phase of a real signal with that of a virtual signal. A decision unit(33) receives the second receiving data and the second image data, and decides an input value as an approximate value. The first compensation unit(34) receives the second receiving data, the second image data, the third receiving data and the third image data. The second compensation unit(50) receives a phase error signal which is an output of the first compensation unit(34). A digital voltage control oscillation unit(36) receives a transmission channel error signal which is an output of the second compensation unit(50), and generates a clock to be outputted to the composite multiplication unit(31).

Description

Carrier Recovery Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit, and more particularly, to a carrier recovery circuit for improving signal recovery power.

The carrier recovery circuit according to the prior art inputs a complex input signal of first externally received data and first image data received from a Hilbert transform as shown in FIG. 1. A complex multiplier 11 for receiving and multiplying and adding the outputs; an equalizer 12 for matching the magnitude and phase of a real signal and a virtual image signal by receiving the output of the complex multiplier 11; and the equalizer 12 A decision unit 13 for receiving the second received data and the second image data, which are the outputs of the input signal, and determining the input value as a discrete specific value, that is, an approximate value. And a compensation unit 14 which receives the received data, the second image data, the third received data which is the output of the decision unit 13, and the third image data, detects phase errors of the input signals and compensates the phase errors. , The seventh product of the output of the compensation unit 14 Receiving input from the exchanger (15) consists of a digital voltage-controlled oscillator 16 that generates a clock to be output to the complex multiplier (11).

Here, the digital voltage controlled oscillator 16 receives the first adder 17, the delayer 18 receiving the output of the first adder 17, and the output of the delayer 18. And a sine / cosine calculator 19 for generating a clock to be output to the multiplier 11.

The complex multiplier 11 may include first and second multipliers 20 and 21 and the first image data and the sine / cosine calculator that multiply the output values of the first received data and the sine / cosine calculator 19. 19 and adds the output values of the third and fourth multipliers 22 and 23 and the first and third multipliers 20 and 22, and then outputs the resultant values to the equalizer 12. A second adder 24 for outputting, and a third adder 25 for adding the output values of the second and fourth multipliers 21 and 23 and outputting the result to the equalizer 12. .

The compensator 14 includes a fifth multiplier 26 for multiplying the second image data and the third received data, a sixth multiplier 27 for multiplying the second received data and the third image data, And a fourth adder 28 for adding the outputs of the fifth and sixth multipliers 26 and 27.

The operation description of the conventional carrier recovery circuit configured as described above is as follows.

In order to demodulate a passband signal in a coherent manner, a clock signal having the same frequency and phase as the carrier frequency of the received data should be used.

However, when the clock phase of the digital voltage control oscillator used during demodulation does not exactly match the phase of the received data, the original signal is rotated by the phase difference and restored.

Thus, in order to remove the phase difference, the second receiving data and the third receiving data are multiplied by the fifth multiplier 26 in the compensator 14, and the second image data and the third image data are multiplied by the second image data. After multiplication in the six multiplier 27, the outputs of the fifth multiplier 26 and the sixth multiplier 27 are added by the fourth adder 28 to generate a phase error signal.

In other words, the phase difference of two signals is calculated as the vector product as follows.

SIN (θ) = Im (second data × third data) / (| second data | × | third data |)

Here, the second data is second received data and second image data output from the equalizer 12, and the third data is third received data and third image data output from the decision unit 13. .

When θ is a value close to 0 in Equation 1 Sin (θ) ≒ θ Phase difference between the two signals Im (2nd data x 3rd data) / (| 2nd data | x | 3rd data |) This result is input to the digital voltage controlled oscillator 16 to compensate for the phase error.

As shown in FIG. 1, when the first reception data and the first image data are input to the complex multiplication unit 11, the clocks of the first reception data and the digital voltage controlled oscillator 16 are input to the first and second reception data. Multiply by the second multipliers 20 and 21, and multiply the input first image data and the clock of the digital voltage controlled oscillator 16 by the third and fourth multipliers 22 and 23.

The output of the first and third multipliers 20 and 22 is added by the second adder 24, and then input to the equalizer 12, and the second and fourth multipliers 21 and 23 are added. ) Is added by the third adder 25 and input to the equalizer 12.

The equalizer 12 then matches the magnitude and phase of the real and imaginary signals of the second adder 24 output value as the input signal or the real and imaginary signals of the third adder 25 output value.

The decision unit 13 receives the second received data and the second image data output from the equalizer 12, and determines the input value as a discrete specific value, that is, an approximate value.

Subsequently, the compensator 14 assumes that the second received data, the second image data and the originally transmitted signal, that is, the output of the equalizer, that is, the third received data and the third image, which are the outputs of the decision unit 13. The data is outputted to the digital voltage controlled oscillator 16 through the seventh multiplier 15 to output a phase error signal for compensating for an error due to a difference in carrier frequencies between signals.

The digital voltage controlled oscillator 16 receives the phase error signal, passes the input signal through the first adder 17, the delayer 18, and the sine / cosine calculator 19. Generates a clock to be output to).

However, the conventional carrier recovery circuit can compensate for the error of the frequency and phase difference caused by the carrier frequency difference between the signals, but there is a problem that the error of the frequency and phase difference due to jitter generated in the transmission channel cannot be compensated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a compensation unit for compensating for errors in frequency and phase difference caused by jitter or the like in a transmission channel. have.

1 is a block diagram illustrating a carrier recovery circuit according to the prior art.

2 is a block diagram illustrating a carrier recovery circuit according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

50: second compensator 51: seventh multiplier

52: Adaptive Phase Predictor 53: Fifth Adder

54: eighth multiplier 55: ninth multiplier

56: delay element 57: sixth adder

58: seventh adder 59: eighth adder

The carrier recovery circuit of the present invention receives the received data and the image data through a complex multiplication unit, an equalization unit for matching the magnitude and phase of each real signal and the virtual image signal, and receives the output of the equalization unit to determine a discrete specific value. A first compensator for detecting the error of the input signals by receiving the output of the decision unit, the equalizer and the decision unit and compensating the error, and receiving a phase error signal that is an output of the first compensator is generated in the transmission channel. And a digital voltage control oscillator for receiving a transmission channel error signal that is an output of the second compensation unit and generating a clock to be output to the complex multiplication unit.

A preferred embodiment of the carrier recovery circuit according to the present invention as described above will be described in detail with reference to the accompanying drawings.

In the carrier recovery circuit according to the embodiment of the present invention, as shown in FIG. 2, a multiplier unit for receiving and multiplying and adding a composite input signal of first received data received externally and first image data received from a Hilbert transformer (31), an equalizer 32 for receiving the output of the complex multiplier 31 and matching the magnitude and phase of a real signal and a virtual image signal, and second received data and second output of the equalizer 32; A decision unit 33 which receives image data and determines its input value as a discrete specific value, that is, an approximate value, second received data which is an output of the equalizer 32, second image data and decision unit 33 A third compensator 34 which receives the third received data and the third image data that are outputs of the first signal, and detects phase errors of the input signals and compensates the phase errors, and a phase which is an output of the first compensator 34. Input error signal to transmission channel A second compensation unit 50 for compensating for errors caused by jitter and the like, and a transmission channel error signal output from the second compensation unit 50 are input to generate a clock to be output to the multiplication unit 31. The digital voltage controlled oscillator 36 is configured.

Here, the digital voltage controlled oscillator 36 may include a delay unit 38 that receives the output of the first adder 37, the first adder 37, and a sine / receiver that receives the output of the delay unit 38. It consists of a cosine calculator 39.

The complex multiplier 31 may include first and second multipliers 40 and 41 and the first image data and the sine / cosine calculator that multiply the output values of the first received data and the sine / cosine calculator 39. 39, the output values of the third and fourth multipliers 42 and 43 and the first and third multipliers 40 and 42 that multiply the output values are added to the equalizer 32. A second adder 44 for outputting, and a third adder 45 for adding the output values of the second and fourth multipliers 41 and 43 and outputting the result values to the equalizer 32. .

In addition, the first compensator 34 may include a fifth multiplier 46 for multiplying the second image data and the third received data, and a sixth multiplier 47 for multiplying the second received data and the third image data. And a fourth adder 48 for adding the outputs of the fifth and sixth multipliers 46 and 47.

The second compensator 50 receives a result of the seventh multiplier 51 and the seventh multiplier 51 which multiply the phase error signal and the jitter constant, and compensates for the frequency and phase difference caused by jitter. An adaptive phase predictor 52 for outputting a predictive value, a fifth adder 53 for adding the phase error signal and the adaptive phase predictor 52, the fifth adder 53 and a first gain constant The output of the eighth multiplier 54, multiplying the fifth adder 53 and the second gain constant, the ninth multiplier 55, and the ninth multiplier 55 to receive the output to the delay element (56) A sixth filter configured to correct an error signal having a relatively high frequency component, and add an output value of the ninth multiplier 55 and the filter, and output the resultant value to the filter. A seventh adder for adding an adder 57, an eighth multiplier 54, and an output value of the filter; (58), and an eighth adder (59) for adding the output values of the seventh adder (58) and the adaptive phase director (52) and outputting the result values to the digital voltage controlled oscillator (36). .

Here, the adaptive phase director 52 is composed of a finite impulse response (FIR) filter.

The operation description of the carrier recovery circuit according to the embodiment of the present invention configured as described above is as follows.

In order to demodulate the passband signal in a coherent manner, a clock signal having the same frequency and phase as the carrier frequency of the received data should be used.

However, when the clock phase of the digital voltage controlled oscillator 36 used during demodulation does not exactly match the phase of the received data, the original signal is rotated and restored by the phase difference.

Thus, the second compensation unit 34 multiplies the second received data and the third received data by the fifth multiplier 46 to remove the phase difference, and the second image data and the third image data are multiplied. After the multiplication is performed by the sixth multiplier 47, the outputs of the fifth multiplier 46 and the sixth multiplier 47 are added by the fourth adder 48 to generate a phase error signal.

In addition, after the error caused by jitter or the like generated in the transmission channel is multiplied by the seventh multiplier 51 by the phase error signal, which is the output of the first compensation unit 34, and the jitter constant by the second compensation unit 50, It outputs to the digital voltage controlled oscillator 36 through the adaptive phase precipitator 52 to correct jitter generated by the transmission channel, and feeds back the output of the adaptive phase predator 52. By adding the phase error signal and the fifth adder 53 again, the jitter error is compensated overall, and the jitter constant and the first and second gain constants are adjusted according to the size of the jitter to remove the jitter. To compensate.

As shown in FIG. 2, when the first reception data and the first image data are input to the complex multiplication unit 31, the clocks of the first reception data and the digital voltage control oscillator 36 are input to the first and second reception data. The second multipliers 40 and 41 multiply and multiply the input first image data and the clock of the digital voltage controlled oscillator 36 by the third and fourth multipliers 42 and 43.

In addition, the output of the first and third multipliers 40 and 42 is added by the second adder 44, and then input to the equalizer 32, and the second and fourth multipliers 41 and 43. ) Is added by the third adder 45 and input to the equalizer 32.

Subsequently, the equalizer 32 matches the magnitude and phase of the real signal and the imaginary signal of the output value of the second adder 44 as the input signal or the imaginary signal and the imaginary signal of the output value of the third adder 45.

The decision unit 33 receives the second received data and the second image data output from the equalizer 32, and determines the input value as a discrete specific value, that is, an approximate value.

Subsequently, the first compensation section 34 assumes that the second reception data, the second image data and the signal originally transmitted, that is, the output of the equalization section, that is, the third reception data and the output of the decision section 33. 3, the image data is input to the second compensator 50 to output a phase error signal for compensating for an error due to a difference in carrier frequencies between signals.

The second compensator 50 receives the phase error signal and outputs an output signal to the digital voltage controlled oscillator 36 to compensate for errors caused by jitter in the transmission channel.

The digital voltage controlled oscillator 36 receives the phase error signal and passes the input signal through the first adder 37, the delayer 38, and the sine / cosine calculator 39. Generates a clock to be output to).

In the carrier recovery circuit of the present invention, the second error compensator generates a phase error signal, which is an output of the first compensator, and a jitter constant by a seventh multiplier, and then outputs the digital voltage control oscillator through an adaptive phase precipitator. This function compensates the jitter, and adds the phase error signal and the fifth adder by feeding back the output of the adaptive phase predictor to compensate for the jitter error as a whole. Also, the jitter constant and the first, Since the jitter is removed by adjusting the second gain constant, an error in frequency and phase difference caused by jitter or the like occurring in the transmission channel is compensated for, thereby improving signal resilience.

Claims (3)

An equalizer which receives the received data and the image data through the complex multiplication unit and matches the magnitude and phase of each real signal and the virtual image signal; A decision unit which receives the output of the equalizer and determines the discrete value; A first compensator configured to receive outputs of the equalizer and the decision unit, detect an error of the input signals, and compensate for the error; A second compensator for receiving a phase error signal that is an output of the first compensator and compensating for an error occurring in a transmission channel; And a digital voltage controlled oscillator for receiving a transmission channel error signal that is an output of the second compensator and generating a clock to be output to the complex multiplier. The method of claim 1, The second compensator is configured to compensate for a frequency and phase difference due to jitter by receiving a result of the first multiplier and the first multiplier that multiply the jitter constant and the first and second gain parts and the phase error signal and the jitter constant. An adaptive phase dictator that outputs a predicted value for the first quantizer; A third multiplier multiplying a gain constant, a high pass filter configured to receive an output of the third multiplier and comprising a delay element to correct an error signal having a relatively high frequency component, and add an output value of the third multiplier and the filter A second adder for outputting the resultant value to the filter, a third adder for adding output values of the second multiplier and the filter, and a third adder The result by the addition output value of the phase peurek dikteo carrier recovery circuit, characterized by consisting of a fourth adder for outputting the digital voltage-controlled oscillation unit. The method of claim 2, And said adaptive phase predictor is comprised of an FIR filter.