JPS63224515A - Phase comparating circuit - Google Patents

Abstract

PURPOSE:To attain the phase comparison even with an input signal having only one set of edge information by adopting the constitution such that the phase of the input signal and that of the clock are compared by an FF and two latch circuits. CONSTITUTION:An output edge data signal of an AND gate 1 is inputted to an FF 2, which is set at its leading edge. The output of the FF 2 is inputted to a data terminal of an FF 3, which latches the data at the leading edge of the clock. A terminal, Q of the FF 3 is connected to a reset terminal of the FF 2, which outputs the edge data and a pulse having a width corresponding to the time difference information of the clock. The output of the FF 3 is inputted to a buffer 6 and also inputted to an FF 4. Since the inverted clock is inputted to the clock terminal of the FF 4, the FF 4 latches the input at the other edge of the clock. Thus, since an AND gate 5 outputs the pulse corresponding to the width of the clock to a buffer 7, the buffer 7 outputs a signal opposite in polarity to that of the buffer 6 to enable the phase comparison of the signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparator circuit suitable for use in a PLL circuit for extracting a clock in, for example, an optical disk device.

[Summary of the invention]

In the present invention, phase comparison between an input signal and a clock is performed using a flip-flop and two latch circuits.

(Prior art) Fig. 5 shows a servo byte pattern of sample servo in an optical disk device. Each sector of an optical disk consists of 43 servo blocks, and one servo block consists of 2 servo bytes followed by 16 bytes. The servo byte consists of two wobbled bits and one clock bit, and the wobbled bits are arranged on the left and right sides of the track center.

When the pickup (light spot for information detection) traces the track center, the amount of decrease in light intensity on the left and right wobbled bits becomes equal, and when the tracing position shifts left and right, the two The amount of decrease in light intensity in the wobbled bit changes. Therefore, a tracking error signal is generated from the difference in drop it (RF signal level difference) at two positions, and this tracking error signal is held for the duration of the following data byte. Also, the two wobbled bits are longer every 16 tracks. By detecting changes in this interval, the number of tracks can be accurately counted even during high-speed searches (16 track counting).
It is now possible to do so.

The distance between the wobbled pit and the clock pit located further back is set to a special length that does not appear in the data byte. Therefore, this distance can be detected as a synchronization signal. Various timing signals are generated based on the detected synchronization signal. A clock is generated in response to a clock pit detection signal. The mirror surface at a distance is used as a focus area, where a focus error signal is detected and held for the following data byte.

[Problem that the invention seeks to solve]

For example, when a 5-inch DRAW disk on which such servo bytes are recorded is rotated at 180 rpm,
Clock pit edge information is 41゜28K XIz
is detected at a repetition frequency of However, since this signal has only one edge information, it is not possible to perform a phase comparison with a reference signal as with a normal continuous signal or a burst signal that continues for a predetermined period of time.

Therefore, the present invention is designed to perform phase comparison of signals having only one edge information.

[Means for solving problems]

The present invention provides a phase comparator circuit that includes a flip-flop set by an input signal and a first flip-flop that latches the output of the flip-flop at the timing of one edge of a clock.
a latch circuit, a second latch circuit that latches the output of the first latch circuit at the timing of the other edge of the clock, and a flip-flop and the output of the first latch circuit to obtain time difference information between the input signal and the clock. A first generation circuit that generates a corresponding first pulse, a first latch circuit, and a second latch circuit generate a second pulse corresponding to the width of one edge and the other edge of the clock. It is characterized by comprising a second generation circuit that generates.

[Effect]

An input signal sets a flip-flop, and the output of the flip-flop is latched into a first latch circuit at the timing of one edge of the clock. The output of the first latch circuit is synchronized with the second latch circuit at the timing of the other edge of the clock.
is latched into the latch circuit. The first generation circuit generates a first pulse corresponding to time difference information between the input signal and the clock from the output of the flip-flop and the output of the first latch circuit. The second generation circuit generates a second pulse corresponding to the width of one edge and the other edge of the clock from the output of the first latch circuit and the output of the second latch circuit.

〔Example〕

FIG. 1 is a block diagram of a phase comparator circuit according to the present invention. When the spot light traces the vicinity of the clock pit in the servo byte section, the RF multiplied signal waveform becomes as shown in FIG. 2(a). In other words, the amount of light reflected from the disk decreases in a clock pit portion or a portion where there are scratches, dust, etc., and the RF multiplied signal level corresponding to the amount of received light decreases. When this RF multiplied signal is differentiated by a circuit (not shown) and its edge information is detected, an edge data signal (input signal) shown in FIG. 4(b) is obtained. Furthermore, as described above, the timing signal generation circuit (not shown) generates a gate signal (not shown) that gates the edge data signal based on the detected synchronization signal.
FIG. 2(C)) is generated. Since this edge data signal and gate signal are input to AND gate 1, AND gate 1 does not output pulses due to dust, scratches, etc., and outputs only edge data signals (41, 28 KHz) (
Figure 2(d)).

The output of AND gate 1 is input to R-S flip-flop 2, and flip-flop 2 is set at its rising edge (Fig. 2(e)). input to the data terminal of step 3.

Since a clock (for example, 11.1456 MHz) as a reference signal to be compared is input to the clock terminal, the flip-flop 3 latches the data at the data terminal at the timing of the rising edge of the clock (see Fig. 2 (f)). ), (i)), the output Q terminal of the flip-flop 3 is connected to the reset terminal of the flip-flop 2, forming a generation circuit. Therefore, since it is reset by the falling edge of the output of the flip-flop 3 (FIG. 2(f)), the flip-flop 2 generates a pulse (
Figure 2(e)) is output.

When a high-level signal (enable signal) is input from the flip-flop 2, the 3-state buffer 6 becomes enabled and outputs a low-level signal (Fig. 2 (1)). This signal is connected to the resistor R. is converted into a current, and a current I□ of one polarity flows. This current Ii is output to a low-pass filter (not shown) forming part of a PLL circuit that generates a clock. When a low level signal is input from the flip-flop 2, the buffer 6 is in an open state.

The output Q of the flip-flop 3 (FIG. 2(i)) is input to the data terminal of a delay type flip-flop 4 as a latch circuit. Since a clock whose phase is inverted (Fig. 2 (h)) is input to the clock terminal, the flip-flop 4 latches the output Q of the flip-flop 3 at the timing of the other edge of the clock (Fig. 2 (h)). (j)), the output Q of the flip-flop 3 and the output Q of the flip-flop 4 are connected to an AND gate 5 as a generation circuit.
, the AND gate 5 outputs a pulse (second pulse) corresponding to the width of one edge and the other edge of the clock.
Figure (k)) is output.

The three-state buffer 7 is enabled when a high-level signal (enable signal) is input from the AND gate 5, and outputs a signal (high-level signal) with the opposite polarity to that of the buffer 6 (Fig. 2). (m)). This signal is converted into a current by a resistor R, and a current with a polarity opposite to that in the above case flows. This current I2 is also output to a low-pass filter (not shown).

The output of the flip-flop 2 corresponds to the time difference between the edge of the clock data and the edge of the clock, and the output of the AND gate 5 corresponds to 172 cycles (width between one edge and the other edge) of the clock. It is possible to output only the output of flip-flop 2 as the phase comparison result, but by outputting the difference between the output of flip-flop 2 and the output of AND gate 5 via a low-pass filter, it is possible to output the edge (clock data). It is possible to obtain a phase comparison result that does not depend on the repetition period. Therefore, even if the rotational speed of the disk changes, it is possible to prevent the phase comparison result from changing. It is also possible to perform phase comparison of signals with varying edge spacing.

Also, since only one edge is used as phase comparison information,
Even if the pulse width changes as shown by the broken line in FIG. 2(b), this does not change the comparison results.

Furthermore, since the buffer 6.7 is enabled only during the sampling period and is open during the other periods, the so-called sample-and-hold operation in which the result of phase comparison during the sampling (enable) period is held during the other (open) period is performed during phase comparison. It can be done in the circuit itself.

FIG. 3 is a block diagram of another embodiment, and FIG. 4 is a timing chart thereof (corresponding parts to those in FIGS. 1 and 2 are given the same reference numerals). In the embodiment, the flip-flop 2 is reset by the output Q of the flip-flop 4 ((0) in FIG. 4), and the output of the flip-flop 2 and the output 0 of the flip-flop 3 are input to an AND gate 11 as a generation circuit. Then, a time difference information signal (FIG. 4(n)) is generated and output.

In the embodiment of FIG. 1, the minimum time difference between the signals output by flip-flop 2 is the data set up time of flip-flop 2 and the delay time from the clock input of flip-flop 3 until output 0 is generated. , is regulated by the sum of the time from the reset input of the flip-flop 2 until the output Q is inverted. In contrast, in the case of the embodiment shown in FIG. 3, the data set up time of flip-flop 2 and the output Q from the clock input of flip-flop 3 are
It is regulated to the value obtained by adding the delay time until it is issued. Therefore, the embodiment of FIG. 3 is faster.

In the above case, the output circuit includes a 3-state buffer 6.
7 is used, but it is also possible to switch the current source so that the current is output only during the period when the phase comparison output is sent out.

〔effect〕

As described above, the present invention uses a flip-flop set by an input signal in a phase comparator circuit.

a first latch circuit that latches the output of the flip-flop at the timing of one edge of the clock; a second latch circuit that latches the output of the first latch circuit at the timing of the other edge of the clock; A first generation circuit generates a first pulse corresponding to the time difference information between the input signal and the clock from the output of the first latch circuit, and a clock pulse from the output of the first latch circuit and the second latch circuit. Since the second generation circuit generates a second pulse corresponding to the width of one edge and the other edge, phase comparison can be performed even with an input signal having only one edge information.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the phase comparison circuit of the present invention, Fig. 2 is its timing chart, Fig. 3 is a block diagram of another embodiment, Fig. 4 is its timing chart, and Fig. 5 is its servo byte pattern. FIG. 1...AND gate 2...R-S flip-flop 3.4...Delay type flip-flop 5...And gate 6.7°00 buffer 11...And gate or more

Claims (1)

[Claims] A flip-flop that is set by an input signal, a first latch circuit that latches the output of the flip-flop at the timing of one edge of the clock, and an output of the first latch circuit that latches the output of the flip-flop at the timing of the other edge of the clock. a second latch circuit that latches the input signal, and a first generation circuit that generates a first pulse corresponding to time difference information between the input signal and the clock from the outputs of the flip-flop and the first latch circuit; A second generating circuit that generates a second pulse corresponding to the width of one edge and the other edge of the clock from the outputs of the first latch circuit and the second latch circuit. Phase comparator circuit.