JPS63223948A - Inter-processor communication method in multiprocessor os - Google Patents

Abstract

PURPOSE:To remarkably improve processing speed by adding an FIFO type buffer to each processor connected in a ring shape or in a pipeline shape, and executing a data communication between each processor through the buffer. CONSTITUTION:For instance, a case that a data on a peripheral equipment 5 (disk) is outputted to a peripheral equipment 4 (printer) is considered. A master processor 1-1 divides its processing into a processing for reading out the data from the disk, and a processing for outputting the data to the printer. Subsequently, the processor sends the message requesting the processing to a slave processor 1-2 and 1-3, respectively. When the message is sent, it is stored in a buffer, therefore, the processor 1-1 can shift to the execution of a next processing. The processors 1-2, 1-3 fetch the message stored in the buffer, interpret its contents and read out the data from the disk, and outputs the data to the printer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an inter-processor communication method in a multiprocessor OS (operating system).

(Prior Art) An OS provides a working environment to a computer system, and various methods have been proposed for efficiently running this OS.

One conventional method is to separate relatively time-consuming processing for peripheral devices such as printers, disk drives, tape drives, or keyboards from the main processor, and have dedicated processors handle the processing in parallel. There is something.

However, as described above, these conventional proposals merely distribute processing for each peripheral device to dedicated processors, but do not distribute the OS itself to perform parallel processing. Therefore, it cannot contribute to shortening the processing time when one system is used by a plurality of users.

In other words, conventional OSes use T8S (time sharing system)1 to divide time and switch processes at high speed to achieve apparent parallel processing. When the processing time increases, the processing time of a single processor itself remains unchanged, so the processing time of the entire OS decreases as the overhead of processing switching time increases.

(Object of the invention) The present invention has been made in view of the above-mentioned circumstances, and includes:
It is an object of the present invention to provide an inter-processor communication method in a multiprocessor OS that makes it possible to implement the OS itself extremely efficiently.

(Summary of the Invention) In order to achieve this object, the present invention adds a FIFO type buffer to each processor of a computer system in which processors having two or more pairs of input/output channels are connected in a ring or pipeline configuration. The processors are configured to perform data communication between the processors via the processor.

(Example) The present invention will be described in detail below based on the illustrated example.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the same figure, 1-1.1-2. ......, 1-n is a processor unit, 2-1, 2-2, -, 2
-n is a FIFO type buffer, and every other buffer is connected in a ring shape.

Further, a dedicated memory is added to each processor unit, and one of the processor units, for example 1-1
The master processor is connected to the slave processor unit, and the master processor unit 1-1 is connected to the pass line aK.

Further, the pass line includes, for example, a printer 4. Disc 5.
Peripheral devices such as..., etc. are connected.

The master processor collectively controls all slave processors and peripheral devices connected to the pass line.

Mask (slave) processor Data exchange between slave processors is performed using a message communication method through a communication channel.

The master processor and each slave processor store all processing in inter-processor communication in the form of messages, and when a message is sent from the other party, they interpret and execute it and process it to the other party. When making a request, send the contents as a message to the other party.

A simple example of message communication is shown. Now consider the case where data on peripheral device 5 (disk) is output to peripheral device 4 (printer).

The master processor 1-1 divides this process into the process of reading data from the disk and the process of outputting data to the printer, and separates this process into the process of reading data from the disk and the process of outputting data to the printer.
-2 and the slave processor 1-3 to request processing. Here, for the sake of simplicity, it is assumed that slave processors 1-2 and 1-3 are in an idle state (waiting for a processing request). When the master processor sends a message, it is stored in a buffer, so it can immediately move on to the next process. The slave processor reads the message stored in the buffer, interprets the contents, reads the data from the disk, and sends the data to the slave processor 1-3. Slave processor 1-3 receives and receives data from slave processor 1-2 and outputs the data to the printer.

Next, details of message communication will be described.

FIG. 2 is a block diagram showing one embodiment of a processor and a buffer used in the present invention. There are two types of channels between each processor: an output communication channel and an input communication channel.

Therefore, there are two types of buffers: an output channel buffer and an input channel buffer. In the same figure, ......, 2, -1, 2,
・・・・・・ is the output channel buffer, ・・・・・・
3-1, 3, . . . are input channel buffers.

FIG. 3 is a structural diagram of a channel buffer.

The structure of the buffer is the same for both output and input, FI
It takes the form of FO.

The unit of access to this buffer is a packet. A packet is a representation of a message in a form that each processor can interpret.

FIG. 4 is a diagram showing the structure of a packet. A packet is composed of five elements as shown in the figure.

i is the content of the message (processing content) ii is the message sender (processing requester) i is the message receiver (processing executor) God is the type of data received by the message receiver V is the message reception A person receives data or a pointer to data.Here, does V represent the data itself?

Determines whether it represents a pointer to data. 1 Parallel processing by normal multiprocessors In 1, the data exchanged by one process (unit processing) is often a few words to a few words long compared to the word length of the processor.
One packet has this number of words reserved in advance for data. In this case, the type of data indicates that V is the data itself. (Packet 1 in the same figure
-1) On the other hand, data 'v+ that exceeds the amount secured by the packet
If b*b, God indicates that V is a pointer to data. (Packet in the figure) In this case, the actual data is usually in the message sender's private memory.The pointer indicates the start address of the sender's private memory where the data exists and the number of data.

Here, a specific example of communication will be shown.

■ Simple example situation: When a certain processor S requests the execution of an adjacent processor RK process, and the requested processor R is idle. FIG. 5 shows the above situation.

The behavior of processor S and processor R under this situation is shown below.

S is the packet i K #'i The message ii that S sends to R is S iK is R -, data type V is filled with data (or a pointer to the data), and this packet is loaded into OCR. At this point, 8 is released from this process and can move on to executing the primary process.

R periodically reads the contents of the message stored in the first packet stored in the OCR and executes the specified process.

Packet i has R sending message ii to S. iK is S God has data types V contains data (or a point to the data) Inter) and load this packet onto the ICB.

S periodically reads the packet v stored at the beginning of the ICB. Check whether the content corresponds to the content of the packet stored at the beginning of the OCR, and if it does, temporarily suspend the execution of the process that was running up until then and stop receiving the data of the ICB packet. Torifi, OCR
, ICB packets are shifted and updated one by one. The suspended process then resumes execution.

■ Complex example situation: A certain processor S requests an adjacent processor B to execute a process.

Processor B is running another process and is not available, and requests the idle processor RICB, which is adjacent to processor B, to execute the process.

FIG. 6 shows the above situation.

The behavior of processor S, processor B, and processor 2 under this situation is shown below.

S is the message that S sends to B in packet i, iiK' is 5, iiK is B, data type V is data (!! or a pointer to data), and this is loaded in 0CB1, S is released from this process at this point and moves on to execution of the primary process.

B goes to read the first packet stored in the periodic KOCBI. At this time, the running process is temporarily suspended.

B then learns that the message has been delivered to him, but since he is running another process, he asks 9 to run the process in place of R, who is playing next to him. Namely.

Message S sends RK to packet i ffc
is S i is R data type vK is data (t or a pointer to data), and this is loaded in 0CR2, and Fm v! of the packet loaded ahead of KOCBI. ! : Changed from B to R.

Resume a suspended process.

R periodically reads the contents of the message stored in the first packet stored in 0CB2, and the people it is playing with execute the specified process.

Packet i has R sending message ii to S. 5 for i ivK is data type V contains data (or a point to the data) Inter) and load it into ICB2.

B periodically reads the packet stored at the beginning of ICB2. Check whether the content corresponds to the content of the first Kff packet of 0CB2, and if it does, temporarily suspend the execution of the currently running process,
It receives the data of the packet in ICB2 and returns i of the first packet loaded in 0CB1 from R to B. Copy the KICB2 packet data again.

Load ICBIK, i.e. packet i, message sent by FiB to 8, ii to B, S to data type V, and load data (or pointer to data) to ICBI.Second, 0CB2, ICB2 The packets are shifted and updated one by one, and execution of the temporarily suspended process is resumed.

Below, we will use the same method as above for more complex cases.
It would be a good idea to find an idle processor and execute the process.

Note that the process in which each processor refers to the contents of the channel buffer is performed with priority over any other process.

Note that in the embodiments described above, a case where a plurality of processor units are connected in a ring shape is illustrated, but in carrying out the present invention, it is not necessarily limited to this, and each element described above is connected not in a ring shape, but It may be connected only in one direction.

In this case, control can be simplified because the positional relationship of the slave processors can be uniquely determined.

Furthermore, using the system of the present invention, one job (Job)
If the processing of each stage of is performed in parallel and distributed.

It can perform the same function as the pipeline method.

Further, by combining the present invention with the conventional pipeline system in various ways, it is possible to take advantage of the advantages of both methods and process multiple jobs more efficiently.

(Effects of the Invention) As explained above, the present invention is configured so that the OS processing itself is distributed and processed by multiple processor units, so the processing speed of the combinator system is significantly improved compared to the conventional TSS method. can do.

In particular, when a plurality of jobs are executed simultaneously, since they can be processed in parallel, much faster processing is possible than in the conventional TSS method, and the effect is remarkable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a partial block diagram explaining the operation of FIG. 1, and FIG. 3 is an embodiment of a FIFO type buffer used in the present invention. diagram showing,
FIG. 4 is a diagram showing an example of the contents of the FIFO type buffer shown in FIG. 3, and FIGS. 5 and 6 are partial configuration diagrams illustrating the specific operation of the system shown in FIG. 1. 1-1 to 1-n...Proset unit. 2-1 to 2-n...Buffer. Patent Applicant Toyo Tsushinki Co., Ltd. Zero Z Figure n AFIFO 8', to 7° 3 From the figure M ÷ Soluba) No. 51! ] zg sword

Claims (1)

[Scope of Claims] In a computer system in which processors having one, two or more pairs of input and output channels are connected in a ring or pipeline, FIFO type buffers are arranged at all or required positions between the respective processors. An inter-processor communication method in a multiprocessor OS, characterized in that data communication is performed between each processor via the buffer. 2. The method according to claim 1, characterized in that one of the processors is defined as a master processor and the others are defined as slave processors, and processing is distributed from the master processor to the slave processors to execute them. A communication method between processors in a multiprocessor OS. 3. The multiprocessor OS according to claim 1 or 2, wherein when the processors are connected in a ring, a processor that is not currently processing is selected as the processor to which processing is assigned. Inter-processor communication method in . 4. Each of the processors is provided with a memory, and the data being processed is saved in the memory at predetermined intervals. During this time, it is detected whether or not data is transferred from another processor, and the data transferred is detected. 4. An inter-processor communication method in a multiprocessor OS according to claim 1, characterized in that, if there is one, the received one is given priority and required processing is performed.