JPS63222372A - Pulse shaping circuit - Google Patents

Abstract

PURPOSE:To reproduce correct digital data by operating exclusive OR between data, which is generated by slicing read data and is not delayed, and data which is generated similarly and is delayed and latching delayed data synchronously with the output of this OR. CONSTITUTION:When a clock signal is supplied to a clock input terminal 17 and digital data including glitch in the polarity inversion part is generated from a comparator 12, D-FF circuits 15 and 16 latch data by the rise of the clock signal, and delayed data is outputted from an output terminal Q of the circuit 16. Output data of the circuit 16 is latched synchronously with the rise of output data from an EXOR circuit 8 by a D-FF circuit 19. Therefore, the polarity inversion point of time of output data of the circuit 19 is synchronized with the first polarity variance of glitch of data outputted from the comparator 12, and digital data where glitch is removed is supplied to a demodulating reproducing system through an output terminal 10. Thus, correct data is reproduced with simple constitution.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is directed to data obtained by slicing data read from a dynamic recording medium such as a tape or a disk at a predetermined slice level. This invention relates to a pulse shaping circuit that shapes digital data.

(Prior Art) As is well known, in a digital playback device such as a digital audio recorder or a compact disc player, data read from a dynamic recording medium such as a tape or a disk is sliced at a predetermined slice level. By doing so, it is converted into pulse-like digital data.

FIG. 3 shows a data slice circuit used in this type of digital playback device.

That is, data read from the dynamic recording medium is supplied to one input end of the comparator 12 via the input terminal 11. At the other input terminal of this comparator 12,
The slice level output from the slice level control circuit 13 is supplied.

The comparator 12 compares the data and the slice level, and generates an H (high) level signal when the data level is higher than the slice level, and a low (low) level signal when the data level is higher than the slice level. Pulse-like digital data can be obtained. Note that the digital data output from the comparator 12 is supplied to a slice level control circuit 13, and the slice level is controlled according to, for example, the duty ratio of the digital data.

However, in the case of an actual circuit, the data supplied to the input terminal it contains many noise components, as shown in FIG. The data includes the same figure (b)
As shown in FIG. 2, a problem arises in that glitches occur in the polarity inversion portion.

Here, glitch prevention means using, for example, a hysteresis circuit have been generally considered, but in the case of a digital playback device, the digital data output from the data slice circuit contains information at the edges, that is, when the polarity is reversed. It is designed to determine the meaning of the glitch, and conventional glitch prevention means are not suitable for such digital data.

(Problems to be Solved by the Invention) As described above, the digital data output from the data slice circuit in a digital playback device includes glitches in the polarity inversion portion. A problem has arisen in that general glitch prevention means such as conventional hysteresis circuits cannot be applied.

Therefore, this invention was made in consideration of the above circumstances, and it is possible to remove glitches with a simple configuration, and it is possible to accurately determine the meaning of information held at the point of polarity reversal of digital data, and to make it possible to accurately determine the meaning of information at the time of polarity reversal of digital data. It is an object of the present invention to provide an extremely good pulse shaping circuit that can reproduce digital data.

[Structure of the Invention] (Means for Solving the Problems) That is, the pulse shaping circuit according to the present invention processes pulse-shaped digital data generated by slicing data read from a dynamic recording medium at a predetermined slice level. Data is delayed by a predetermined amount in synchronization with a clock signal of a constant period, the exclusive OR of the digital data before the delay and the digital data after the delay is performed, and the digital data after the delay is synchronized with the OR output. It is designed to latch.

(Function) According to the above configuration, the delayed digital data is latched in synchronization with the exclusive OR output of the digital data before and after the delay, so that the latched digital data Since the polarity reversal point of the digital It is possible to accurately determine the meaning of information at the time of polarity reversal of data, and it is possible to reproduce correct digital data.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as in FIG. 3 are indicated by the same symbols, and only the different parts will be described here. That is, the output terminal of the comparator 12 is
It is connected to the input end of a D-type flip-flop circuit (hereinafter referred to as D-FF circuit) 15. The output terminal Q of this D-FF circuit 15 is connected to the input terminal of another D-FF circuit IB.

The clock input terminals C of the D-FF circuits is and 1B are both connected to a clock input terminal 17 to which a clock signal of a constant period is supplied. For example, in the case of a compact disc player, the clock signal supplied to the clock input terminal 17 is a PLL (phase locked loop) used to separate bits from digital data.
A read clock PLCK is used which is generated in the circuit in phase synchronization with the digital data.

The input end of the D-FF circuit 15 and the output end Q of the D-FF circuit 16 are connected to both input ends of a two-man exclusive OR circuit (hereinafter referred to as EX-OR circuit) 18. There is. Further, the output terminal Q of the D-FF circuit 16 is connected to the input terminal of the D-FF circuit 19, and the output terminal of the EX-OR circuit 18 is connected to the clock input terminal C of the D-FF circuit 19. has been done. And this D-F
The inverted output terminal Φ of the F circuit 19 is connected to the output terminal 20 via the output terminal 20.
It is connected to a digital data demodulation/reproduction system (not shown).

The operation of the above configuration will be described below with reference to the timing diagram shown in FIG.

That is, the clock signal shown in FIG. 2(a) is supplied to the clock input terminal 17, and the comparator 12
Assume that digital data including a glitch in the polarity inversion portion is generated as shown in FIG. 2B.

Then, since the D-FF circuits 15 and 16 each latch the data at the input end at the rising edge of the clock signal, the data shown in FIG. 2(C) is output from the output end Q of the D-FF circuit 16. Output. Therefore, EX-OR circuit 1
Data shown in FIG. 2(d) is output from B.

Then, by the D-FF circuit 19, the EX-OR circuit 1
In synchronization with the rise of the output data of 8, D-FF circuit 1
G output data is latched. Therefore, as shown in FIG. 2(e), the polarity inversion point of the digital data output from the inversion output end of the D-FF circuit 19 corresponds to each polarity inversion portion of the digital data output from the comparator 12. The signal is synchronized with the maximum polarity variation of the generated glitch, and digital data from which the glitch has been removed is supplied to the demodulation/reproduction system via the output terminal 20.

Therefore, according to the configuration of the above embodiment, three D-FF circuits 15. Glitches in digital data can be removed with a simple configuration that uses lfi, '19 and the EX-OR circuit 18. Therefore, the demodulation/reproduction system described above can accurately determine the meaning of the information at the time of polarity reversal of digital data, and can reproduce correct digital data.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as detailed above, according to the present invention, glitches can be removed with a simple configuration, and the meaning of information held at the point of polarity reversal of digital data can be accurately determined. Therefore, it is possible to provide an extremely good pulse shaping circuit that can reproduce correct digital data.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a pulse shaping circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of the same embodiment, and FIG. 3 is a block diagram showing the configuration of a data slicing circuit. The configuration diagram and FIG. 4 are timing diagrams for explaining the conventional problems. 11...Input terminal, I2...Comparator, 13.
...Slice level control circuit, 14...Output terminal, 1
5.18...D-FF circuit, 17...Clock input terminal, 18...EX-OR circuit, 19...D-FF
Circuit, 20...output terminal.

Claims (1)

[Claims] A data generation means for slicing data read from a dynamic recording medium at a predetermined slice level to generate pulse-like digital data, and a data generation means for synchronizing the digital data output from the data generation means with a clock signal of a constant period. a delay means for delaying by a predetermined amount; an arithmetic means for calculating the exclusive OR of digital data input to the delay means and digital data output from the delay means; 1. A pulse shaping circuit comprising: latch means for latching digital data output from the means.