JPS63222370A - Time base control system - Google Patents

Abstract

PURPOSE:To adjust a time base by generating a reference signals in accordance with the red position of a recording disk and controlling the rotative speed in accordance with an error signal corresponding to the level difference between a speed detection signal and the reference signal. CONSTITUTION:When a play command is issued, the output of an equalizer 40 is selectively outputted from a change-over switch 26 to turn on the frequency servo loop formed with a frequency generator 34, a waveform shaping circuit 35, an F/V converting circuit 36, a substracting circuit 37, an equalizer 44, the switch 26, a drive amplifier 32, and a spindle motor 33. Since data corresponding to the rotation number of a motor 33 in the read start position is preliminarily supplied to a D/A converter 38, the rotative speed of a disk 1 can be controlled within + or -5% range of a prescribed rotative speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time axis control method when reproducing information such as a video signal from a recording disk.

A M U that compresses the C-band of a single-dish high-definition television signal to a bandwidth of approximately 8 MHz to enable transmission by broadcast nil.
S E (Multiple 5ub-Nyquist
A method called "sampling encoding" has been proposed. According to this MLISE method, it is also easy to record high-quality television signals onto a recording medium such as an optical video disc.

However, the synchronization signal of the high-quality image signal (hereinafter referred to as MLJSE signal) with a bandwidth of about 8 MHz obtained by this MLISE method is positive polarity synchronization, and the amplitude of the synchronization signal is within the level of the video signal. do. As a result, MUS
With E signals, it is impossible to easily detect the synchronization signal using methods such as amplitude separation as in the case of conventional NTSC signals, and synchronization separation cannot be performed unless the signal is being reproduced on the normal time axis. Have difficulty. For this reason, if normal playback is not performed, especially during startup from a rotational stop state to steady rotation during playback on an optical video disc player, or during a search operation on a CLV (constant linear velocity) disc, The synchronization signal of the video signal cannot be used for time axis control when the disk rotation is not normal.

Therefore, it has been proposed to frequency-multiplex a pilot signal onto a video FMf signal when recording a MUSE signal on a video disk, and to separate this pilot signal when it is recorded to detect time-base errors. However,
In such a system, during disk playback, intermodulation components between the pilot signal and the video FM modulation signal appear as spurious within the baseband band of the video signal, and it is difficult to completely eliminate interference with the reproduced image due to this spurious. There is a drawback.

1 and 1 Accordingly, an object of the present invention is to provide a time axis control method that can perform time axis control favorably without using a pilot signal.

The time axis control method according to the present invention generates a reference signal according to the reading start position at the time of startup or search, and generates an error signal according to the level difference between the speed detection signal and the reference signal according to the rotational speed of the recording disk. The present invention is characterized in that the time axis is adjusted by controlling the rotational speed of the recording disk according to the rotational speed of the recording disk.

Friend-Shibu-1 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, recorded information on a disc 1 is read by an optical pickup 2. As shown in FIG. The pickup 2 includes a laser diode, an objective lens, a focus actuator, a tracking actuator, a photodetector, and the like.

The output of the photodetector in the pickup 2 is supplied to an RF amplifier 3 and a tracking error generation circuit 4. In the tracking error generation circuit 4, a tracking error signal is generated using a three-beam method, a push-pull method, or the like.

This tracking error signal is supplied to the tracking actuator in the pickup 2 via the tracking servo amplifier 5. Further, the DC component of the tracking error signal is supplied via a slider servo amplifier 6 to a slider motor 7 that moves the slider carrying the pickup 2 in the disk radial direction.

These tracking error generation circuits 4, tracking servo amplifiers 5, and slider servo amplifiers 6 are used to detect information that is formed by converging a laser beam emitted from a laser diode in the pickup 2 onto the recording surface of the disk 1 using an objective lens. The position of the light spot (information detection point) in the radial direction of the disk 1 is controlled.

A drive signal output from a search operation control circuit 7 is supplied to the slider servo amplifier 5. The search operation control circuit 7 receives data indicating the number of moving tracks from the system controller 8, and specifies the information detection light spot while counting the number of tracks to which the information detection light spot has skipped and moved based on the tracking error signal. The slider servo amplifier 6 is configured to send a drive signal to the slider servo amplifier 6 until the slider servo amplifier 6 has moved by the number of interlaced tracks, and then output a movement end signal. Further, a track jump command signal is supplied from the system controller 8 to the tracking servo amplifier 5, so that the information detection light spot jumps one track at a time.

On the other hand, the RF (high frequency) signal output from the RF amplifier 3 is supplied to a demodulation circuit 9 consisting of an FM demodulator etc.
The SE signal is demodulated. After the amplitude of this MUSE signal is made constant (for example, IVp-p) by the clamp circuit 10 and AGC (automatic gain control circuit) 11, the A/D
(analog-digital) is supplied to the converter 12 and comparator 13. A/1] The converter 12 is supplied with a clock a of 16.2M1-1z output from the pulse generation circuit 14. In the A/D converter 12, the MLJSE signal is zumbling by the clock a, and the obtained samples are sequentially converted into digital data. The output data of this A/D converter 12 is supplied to the HD detection OK signal generation circuit 15, the FP detection circuit 16, and the data separation circuit 17, and at the same time, the MU
Sent to an SE decoder (not shown).

The FP detection circuit 16 is configured to detect frame pulses in the digitized MUSE signal output from the A/D converter 12, for example, by pattern recognition. That is, when the FP detection circuit 16 detects the frame pulse inserted in the portion corresponding to the 605th line of the MUSE signal by pattern recognition, the FP detection circuit 16 detects the frame pulse inserted in the 606th line of the MUSE signal.
The pattern of frame pulses shown in FIG. 2 (A), which are inserted into the portion corresponding to the line and whose phase is inverted, is sequentially recognized and recognized by the clock a shown in FIG. A frame pulse point p existing 8 clocks ahead is detected to generate an FP detection pulse b as shown in FIG. 3(C).

FP detection pulse b output from this FP detection circuit 16
is supplied to the FP counter 18. FP counter 18
is configured to count the number of pulses of clock a by 1° over the period between two consecutive FP detection pulses. This FP counter 18 obtains a count value NF corresponding to the generation cycle of the FP detection pulse. The output data of this FP counter 18 is supplied to a sieve filter 19 to calculate the average number of clocks N1-IQ (NF/1125) in the HD interval. At normal timing (when synchronization is achieved and there is no sick), there are 540,000 clocks (480 clocks x 1125) in the detection FP interval, but when the disk rotation speed is controlled with an accuracy of a few percent of the specified speed, The average value of the HD interval is obtained by dividing the number of clocks NF present during the detected FP interval by 1125.

The output data of the divider 19 is supplied to the HD detection OK signal generation circuit 15 and the ID detection circuit 20.

The HD detection OK signal generation circuit 15 generates an HD detection window signal with a pulse width of 16 clocks centered at a position delayed by 13 clocks from the rising edge of the FP detection pulse b, for example, and this HD detection window signal exists. The HD detection OK signal is generated according to the level indicated by the output data of the A/D converter 12 during a period of 16 clocks. That is, the HD detection OK signal generation circuit 15 operates as shown in FIG. 3(D) over a period of 16 clocks centered at a position 13 clocks away from the rising edge of the FP detection pulse b as shown in FIG. 3(C). During the 6 clock period during which the HD detection window signal as shown in the figure exists, the output data of the A/D converter 12 as shown in FIG.
After reaching the value corresponding to the 56 level, it becomes the value corresponding to the 64/256 to 192/256 level over the next two clocks, and then becomes the value corresponding to the 64/25 level over the next two clocks.
When the value corresponding to the 6th level is reached, as shown in the same figure (E), < 64/2!HD detection is performed for, for example, 4 clocks from the rise of the next clock a between the 2 clocks in which the 16th level was detected. Generates OK signal d. Thereafter, HD detection is performed in the same manner, but the timing for generating the next I''D detection window signal is set using the NHD calculated by the divider 19.

That is, HD detection on and after the 608th line is performed from the rise of the HD detection OK signal on the 607th line to Nt+o.
This is done by generating a detection window signal that exists for 16 clocks centered on a position delayed by -3 clocks. still,
Since the HD signal is inverted every line after the 607th line, 1-ID detection is also inverted accordingly.

Further, since the NHD is updated sequentially as FP detection is performed, the NF also approaches 480×1125 (clock) as the F servo (frequency servo) loop, which will be described later, is locked.

Also, if the HD signal is lost due to dropouts, etc.
The D detection OK signal @d does not rise, and there is no timing to generate the next T + 0 detection window signal, but since the time width of the HD detection window signal is set to 16 clocks, for example, the previous HD It is sufficient to generate the signal over a period of 16 clocks centered at a position delayed by NHD from the center of the detection window signal.

The HD detection OK signal d is supplied to the HD detection circuit 20. When the l-1D detection OK signal is present, the HDD output circuit 20 delays the output of the comparator 13 for a predetermined period of time from the rising or falling edge of the output of the delay circuit 21, which delays the output of the comparator 13 by about 50 times. It is configured to output a high-level HD detection signal sound.

Now, the MUSE signal output from the FM demodulation circuit 9 passes through the clamp circuit 10 and the AGC circuit 11 and is supplied to the comparator 13 as a signal having an amplitude of <1V peak to peak as shown in FIG. .This comparator 1
If the reference level of 3 is set to the center level of the amplitude of the output f of the AGC circuit 11, that is, the level corresponding to the 12B/256 level, the output of the comparator 13 will always be inverted at the slope part of the HD signal, as shown in the figure. A signal as shown in (B) is obtained. Since the HD signal is a line alternating signal, rising edges and falling edges appear alternately in the output of the comparator 13 in 1H cycles. However, since level reversals occur frequently in video signals, edge detection using HD signals requires an HD detection OK signal d as shown in the same figure (C).
This is how it is done.

That is, the output Q of the comparator 13 is
As shown in FIG. 3(D), the edge of the HD signal is a signal that appears at the center timing of the existence period of the HD detection OK signal d in the normal state (locked state). Therefore, the delay amount of the delay circuit 21 is approximately 5
The time is set to a clock minute. If anything, H
This is because the D detection OK signal d is generated approximately three clocks later than the slope portion of the HD signal, and has a signal width of four clocks. In addition, in this example, as described later, F
Since the rotational speed of the disk 1 is controlled by the servo loop to a value of approximately ±5% of the specified speed, the timing of the HD detection OK signal d is within ±1 clock accuracy of the specified timing, and 12 from the characteristics of HD waveforms
Since the output 9 of the comparator 13 is not inverted within ±4 clock widths with respect to the 8/256 level, the width of the HD detection OK signal d is set to 4 clock widths.

For HD detection, the output timing of the HD detection signal is determined by the level inversion edge of the delayed output of the comparator 13 that exists within the HD detection OK signal width, and the pulse width is set at approximately 0.58D intervals using a one-shot circuit or the like. As a result, when locking is performed, an HD detection detection signal sound is generated as shown in FIG.

Note that if the HD detection OK signal is not output due to dropout, the L-ID detection signal may be forcibly generated at the NHo timing. In addition, the delay circuit 2
1, there will be a dead time element in the time axis servo loop, but this does not pose a problem because the bands of the spindle system and jitter control system are approximately 1 x 1''Z and several kHz, respectively.

The detection output of the HDD output circuit 20 is supplied to a phase comparator circuit 21 to generate an error signal according to the phase difference with the output of the frequency dividing circuit 23. The frequency dividing circuit 23 is configured to frequency divide the clock pulse and generate a reference signal of a predetermined frequency. The output of the phase comparator circuit 21 is supplied to a selector switch 26 via an equalizer amplifier 25. Further, the output of this phase comparison circuit 21 is supplied to a lock detection circuit 27. The lock detection circuit 27 is configured to generate a PLL lock detection signal when the absolute value of the output of the phase comparison circuit 21 becomes less than or equal to a predetermined value. This PLL lock detection signal is supplied to the system controller 8.

The output of the changeover switch 26 is supplied as a spindle error signal to a spindle motor 33 that rotationally drives the disk 1 via a drive amplifier 32, so that the rotational speed of the disk 1 is controlled. The spindle motor 33 has a built-in frequency generator 34 that generates an FG multiplied signal of a frequency corresponding to the rotational speed of the spindle motor 33. FG multiplied signal output from this frequency power generation 1134, waveform shaping circuit 3
5, the signal is supplied to an F/V conversion circuit 36 consisting of a differentiating circuit or the like, and is converted into a signal having a signal level corresponding to the FG multiplied signal frequency. The output of this F/V conversion circuit 36 is
It is supplied to a subtraction circuit 37.

The subtraction circuit 37 includes a D/A (digital/analog)
The output of the converter 38 is supplied, and the output of the F/V conversion circuit 36 is subtracted from this D/A converter 38. The output of this subtraction circuit 37 is supplied to a lock detection circuit 39, and at the same time, it is passed through an equalizer amplifier 40 and becomes an input to the switching main 'f-26.

The changeover switch 26 is configured to selectively output one of the outputs of the equalizer amplifiers 25 and 40 according to a command supplied from the system controller 8. The lock detection circuit 39 also includes, for example, a subtraction circuit 37.
The F servo lock detection signal is generated when the absolute value of the output becomes equal to or less than a predetermined value. The output of this lock detection circuit 39 is supplied to the system controller 8. The system controller 8 is supplied with address information inserted into a predetermined section of the MUSE signal by the data separation circuit 17, that is, a frame number in a CAV disk or a time number in a CLV disk. The system controller 8 is formed by a microcomputer including a processor, ROM, RAM, etc. In the system controller 8, each part is controlled by a processor that operates according to a program stored in advance in the ROM.

The operation of the processor of the microcomputer forming the system controller 8 in the above configuration will be explained with reference to the flowchart shown in FIG.

When a key operation on an operation unit (not shown) is performed during execution of a main routine or the like, the processor moves to step S1 and determines whether or not a play command has been issued. Step S
1, when it is determined that a play command has not been issued, the processor moves to step S2 and determines whether a search command has been issued. If it is determined in step S2 that the 'l--chi command has not been issued, the processor resumes execution of the routine that was being executed immediately before proceeding to step S1.

When it is determined in step S1 that a play command has been issued, the processor moves to step S3 to determine the rotational speed F of the disk 1 at the reading start position (innermost circumference).
o is calculated using a table stored in advance in the ROM. Next, the processor moves to step S4 and sends the rotational speed data to the D/A converter 38. Next, the processor moves to step S5 and selects the changeover switch 2.
The output of the equalizer amplifier 40 is selectively outputted from the frequency generator 34, the waveform shaping circuit 35, and the F
/V conversion circuit 36, subtraction circuit 37, equalizer amplifier 4
0, the F servo loop formed by the changeover switch 26, drive amplifier 32, and spindle motor 33 is turned on. Next, Pu Ot? The controller then proceeds to step S6 and determines whether or not the F servo lock detection signal is output from the lock detection circuit 39. In step S6, F
When it is determined that the servo lock detection signal is not output, the processor executes step $6 again, and only when it is determined that the F servo lock detection signal is output, the processor moves to step S7 and performs step 1-1. It is determined whether the 1D detection OK signal is output. In step S7, when it is determined that the HD detection OK signal is not output, the processor executes step S7 again, and only when it is determined that the HD detection OK signal is output, the processor moves to step S8. In step S8, the processor selectively outputs the output of the equalizer amplifier 25 from the changeover switch 26, turns off the F servo loop, and at the same time controls the spindle according to the phase difference between the HD signal and the output of the frequency divider 23. The PLL servo loop that controls the rotational speed of the motor 33 is turned on. Next, the processor moves to step S9 and determines whether or not the lock detection circuit 27 outputs a P and L lock detection signal.

In step S9, when it is determined that the PLL lock detection signal is not output, the processor executes step $9 again, and only when it is determined that the PLL lock detection signal is output, the processor moves to step S10. TeM
An operation start command is sent to a USE decoder (not shown) or the like to start the reproduction operation, and the routine executed immediately before proceeding to step S1 is resumed.

If it is determined in step S2 that a search command has been issued, the processor proceeds to step 811 and calculates the number of tracks Tn from the designated recording position to a position a predetermined distance in the inner circumferential direction. Next, the processor moves to step 812 and sends data indicating the calculated number of tracks Tn and the moving direction to the search operation control circuit 7 to start the search operation. Next, the processor moves to step 813 and calculates the rotational speed Fn of the disk 1 at the designated recording position using a table stored in advance in the ROM. The processor then moves to step 814 and sends the rotational speed data to the D/A converter 38. The processor then performs step 81
5 and from the changeover switch 26 to the equalizer amplifier 4.
Turn on the F servo loop so that the output of 0 is selectively output. The processor then performs step 816
Then, it is determined whether a movement end signal has been output from the search operation control m circuit 7. If it is determined in step S16 that the movement end signal has not been output, the processor executes step 816 again, and moves to step 817 only when it is determined that the movement end signal has been output. In step 317, the processor determines whether or not the F servo lock detection signal is output from the lock detection circuit 39. In step 817, when it is determined that the F servo lock detection signal is not output, the processor executes step S17 again, and only when it is determined that the F servo lock detection signal 4:A is output, step The process moves to 818. In step 818, the processor determines whether the position of the information detection light spot is shifted inward by a predetermined distance from the search position. If it is determined in step 818 that the position of the light spot is not shifted inward by a predetermined distance from the search position, the processor proceeds to step 319 and sends a track jump command to the tracking servo amplifier 5 using data indicating the jump direction. Then, the process returns to step S18. If it is determined in step 818 that the position of the light spot is shifted inward by a predetermined distance from the search position, the processor moves to step S7.

In the above operation, when a play command is issued, the output of the equalizer amplifier 40 is selectively outputted from the changeover switch 26 in step S5, and the FI nervo loop is turned on. Then, in step S4, D
Since data corresponding to the rotation speed of the spindle motor 33 at the reading start position is supplied to the /A converter 38, the spindle motor 33 is driven so that the rotation speed of the disk 1 converges to the speed at the reading start position.
be done. This F servo allows the rotational speed of the disk 1 to be set within a range of 15% of the specified rotational speed so that the HD signal can be detected.

Now, if the detection level in the lock detection circuit 39 is set so that the F servo lock detection signal is generated when the disk rotation speed falls within 15% of the specified rotation speed, the F servo lock detection signal will be generated. At this time, the PLL servo loop is turned on in steps S7 and S8, and the rotation speed of the spindle motor 33 is adjusted so that the phases of the 1-ID detection signal and the reference HD signal match, thereby achieving IS-accurate time-base control. will be started.

Further, when a search command is issued, the rotational speed of the spindle motor 33 is started to 1lilltll by 1=servo loop in steps 813 to 815 almost at the same time as the search operation is started. Therefore, at the same time as the movement of the information detection optical spot of the pickup ends, the rotational speed of the disk 1 can be set to a value within 15% of the specified rotational speed so that the ID signal can be detected. Therefore, the PLL servo can be started up quickly.

Note that the method of controlling the rotational speed of the spindle motor 33 using F servo roots as in steps S1 to S6 and S11 to S818 can also be employed in a device that performs time/axis control using a pilot signal.

■ Time axis according to the present invention as described in detail above 1. IJ all
This method generates a reference signal according to the reading start position, such as the innermost circumference position at startup or the skipped light during search, and generates a reference signal according to the level difference between the speed detection signal and the reference signal, which corresponds to the rotational speed of the recording disk. Since the frequency revo loop that adjusts the time axis by controlling the rotational speed of the recording disk according to the error signal detected by Since the time axis υ1111 can be performed to enable time axis control using a synchronization signal, a pilot signal is not required. Therefore, during normal reproduction, a good reproduced image without interference caused by the pilot signal can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 4 are waveform diagrams showing the operation of the device in FIG. 1, and FIG.
The figure is a flowchart, but does not show the operation of the microcomputer Brossener forming the system controller 8 in the apparatus of FIG.

Claims (2)

[Claims] (1) Generate a reference signal according to the reading start position of a signal reading means that reads the recorded signal of the recording disk in response to a command, and the level of the speed detection signal and the reference signal according to the rotational speed of the recording disk. generates an error signal according to the difference, starts adjusting the time axis by controlling the rotational speed of the recording disk according to the error signal, and reads a predetermined signal from the signal read by the signal reading means at the reading start position. A time axis control method characterized in that the adjustment is continued until detection is performed. (2) The recording signal is a MUSE formed by band-compressing a high-quality TV signal using the TCI multiplex subsampling method.
(MultipleSub-NyquistSample
2. The time axis control method according to claim 1, wherein the predetermined signal is a horizontal synchronization signal (HD signal).