JPS63220628A - Receiving signal processing circuit - Google Patents

Abstract

PURPOSE:To use one type of a timing signal to attain signal processing and to use a circuit in common by connecting a frame synchronizing circuit and a signal processing circuit to the output side of a forward error correction circuit. CONSTITUTION:A frame synchronizing circuit 5 detects a frame pattern in a signal inputted and outputted through a forward error correction circuit 4 to stop an error correction function or a signal inputted directly, and with the detecting pattern, a second timing signal is generated and sent to a signal processing circuit 2. The signal processing circuit 2 executes the processing to the above-mentioned input signal with use of this timing signal regardless of the presence and absence of the forward error correction circuit, the second timing signal can be shared and the circuit scale is shrinked.

Description

[Detailed Description of the Invention] [Summary] In a received signal processing circuit, a frame synchronization circuit detects a frame pattern in a signal inputted via a forward error correction circuit whose error correction function is stopped or in a signal inputted directly. At the same time, a second timing signal is generated using this detection timing and sent to the signal processing circuit.

The signal processing circuit uses this timing signal to process the above input signal, thereby making it possible to share the second timing signal regardless of the presence or absence of the forward error correction circuit, thereby reducing the circuit scale. This is what I did.

[Industrial application field]

The present invention relates to an improvement in a received signal processing circuit 1 used in a multi-plant QAM digital multiplex radio device, for example.

FIG. 4 shows an example of the configuration of a multilevel QAM digital multiplex radio system.

First, the line switching device has a line switching function, a line monitoring function, and a signal processing function.

The line switching function is for switching between the working line and the protection line, and the line monitoring function is for inserting and extracting line monitoring pulses, monitoring line quality, etc. Further, the signal processing functions include bipolar/unipolar conversion, unipolar/bipolar conversion, serial/parallel conversion, parallel/serial conversion, speed conversion, etc.

Next, the transmitting device in the wireless transmitting/receiving device uses the input signal from the line switching device to convert the carrier wave to multilevel QAM L, a predetermined level,
The signal is transmitted at a predetermined frequency, and the receiving device demodulates the received multilevel QAM signal and sends it to the line switching device. Further, the supervisory control device monitors the operation of the relay device and the like.

Here, the received signal processing circuit of the present invention is included in the receiving side line switching device, but the timing signal for extracting the above-mentioned inserted pulse is used for forward error correction (hereinafter referred to as
It is necessary to reduce the circuit scale by making it possible to share the circuit with or without FEC (abbreviated as FEC).

[Conventional technology]

Figure 5 is a block diagram of a conventional example.
When the circuit is added, Fig. 5 (b) is when FEC is not added, Fig. 6 is an explanatory diagram of the operation of Fig. 5, and □
Figure G (al is when the FEC circuit is added, Figure 6 (
The figure shows the case where no FEC circuit is added. Note that the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG. The operation shown in FIG. 5 will be explained below with reference to FIG.

(1) When an FEC circuit is added.

As shown in FIG. 6 (81-■), a signal into which frame synchronization pulses F4, F5+ Fb, P7, etc. are periodically inserted is applied to the frame synchronization detection/protection circuit 31 in the frame synchronization circuit 3, Since the frame pattern from the frame pattern generator 32 is added here, the patterns are compared and if they match a predetermined number of times in succession, frame synchronization is determined and a frame synchronization pulse is sent to the timing generator 33.

Therefore, the timing generator uses this pulse to
An EC timing signal and a signal processing timing signal are generated and sent to the FEC circuit 1 and the signal processing circuit 2.

The FEC circuit 1 calculates the error position in the signal using the FEC timing signal, corrects the error, and outputs it, but the signal is delayed for the time necessary for calculation and correction, for example, by two subframes as shown in the figure. (See Figure 6 (al-■, ■)
. Here, since the signal input to the signal processing circuit 2 is delayed by two subframes, the above timing signal for signal processing is also delayed by two subframes as shown in FIG. 6 (al-■, ■). Become.

The signal processing circuit 2 extracts parity pits inserted on the transmitting side, digital service channel signals necessary for maintenance, etc. from the error-corrected signal using the signal processing timing signal, and then extracts the parity pits inserted at the transmitting side, digital service channel signals necessary for maintenance, etc. ).

(If the 21FEC circuit is not added.

When a signal as shown in FIG. 6 (bl-■) is applied to the frame synchronization circuit 3 without delay, a frame synchronization pulse is applied to the timing generator 33, and from there a timing signal for signal processing is applied to the signal processing circuit. , since this timing signal processes a signal that does not have a delay (there is no delay like in item 1 and 1 (Fig. 6-■).

■Reference).

[Problem that the invention seeks to solve]

That is, since it is necessary to generate two types of timing pulses for signal processing to be sent from the frame synchronization circuit to the signal processing circuit depending on the presence or absence of the FEC circuit, there is a problem in that the circuit size increases if shared use is performed.

[Means for solving problems]

The above problem is solved by the received signal processing circuit shown in FIG.

4 outputs the input signal without performing error correction while the correction prohibition signal is applied, and corrects errors in the input signal using the first timing signal while the correction permission signal is applied. A forward error correction circuit 5 outputs a correction prohibition signal until frame synchronization is established between the first timing signal and the second timing signal and the output from the forward error correction circuit 4. After that, there is a frame synchronization circuit that sends out a correction permission signal.

Further, 2 is a signal processing circuit that performs signal processing on the output from the forward error correction circuit using the second timing signal.

[Effect]

The present invention connects the frame synchronization circuit 5 and the signal processing circuit 2 to the output side of the PEC circuit 4, so that the phase relationship between the second timing signal and the signal input to the signal processing circuit is independent of the presence or absence of the FEC circuit. I tried to make sure it didn't change.

That is, the frame pattern in the signal input via the PEC circuit 4 whose error correction function is prohibited or in the signal input directly is detected by the frame synchronization circuit 5, and this detection timing is used to detect the frame pattern in the first timing signal. , generates a second timing signal and sends it to the FEC circuit and signal processing circuit 2.

Since the same signal as the signal input to the frame synchronization circuit is applied to the signal processing circuit, signal processing can be performed using one type of second timing signal regardless of the presence or absence of the FEC circuit, so the circuit can be shared. This makes it possible to reduce the scale of the two circuits.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 2(a)
is shown in Figure 2 (bl is F when an FEC circuit is added).
When the EC circuit is not added, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 3 (a) is an explanatory diagram of the operation of Fig. 2 (a), and Fig. 3 (b) is an explanatory diagram of the operation of Fig. 2. An explanatory diagram of the operation in (b) is shown.

Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Also, the same reference numerals indicate the same objects throughout the figures. The operation shown in FIG. 2 will be explained below with reference to FIG.

+11 If an FEC circuit is added.

Figure 3 ((
When the frame pattern in the signal shown in L)-■ does not match the frame pattern from the frame pattern generator 52, a correction prohibition signal as shown in FIG. The FEC function is stopped.

However, when frame synchronization is achieved, the correction inhibition signal is canceled by the correction permission signal, and the frame synchronization pulse shown in FIG. 3(a)-0 is applied to the timing generator 53.
From here, the timing signal for signal processing, Fig. 3(a)-■
The FEC timing signal as shown in the figure is sent to the signal processing circuit 2.
It is added to the PEC circuit 41.

Therefore, the FEC circuit outputs a signal with the error corrected,
The corrected signal is processed by the signal processing circuit 2 and sent to the outside.

(If the 21FEC circuit is not added.

The frame synchronization detection/protection circuit 51 outputs a frame synchronization pulse and sends a signal processing timing signal to the signal processing circuit 2 when the frame pattern in the input signal matches the generated frame pattern (as in the case of Section 11). The signal processing circuit then uses this timing signal to process the input signal.

That is, the signal processing timing signal applied to the signal processing circuit can be shared regardless of the presence or absence of the FEC circuit, thereby reducing the circuit scale.

〔Effect of the invention〕

As described in detail above, according to the present invention, the signal processing timing can be shared, so that the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, FIG. 4 is a configuration example of a digital multiplex radio device, and FIG. The figure shows a block diagram of a conventional example, and FIG. 6 shows an operation explanatory diagram of FIG. 5.

Claims (1)

[Claims] While the correction prohibition signal is applied, the input signal is output without error correction, and while the correction permission signal is applied, the input signal is output using the first timing signal. Forward error correction circuit (
4) and a correction prohibition signal until frame synchronization is established for the first timing signal, the second timing signal, and the output from the forward error correction circuit (4), and a correction permission signal after the establishment. Frame synchronization circuit (5
); and a signal processing circuit (2) that performs signal processing on the output from the forward error correction circuit using the second timing signal.