JPS63220536A - Evaluation of radiation resistance of integrated circuit - Google Patents
Evaluation of radiation resistance of integrated circuitInfo
- Publication number
- JPS63220536A JPS63220536A JP62052862A JP5286287A JPS63220536A JP S63220536 A JPS63220536 A JP S63220536A JP 62052862 A JP62052862 A JP 62052862A JP 5286287 A JP5286287 A JP 5286287A JP S63220536 A JPS63220536 A JP S63220536A
- Authority
- JP
- Japan
- Prior art keywords
- radiation resistance
- ics
- integration
- data
- radiation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005855 radiation Effects 0.000 title claims abstract description 60
- 238000011156 evaluation Methods 0.000 title description 3
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 230000010354 integration Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 8
- 101150097247 CRT1 gene Proteins 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の耐放射線性の評価方法に係り、特に
電子回路の設計に好適な集積回路の耐放射線性評価方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for evaluating the radiation resistance of an integrated circuit, and particularly to a method for evaluating the radiation resistance of an integrated circuit suitable for designing electronic circuits.
集積回路の耐放射線性は、昭和58年度宇宙開発事業団
委託業務成果報告書 第27頁から第34頁等において
報告されているように、各集積回路毎に異なっている。The radiation resistance of integrated circuits differs from one integrated circuit to another, as reported in pages 27 to 34 of the 1985 National Space Exploration Agency Commissioned Work Results Report.
このため、従来の耐放射線性の評価は集積回路の1種類
毎に実験して行なっていた。For this reason, radiation resistance has conventionally been evaluated by conducting experiments for each type of integrated circuit.
電子回路の設計は、多種類の集積回路(以下、ICと記
述する)を使用して行なわれる。一方、設計した電子回
路の耐放射線性を評価するためには、使用したIC各々
の耐放射線性を知る必要がある。しかし、市販されてい
るICの種類は非常に多いため、上記従来技術の評価方
法で全てのICの耐放射線性をあらかじめ評価しておく
のは非常に困難である(電子回路の耐放射線性を評価す
るのに必要な、使用ICの耐放射線性データが全て既知
である場合は殆んどない。)。Electronic circuits are designed using many types of integrated circuits (hereinafter referred to as ICs). On the other hand, in order to evaluate the radiation resistance of a designed electronic circuit, it is necessary to know the radiation resistance of each IC used. However, since there are so many types of ICs on the market, it is extremely difficult to evaluate the radiation resistance of all ICs in advance using the conventional evaluation method described above (the radiation resistance of electronic circuits is There are very few cases in which all the radiation resistance data of the IC used for evaluation is known.)
本発明の目的は限られたICの耐放射線性評価実験デー
タから、実験データの無いICの耐放射線性を予測でき
るようにすることにある。An object of the present invention is to make it possible to predict the radiation resistance of an IC for which there is no experimental data from the limited experimental data for evaluating the radiation resistance of an IC.
上記目的は、ICを製造プロセスにより分類し、分類し
たIC群の中でICの耐放射線性とI Cの集積度との
関係式を少数の丁cの耐放射線性データからあらかじめ
求めておき、耐放射線性データが未知のICの耐放射線
性を、そのICの製造プロセスと集積度をデータとして
、先に求めておいた該当する関係式を用いて予測するこ
とにより達成される。The above purpose is to classify ICs according to their manufacturing process, and to obtain in advance the relational expression between the radiation resistance of ICs and the degree of integration of ICs among the classified IC groups from the radiation resistance data of a small number of ICs. This is achieved by predicting the radiation resistance of an IC for which radiation resistance data is unknown, using the manufacturing process and degree of integration of the IC as data, and using the corresponding relational expression determined previously.
ICの耐放射線性は、製造プロセスが同じであれば集積
度に対応して変化することが分っている。It has been found that the radiation resistance of an IC varies with the degree of integration given the same manufacturing process.
従って、代表的なICの耐放射線性を実験で評価し、耐
放射線性と集積度の関係をあらかじめ数式化しておくこ
とにより、耐放射線性の実験データのないICについて
も、製造プロセスと集積度がわかれば耐放射線性を予測
することができる。Therefore, by evaluating the radiation resistance of typical ICs through experiments and formulating the relationship between radiation resistance and degree of integration in advance, it is possible to evaluate the manufacturing process and degree of integration even for ICs for which there is no experimental data on radiation resistance. If we know this, we can predict the radiation resistance.
以下、本発明の一実施例を第1図〜第3図により説明す
る。第1図は本発明の一実施例の構成図である。本装置
は、ICの耐放射線性(一般に動作に異常が発生しはじ
める放射線量で表わすため、以下、耐放射線量と言う。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a block diagram of an embodiment of the present invention. This device measures the radiation resistance of an IC (generally expressed as the radiation dose at which abnormalities begin to occur, hereinafter referred to as radiation resistance).
)の予81す結果を表示するCRTI、データを入力す
るためのキーボード2、本装置の制御プログラムを格納
しておくメモリ5、そのプログラムに従って装置を制御
するC P tJ 4、ICの耐放射線性データ髪保存
して置くためのディスク6、及びそれらを接続するバス
3から成る。), a keyboard 2 for inputting data, a memory 5 for storing the control program of this device, a C P tJ 4 for controlling the device according to the program, and radiation resistance of the IC. It consists of a disk 6 for storing data and a bus 3 connecting them.
以下、第2図に従って本装置の動作を説明する。The operation of this device will be explained below with reference to FIG.
第2図は制御プログラムのフローチャートである。FIG. 2 is a flowchart of the control program.
プログラムは大きく2つにわかれる。1つはデータ登録
の部分L1〜L6、他は耐放射線性の予測の部分子、
10〜L14である。The program is broadly divided into two parts. One is the data registration part L1 to L6, the other part is the radiation resistance prediction part,
10 to L14.
先ず、データ登録の部分から説明する。キーボード2か
ら操作者がICの製造プロセス名を入力する。First, the data registration part will be explained. The operator inputs the IC manufacturing process name using the keyboard 2.
ICには素子の材料でもシリコンを使用したものやG
a A sを使用したもの等がある。現在、主流である
シリコン系素子を例にとると、そのICを構成する基本
トランジスタの種類により、バイポーラ形、MOS形に
分けられる。上述の製造プロセスとはこのような基本的
な使用材料、基本トランジスタの種類に始まり、トラン
ジスタのpn接合部の製造方法、素子の構造、大きさ等
の詳細の仕様を含めたICの製造方法を言う。各メーカ
は通常、複数の製造プロセスを有しており、それぞれの
製造プロセスに固有の名称が付されている。ICs that use silicon or G
There are some that use a A s. Taking silicon-based devices, which are currently mainstream, as an example, they can be divided into bipolar type and MOS type, depending on the type of basic transistors that make up the IC. The above-mentioned manufacturing process starts with the basic materials used and types of basic transistors, and includes detailed specifications such as the method for manufacturing the pn junction of the transistor, the structure and size of the element, and the method for manufacturing the IC. To tell. Each manufacturer typically has multiple manufacturing processes, each with a unique name.
同じ機能を持ったIC1例えばT T Lの7400シ
リーズでもメーカが異なればその製造プロセスは細かい
部分で異なるため、耐放射線性は異なる。Even if ICs 1 having the same function, such as TTL's 7400 series, are made by different manufacturers, the manufacturing process will differ in the details, so the radiation resistance will differ.
入力された製造プロセス名のデータはL2でCPU4が
取込み、ディスク6上に登録する。次に、操作者は既に
実験により耐放射線量は確認済のIC(登録した製造プ
ロセスのもの)の集積度と耐放射線量のデータを登録す
る(L3〜L4)。The input manufacturing process name data is taken in by the CPU 4 at L2 and registered on the disk 6. Next, the operator registers data on the degree of integration and radiation resistance of the IC (from the registered manufacturing process) whose radiation resistance has already been confirmed through experiments (L3-L4).
データの入力が終了すると、CPUは集積度と耐放射線
量の関係式を計算する(L5)。本実施例では最小2乗
法でフィッティングする。求めた計算式は製造プロセス
名と対応させてディスク6に登録する(T、6)。When the data input is completed, the CPU calculates a relational expression between the degree of integration and the radiation resistance (L5). In this embodiment, fitting is performed using the least squares method. The calculated formula is registered on the disk 6 in association with the manufacturing process name (T, 6).
以上の登録を複数の製造プロセスに対して繰返し行なう
。The above registration is repeated for a plurality of manufacturing processes.
次に耐放射線量の予測について説明する。操作者はキー
ボード2を用いて予測したいICの製造プロセス名を入
力する。CP U 4はそのデータを取込む(LIO)
。さらに操作者はICの集積度(集積されたトランジス
タ数)を入力し、CPU4はそれを取込む(Lll)、
次にCPU4は取込んだ製造プロセス名を用いてディス
ク6から関係式を検索する(L 12)。ICの集積度
とその関係式から、ICの耐放射線量が計算でき、CR
Tlに計算結果を表示する(T、14)。Next, prediction of radiation resistance will be explained. The operator uses the keyboard 2 to input the name of the IC manufacturing process to be predicted. CPU 4 takes in the data (LIO)
. Furthermore, the operator inputs the degree of integration of the IC (the number of integrated transistors), and the CPU 4 takes it in (Lll).
Next, the CPU 4 searches for a relational expression from the disk 6 using the imported manufacturing process name (L12). From the IC integration degree and its relational expression, the radiation resistance of the IC can be calculated, and the CR
The calculation result is displayed on Tl (T, 14).
第3図にCRTlの表示例を示す。耐放射線量を予測す
べきICの製造プロセス名が製造プロセス名表示欄1o
に、集積度が集積度表示欄11に表示される。関係式1
3により計算された耐放射線量が耐放射線量表示欄12
に示される。一般に本図に示されるように、集積度が増
加すると耐放射線量は減少する。FIG. 3 shows an example of a display on a CRTl. The manufacturing process name of the IC whose radiation resistance dose should be predicted is in the manufacturing process name display column 1o.
Then, the degree of accumulation is displayed in the degree of accumulation display column 11. Relational expression 1
The radiation resistance calculated in step 3 is displayed in the radiation resistance display column 12.
is shown. Generally, as shown in this figure, as the degree of integration increases, the radiation resistance decreases.
本実施例によれば、実験データのないICの耐放射線性
が簡単に予測できる効果がある。According to this embodiment, there is an effect that the radiation resistance of an IC for which there is no experimental data can be easily predicted.
本発明によれば耐放射線性実験データのない集積回路の
耐放射線性が、既知の集積回路の耐放射線性データから
簡単に予測できる効果がある。According to the present invention, the radiation resistance of an integrated circuit for which there is no radiation resistance experimental data can be easily predicted from radiation resistance data of known integrated circuits.
第1図は本発明の一実施例の構成図、第2図は制御プロ
グラムのフローチャート、及び第3図はCRT表示画面
図である。
1・・・CRT、2・・・キーボード、3・・・バス、
4・・・CPU、5・・・メモリ、6・・・ディスク、
10・・・製造プロセス名表示欄、11・・・集積度表
示欄、12・・・耐放射線量表示欄、13・・・関係式
表示。
特許出願人 工業技術院長 飯塚十三
第 1 図
第 2 国FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart of a control program, and FIG. 3 is a CRT display screen diagram. 1... CRT, 2... Keyboard, 3... Bus,
4...CPU, 5...Memory, 6...Disk,
10... Manufacturing process name display column, 11... Integration degree display column, 12... Radiation resistance display column, 13... Relational expression display. Patent applicant: Director of the Agency of Industrial Science and Technology Juzo Iizuka No. 1 Figure No. 2 Country
Claims (1)
積回路の製造プロセス毎に、実測された集積回路の耐放
射線性データから集積度と耐放射線性の関係を求め、こ
の製造プロセス毎の集積度と耐放射線性の関係を用いて
、製造プロセスと集積度が既知の集積回路の耐放射線性
を予測することを特徴とする集積回路の耐放射線性評価
方法。1. In the method of evaluating the radiation resistance of integrated circuits, the relationship between the degree of integration and radiation resistance is determined from the actually measured radiation resistance data of integrated circuits for each integrated circuit manufacturing process, and the relationship between the degree of integration and radiation resistance is calculated for each manufacturing process. A method for evaluating the radiation resistance of an integrated circuit, the method comprising predicting the radiation resistance of an integrated circuit whose manufacturing process and degree of integration are known, using the relationship between radiation resistance and radiation resistance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62052862A JP2580503B2 (en) | 1987-03-10 | 1987-03-10 | Radiation resistance evaluation method for integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62052862A JP2580503B2 (en) | 1987-03-10 | 1987-03-10 | Radiation resistance evaluation method for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63220536A true JPS63220536A (en) | 1988-09-13 |
JP2580503B2 JP2580503B2 (en) | 1997-02-12 |
Family
ID=12926678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62052862A Expired - Lifetime JP2580503B2 (en) | 1987-03-10 | 1987-03-10 | Radiation resistance evaluation method for integrated circuits |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2580503B2 (en) |
-
1987
- 1987-03-10 JP JP62052862A patent/JP2580503B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2580503B2 (en) | 1997-02-12 |
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EXPY | Cancellation because of completion of term |