JPS6321920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope circuit suitable as an audio signal generating circuit for digital watches, calculators, and the like.

Recent digital watches, calculators, and other electronic devices have built-in speakers and can generate various sounds. For example, in a digital watch, a continuous tone with a certain frequency or a beautiful melody tone may be emitted from the speaker at the alarm time. Furthermore, on the calculator,
Key operation sounds are heard when keys are operated. In this way, recent electronic devices have begun to appeal to us audibly by having built-in speakers, rather than relying solely on displays.

However, each of the above-mentioned sounds is an electronic sound generated by a simple output circuit, and since the sound does not naturally attenuate, the sound is extremely unpleasant to the ear. In particular, the melody sounds produced by simple output circuits, unlike the soft sounds produced by musical instruments, are extremely unpleasant to the listener.

However, in order to make the above-mentioned unpleasant electronic sound a pleasant sound, if circuit considerations are taken to naturally attenuate the generated sound, the sound will become more similar to natural sounds.

The present invention forms a circuit (envelope circuit) in the speaker output circuit etc. that can naturally attenuate electronic sounds and leave a lingering sound.
This is a device designed to make electronic sounds more pleasant to hear.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, V _AH is an output terminal, and a P-channel type switching MOS transistor TP0 and a resistor R ₀ are connected in series to the output V _AH on the power supply V _DD side. Also, for the output V _AH
N-channel type switching on the GND (ground) side
A MOS transistor TN1 and a resistor _R1 are connected in series, and three series circuits are provided as one block. R ₁ ~ R ₃ are its resistances, TN1 ~ TN
3 is the transistor. Further, an N-channel MOS transistor TNX whose gate input is a buzzer signal BUZ (for example, 4 kHz) is added in parallel to the output _VAH . Transistor TN1~TN
Outputs Q of binary counters (flip-flops) BC1 to BC3 are connected to the gates of 3, respectively. These counters BC1 to BC3 have terminals connected to adjacent T terminals, and only the T terminal of BC1 in the first stage receives a clock signal via inverter I.
CLOCK is supplied. Here, it is assumed that the resistance values of the resistors R ₁ to R ₃ are set so that R ₁ >R ₂ >R ₃ . Also, transistors TP0, TN1~TN
The ON resistance of No. 3 is set to a constant so that it is almost negligibly small with respect to the resistors R ₀ and R ₁ to _{R 3} connected in series with each other. In other words, considering the series combined resistance, {R ₀ + (ON resistance of TP0)} R ₀ {R ₁ + (ON resistance of TN1)} R ₁ {R ₂ + (ON resistance of TN2)} R ₂ {R ₃ + (ON resistance of TN3)} R ₃ .

FIG. 2 is an operating waveform diagram of the envelope circuit having the above configuration.
The operation of the circuit shown in the figure will be explained. First, CLOCK in Figure 1
Connect the clock signal to the signal input terminal as shown in Figure 2.
If CLOCK is input, frequency-divided waveforms S1 to S3 as shown in the figure are obtained and supplied to the gates of transistors TN1 to TN3, respectively.

(1) Output voltage V _AH at time t ₀ : At this time, S1 = S2 = S3 = GND (ground level)
Therefore, transistors TN1 to TN3 are all turned off. Here, when the buzzer signal BUZ is at the power supply voltage V _DD , the transistor TP0 is turned off and the transistor TNX is turned on to reduce the output voltage.
V _AH becomes GND level. Meanwhile, the buzzer signal
When BUZ is GND, transistor TNX turns off and transistor TP0 turns on, so
Output V _AH becomes V _DD level (V _AH0 ). In other words, the output V _AH will fully swing between the GND and V _DD levels.

(2) Output voltage V _AH at time t ₁ : At this time, S ₁ = V _DD and S ₂ = S ₃ = GND, so transistor TN1 is on and transistor
TN2 and TN3 are turned off. Here, when the buzzer signal BUZ is _VDD , the transistor TP0 is turned off and the transistors TNX and TN1 are turned on, so the output _VAH becomes the GND level. When the buzzer signal BUZ is GND, the transistor TP
0, TN1 is on, transistor TNX, TN
2. Since TN3 is off, the output voltage is V _DD −
A voltage divided by the resistances of {R ₀ + (ON resistance of TP0)} and {R ₁ + (ON resistance of TN1)} is output between GND. As mentioned above, {R ₀ + (ON resistance of TP0)} R ₀ {R ₁ + (ON resistance of TN1)} R ₁ , so the output voltage is the power supply voltage between V _DD and GND by resistors R ₀ and R Voltage level divided by ₁ (V _AH1
). Here, V _AH1 = R ₁ /R ₀ + R ₁ ·V _DD (<V _DD ). To summarize, the output voltage V _AH is between GND and
It will swing between V _AH1 .

(3) Output voltage V _AH at time t ₂ : Since S ₂ = V _DD and S ₁ = S ₃ = GND at this time, transistor TN2 is on and transistor
TN1 and TN3 are turned off. Here, when the buzzer signal BUZ is V _DD , transistor TP0 is off and TNX and TN2 are on, so
Output V _AH becomes GND level. On the other hand, when the buzzer signal BUZ is GND, the transistor TP0
and TN2 are on, and TNX, TN1, and TN3 are off, so the output voltage is the resistance between {R ₀ + (on resistance of TP0} and {R ₂ + (on resistance of TN2)} between V _DD and GND. A divided voltage is obtained.
As mentioned above, {R ₀ + (on resistance of TP0)} R ₀ {R ₂ + (on resistance of TN2)} R ₂ , so the output voltage is the power supply voltage between V _DD and GND and the resistance R ₀ . A voltage divided by R ₂ (denoted V _AH2 ) is obtained. Here, V _AH2 = R ₂ /R ₀ + R ₂ ·V _DD (<V _AH1 ). To summarize, the output voltage V _AH is between GND and
It will swing between V _AH1 .

(4) Output voltage V _AH at time _t3 : Since S ₁ = S ₂ = V _DD and S ₃ = GND at this time, transistors TN1 and TN2 are on, and TN
3 is off. Here the buzzer signal BUZ is V _DD
When , transistor TP0 is turned off and TNX,
Since TN1 and TN2 are on, the output V _AH
becomes GND level. Meanwhile, the buzzer signal BUZ
When is GND, transistors TP0 and TN1,
Since TN2 is on and TNX and TN3 are off, the output voltage between V _DD and GND is {R ₀ +
(TP0 on-resistance)}, {R ₁ + (TN1 on-resistance)} and {R ₂ + (TN2 on-resistance)} A voltage divided by the resistances is obtained. As mentioned above, {R ₀ + (on resistance of TP0)} R ₀ {R ₁ + (on resistance of TN1)} R ₁ {R ₂ + (on resistance of TN2)} R ₂ , so the output voltage is V A voltage level (indicated by V _AH3 ) is obtained by dividing the power supply voltage between _DD and GND by the resistors R ₀ , R ₁ , and R ₂ . Here, take V _AH3 = R ₁ R ₂ / R ₀ (R ₁ + R ₂ ) + R ₁ R ₂・V _DD (<V _AH2 ). To summarize, the output voltage V _AH is between GND and
It will swing between V _AH3 . Similarly, the following conclusions can be obtained.

(5) Output voltage V _AH at time t ₄ : At this time, a voltage swinging between GND and V _AH4 (voltage level obtained by dividing the power supply voltage between V _DD and GND by resistors R ₀ and R ₃ ) is obtained. Here, V _AH4 = R ₃ / R ₀ + R ₃ · V _DD (< V _AH3 ) (6) Output voltage at time t ₅ V _AH : At this time, the power supply voltage between GND and V _AH5 (V _DD − GND is connected to the resistor R A voltage swinging between voltage levels divided by ₀ , R ₁ and R ₃ is obtained.
Here, V _AH5 = R ₁ R ₃ / R ₀ (R ₁ + R ₃ ) + R ₁ R ₃・V _DD (＜V _AH4 ) (7) Output voltage V _AH at time t ₆ : At this time, GND and V _AH6 (V (Voltage level obtained by dividing the power supply voltage between _DD and GND by resistors R ₀ , R ₂ , and R ₃ )
A voltage swinging between . Here, V _AH6 = R ₂ R ₃ / R ₀ (R ₂ + R ₃ ) + R ₂ R ₃・V _DD (<V _AH5 ) (8) Output voltage at time t ₇ V _AH : At this time, GND and V _AH7 (V A voltage that swings between voltage levels obtained by dividing the power supply voltage between _DD and GND by resistors R ₀ , R ₁ , R ₂ , and R ₃ is obtained. Here, V _AH7 = R ₁ R ₂ R ₃ /R ₀ (R ₁ R ₂ + R ₂ R ₃ + R ₁ R ₃ )・V _DD (<V _AH6
) As above, the output voltage V _AH is V _AH0 > V _AH1
The following results were obtained: >V _AH2 >V _AH3 >V _AH4 >V _AH5 >V _AH6 >V _AH7 . In other words, the buzzer signal BUZ initially outputs a signal with a full swing between V _DD and GND.
The swing of what was output to V _AH gradually becomes smaller over time. and buzzer signal
Since the frequency of BUZ does not change, only the intensity (loudness) of the sound gradually decreases without changing the pitch.

The features of this envelope circuit are as follows.

(i) Switching MOS transistor TP0, TN
By making the element dimensions of 1 to TN3 sufficiently large and making the on-resistance as small as possible, it is possible to determine the output voltage V _AH only by resistance division of the power supply voltage with respect to the linear resistances R ₀ to R ₃ .
This means that when a desired V _AH is required, an envelope circuit can be constructed with a combination of only linear resistors, and there is no need to include nonlinear resistors such as MOS resistors, making circuit design extremely simple. Become.

(ii) significantly affected by the manufacturing process;
Since the MOS resistor can be ignored in terms of the circuit, it is possible to output V _AH determined according to a certain specification with extremely high accuracy and with less variation.

(iii) In this embodiment, eight different output voltages _VAH can be obtained by combining three blocks of resistors with switching N-channel MOS transistors. In other words, the number of blocks is N
If so, the level of V _AH can be changed in 2 ^N ways, and many types of V _AH can be obtained with a small number of circuit elements.

(iv) The envelope circuit also includes a transistor
TPO (P channel type) and TNx (N channel type)
Since they form a complementary circuit, no through current flows between the power supply and ground.

Furthermore, the binary counters BC1 to BC3 in Figure 1
Although the reset section is not shown, the buzzer signal
When there is no BUZ, a reset is applied and the buzzer signal is activated.
It is possible to configure the reset to be canceled when there is a BUZ.

FIG. 3 shows an example of a circuit in which the envelope circuit 11 shown in FIG. 1 is used to actually drive the speaker 12. In the figure, 13 is an output stage transistor, 14
is a resistance that finely adjusts the slope of the envelope.

Note that the present invention is not limited to the embodiments, and the circuit configuration is not limited to the CMOS type, for example. In addition, linear resistors and switching MOS transistors were used as circuit elements for voltage division.
It may be constructed using a MOS resistor and a switching MOS transistor, or only a MOS transistor having both of these functions. Further, in the embodiment, the transistors TN1 to TN3 are driven by a binary counter, but this driving means is merely an example. In addition, although the transistors TP0 and TNX were driven by a buzzer signal BUZ with a constant frequency, if the frequency is made variable, it can also be heard as music.

As explained above, according to the present invention, the circuit structure is such that the electronic sound can be naturally attenuated and a lingering sound can be left, so that it is possible to provide an envelope circuit that allows the electronic sound to be heard more comfortably.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a signal waveform diagram showing the operation of the circuit, and FIG. 3 is a circuit diagram showing an example of actual use of the circuit. R ₀ ~ R ₃ ...Resistance, TP0, TNX, TN1 ~ TN
3...MOS transistor, BC1 to BC3...Binary counter.

Claims (1)

[Claims] 1 A first circuit section including a series circuit of a first channel type MOS transistor and a resistance element provided between a first potential supply end and an output end, and a second potential supply end and the output end. 2nd channel type between
A second circuit section formed by arranging a plurality of series circuits of MOS transistors and low resistance elements in parallel, and a second channel type circuit section connected in parallel with this second circuit section.
MOS transistor and the first channel type MOS
a transistor and a low resistance element, or the second channel type connected in parallel with the second circuit section;
A sound generator comprising: a first control means for energizing the MOS transistor; and a second control means for energizing a combination of the plurality of parallel-connected second channel MOS transistors and the resistor element. A circuit that directly drives the output terminal is directly connected to the first channel type of the first circuit section.
the gate electrode of the MOS transistor, and the second
the second channel type connected in parallel with the circuit section of
An envelope circuit characterized by having a configuration in which a control input is added to the gate electrode of a MOS transistor.