GB2078032A - Electronic signal decay control circuit - Google Patents

Abstract

An electronic signal decay control circuit particularly for controlling sound signals comprises a first switch TP0 having a series resistance R0 connected between a first potential terminal and an output terminal VAH and a second switch TNX connected between the output terminal and a second potential terminal, the first and second switches being switched in response to an input signal BUZ to be decayed to produce an output signal at a given amplitude. A plurality of third switches TN1-TN7 each having a series resistance R1-R7 are sequentially switched by a shift register SR1-SR6, Figure 1 or counter (Bc1-Bc3 Figure 3) to cause the output signal to decay from the given amplitude. <IMAGE>

Description

SPECIFICATION Electronic signal decay control circuit This invention relates to a control circuit for causing slow decay of an electronic signal.

Digital watches, electronic calculators and the like which are able to generate sounds have recently been developed. Digital watches produce a continuous sound at some frequency or a melody from a speaker at a preset alarm time. Electronic calculators produce sound as the keys are operated. Thus, electronic instruments have been deveioped to apeal to the user not only visually but also aurally. However, these electronic sounds are generated by a simple output circuit, so they are jarring sounds which do not sound natural. Many users have felt annoyed or uncomfortable on hearing melody sounds generated from the output circuit because they are so different from the soft natural sounds produced by musical instruments.

These jarring electronic sounds can be modified to sound more like natural sounds by processing them in a suitable circuit having a function which causes gentle decay of the sounds. This may be accomplished by using a waveform adjusting circuit comprising capacitors and resistors, but such a circuit is unsuitable for a monolithic integrated circuit construction.

An object of this invention is to provide an improved electronic signal decay control circuit which is suitable for incorporation in a monolithic integrated circuit.

According to the present invention, an electronic signal decay control circuit for receiving an input signal and producing a decaying output signal comprises first switching means switchable between on and off states and a series resistance connected between a first electric potential terminal and an output terminal, second switching means switchable between on and off states and connected between said output terminal and a second electric potential terminal, a plurality of third switching means each switchable between on and off states and each having a resistance in series therewith, each third switching means being connected in parallel to said second swiching means between said output terminal and said second electric potential terminal, said first and second switching means being switched in response to said input signal to produce an output signal at a given amplitude, and control means for sequentially switching said third switching means so that said output signal decays from said given amplitude.

The first and second switching means are operated in response to an input signal to produe an output of a given amplitude at the output terminal. The third switching means are selectively controlled to produce an output signal which slowly decays from the given amplitude.

In order that the invention may be more readily understood, it will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of one embodiment of this invention, Figure 2 is a waveform chart to illustrate operation of the circuit of Figure 1, Figure 3 is a circuit diagram of a preferred embodiment of this invention, Figure 4 is a waveform chart to illustrate operation of the circuit of Figure 3, and Figure 5 is a diagrammatic circuit diagram of an application of this invention.

Referring now to Figure 1, there is shown a circuit of the invention. A P-channel type MOS transistor TPo serving as a first switching element has a resistance R0 in series therewith and is connected between an output terminal VAH and a terminal to which a voltage source VDD is applied. An N-channel type MOS transistor TNX serving as a second switching element and N-type MOS transistors TN1 to TN7 serving as third switching elements each having a series resistance R1 to R7, respectively, are connected in parallel between output terminal VAH and a ground terminal. Transistor TNX does not have a series resistance.A buzzer signal (4kHz) BUZ is applied to the gate electrode of transistor TPo and TNX. One bit shift registers SR1 to SRe are provided with cascade connection and form a six bit shift register in which data signal Si is shifted by a timing pulse CLOCK. Input/output signals Si to S7 of bit shift registers SR1 to SR6 are applied to the gate electrodes of transistors TN1 to TN7 respectively.

In this embodiment, the value of resistances R1 to R7 are established in the following relation: R1 > R2 > R3 > R4 > R5 > R6 > R7 The resistances of transistors TPo and TN1 to TN7 in their on state are negligibly small compared to each of resistances R0 and R1 to R7.Consequently, the combined series resistances are according to the following relations: R0 + {(on-resistance of transistor TP,))=R, R1 + {(on-resistance of transistor TN1))=R, R2 + {(on-resistance of transistor TN2))=R2 R3 + {(on-resistance of transistor TN3))=R3 R4 + {(on-resistance of transistor TN4))= R4 R5 + {(on-resistance of transistor TN5))=R5 R5 + {(on-resistance of transistor TNG))=R, R7 + {(on-resistance of transistor TN7))=R7 The manner of operation of the circuit shown in Figure 1 will be explained particularly with reference to the waveform chart in Figure 2. When timing pulses CLOCK and data signals S1 are applied to the respective CLOCK and S1 terminals, shifted signals S1 to S7 are produced and these signals Si to S7 are applied to the gate electrodes of transistors TN1 to TN7. As a result, output voltages VAH0 to VAH7 at times to to t7 are produced as follows: (1) Output VAH0 at time to: Initially, all the transistors TN1 to TN7 are in their off state and the potentials of data signals S1 to S7 are at ground level GND. Buzzer signal BUZ is now applied, shifting between source voltage VDD and ground GND.

When the buzzer signal TPo is in its off state and transistorTNx is in its on state, so output VAHo is at ground level GND. Thereafter, when buzzer signal BUZ is at ground level GND, transistor TNX is shifted to its off state and transistorTPOto its on state, so output VAH0 becomes equal to the source voltage VDD. Thus, output VAH swings between ground level GND and source voltage VDD at a frequency of 4kHz.

(2) OutputVAH1 attimet1: In this time, data signal S1 is VDD and S2 to S7 are at ground level GND, so transistor TN1 is in its on state and transistors TN2 to TN7 are in their off state. When buzzer signal BUZ is VDD, transistors TNX and TN1 are in the on state, so output VAH1 becomes ground level GND. On the other hand, when buzzer signal BUZ is at ground level, transistors TPo and TB1 are in their on state, so output VAH1 becomes the voltage which is produced as the divided voltage of source voltage VDD by resistances R0 and R1.This voltage is given by the following equation: VAH1 = R1/(RO + Ri) X VDD( < VDD) Thus, output VAH swings between ground level GND and voltage VAH1.

(3) Output VAH2 at time t2: Output VAH2 is produced as the divided voltage of source voltage VDD by resistances R0 and R2.

VAH2 = R2/(RO + R2) X VDD ( < VAH1) (4) OutputVAH3 attimet3: Output VAH3 is produced as the divided voltage of source voltage VDD by resistance R0 and R3.

VAH3 = R3/(Ro + R3) x VOD ( < VAH2) (5) Output VAH4 at time 4: Output VAH4 is produced as the divided voltage of source voltage VDD by resistances R0 and R4.

VAH4 = R4(Ro + R4) x VDD ( < VAH3) (6) Output VAH5 at time t5: Output VAH5 is produced as the divided voltage of source voltage VDD by resistances R0 and R5.

VAH5 = R5/(Ro + R5) x VDD ( < VAH4) (7) Output VAH6 at times t6: Output VAH6 is produced as the divided voltage of source voltage VDD by resistances R0 and R5.

VAH6 = R6/(RO + R6) X VDD ( < VAH5) (8) Output VAH7 attimet7: Output VAH7 is produced as the divided voltage of source voltage VDD by resistances R0 and R7.

VAH7 = R7/(Ro + R7) x VoD ( < VAH5) In consequence, output VAH is expressed by the following relation: VAHo > VAHl > VAH2 > VAH3 > VAH4 > VAH5 > VAH6 > VAH7 Initially, the output swings fully between VDD and GND on the buzzer signal of 4kHz, and thereafter the height of the swing decreases gradually. However, the frequency of the buzzer signal does not change so the strength of the sound of the buzzer signal decreases gently without changing the tone of the sound.

Figures 3 and 4 illustrate another embodiment of this invention. Referring to the drawings, similar elements are assigned the same reference numbers as in Figures 1 and 2. This second embodiment is different from the first embodiment shown in Figure 1 in that the number of switching transistors is reduced and three binary counters are used in place of the shift registers. The output terminals Q of binary counters BC1 to BC3 (flipflops) are connected to the gate electrodes of transistors TN1 to TN3 respectively. Timing pulse CLOCK is applied to the input terminal T of binary counter BC1 through an inverter I and another output term inal Q of BC1 is connected to the input terminal T of second binary counter BC2, and so forth.

In this embodiment, the values of resistances R1 to R3 are established according to the following relation: R1 > R2 > R3 The resistance of transistors TPo and TN1 to TN3 when they are switched on is negligibly small compared to resistances R0 and R1 to R3. Consequently, series resistance are determined according to the following relations: R0 + {(on-resistance of transistor TP0}}=R0 R1 + {(on-resistance of transistor TP1)}=R1 R2 + {(on-resistance oftransistorTP2)}-R2 R3 + ((on-resistance of transistor TP3)}#R3 The manner of operation of the embodiment of the invention described in Figure 3 will be explained particularly with reference to the waveform chart in Figure 4.Signals S1 to S3 are produced from binary counters BC1 to BC3 in response to timing pulse CLOCK, and are applied to the gate electrodes of transistors TN1 to TN3, respectively. As a result, output voltages VAHo to VAH7 at times to to t7 are produced as follows.

The explanation of operation is brief to avoid repetition with respect to the first embodiment.

(1) Output VAH0 at time to: When buzzer signal BUZ is at ground level GND, only transistor TP, is in its on state, so output VAH0 becomes VDD. Thus, VAH swings between GND and VDD at 4kHz, (2) OutputVAH1 at time t1: TransistorsTPO and TN1 are in their on state, so outputVAH1 becomes the following: VAH1 = R1/(Ro + R1) x VDD ( < VDD) (3) Output VAH2 at time t2: Transistors TPo and TN2 are in their on state, so output VAH2 becomes the following: VAH2 R2/(RO+ R2)X VDD ( < VAH1) (4) Output VAH3 at time t3:: Signals S1 and S2 are VDD and S3 is GND, so transistors TPo, TN1 and TN2 are in their on state. Thus, output VAH3 becomes the following: VAH3 = R1R2/(Ro(R1+R2)+R1R2) X VDD ( < VAH2) (5) OutputVAH4attimet4: Transistors TPo and TN3 are in their on state, so output VAH4 becomes the following: VAH4 = R3/(Ro + R3) x VDD ( < VAH3) (6) Output VAH5 at time t5: Signals S1 and S3 are VDD and S2 is GND, so transistors TPo,TN1 and TN3 are in their on state, so output VAH5 becomes the following:: VAH5 = RlR3/(Ro(R1+R3)+R1R3) X VDD ( < VAH4) (7) Output VAH6 at time t6: Signals S2 to S3 are all VDD and S1 is GND, so transistors TPo, TN2, and TN3 are in their on state, so output VAH6 becomes the following: VAH5 = R2R3/(R,(R2+R3)+R2R3) X VDD ( < VAH5) (8) Output VAH7 attimet7: Signals S1 to S3 are all VDD, SO transistors TP and TN1 to TNs are all in their on state, so output VAH7 becomes the following: VAH7 = R1 R2R3/(R1 R2+R2R3+R1 R3)) XVDD ( < VAH6) In consequence, output VAH is expressed as the following relation:: VAHo > VAH1 > VAH2 > VAH3 > VAH4 > VAH5 > VAH6 > VAH7 Thus, the circuit of this embodiment also produces a signal which decays gently without altering the frequency of the buzzer signal.

The features of these embodiments of this invention are as follows: (1) Output voltages VAH are determined only by resistance divisional voltages of the source voltage using linear resistance R0 to R7, because the dimensions of switching MOS transistors TPo and TN1 to TN7 are made large and the on resistances are set as small as possible. The circuit design is very simpie.

(2) Output voltages VAH can be set precisely since MOS resistances, which are influenced by the manufacturing process, are negligible.

(3) In the first embodiment of this invention shown in Figure 1, each output VAH corresponds one by one to each resistance, so each is produced independently of other resistances. Therefore establishing the circuit constants and very precisely setting the outputs VAH is easy.

(4) In the second embodiment of this invention shown in Figure 3, eight levels of output are produced by the combination of three resistances. If the number of resistances is N, then 2N output levels of VAH are produced.

Figure 5 illustrates a peripheral circuit of an application of this invention. Circuit 11 has an output VAH which decays slowly as described above and the output is applied to an output transistor 13 connected in series with a speaker 12 causing the speaker to be driven. A resistance 14 adjusts decay of the output waveform.

This invention is not limited to the above-mentioned embodiments and the construction of the circuit is not limited to the CMOS-type. The disclosed voltage dividing elements are linear resistances and switching MOS transistors, but MOS resistances and switching MOS transistors can be used, or only MOS transistors having both functions. The shift registers and the binary counters do not use the reset terminais, but can be reset without the buzzer signal. The above-mentioned embodiments are described using a constant frequency buzzer signal, although a variable frequency signal is possible to produce a musical sound.

In the above-mentioned embodiments of this invention, the electric signal such as an electronic sound signal is naturaliy decayed and the reverberations are produced by the simple circuit.

Although only a few exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the following

Claims (6)

claims. CLAIMS

1. An electronic signal decay control circuit for receiving an input signal and producing a decaying output signal comprising: first switching means switchable between on and off states and a series resistance connected between a first electric potential terminal and an output terminal, second switching means switchable between on and off states and connected between said output terminal and a second electric potential terminal, a plurality of third switching means each switchable between on and off states and each having a resistance in series therewith, each third switching means being connected in parallel to said second switching means between said output terminal and said second electric potential terminal, said first and second switching means being switched in response to said input signal to produce an output signal at a given amplitude, and control means for sequentially switching said third switching means so that said output signal decays from said given amplitude.

2. A circuit as claimed in claim 1, wherein said control means is a shift register connected to each of said third switching means.

3. A circuit as claimed in claim 1, wherein each of said third switching means has a binary counter constituting a control means connected thereto.

4. A circuit as claimed in claim 1,2 or 3, wherein said first switching means is a first type MOS transistor and said second and third switching means are second type MOS transistors.

5. A circuit as claimed in claim 1, 2 or 3, wherein means providing an electronic sound signal is connected to the first and second switching means.

6. An electronic signal decay control circuit substantially as hereinbefore described with reference to Figures 1 and 2 or Figures 3 and 4 of the accompanying drawings.