JP3758580B2 - LCD drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal driving circuit for driving a liquid crystal panel.
[0002]
[Prior art]
In recent years, the use of liquid crystal panels in mobile terminals such as mobile phones has increased rapidly, and it has become indispensable to be driven by batteries for a long time. Therefore, it is important to reduce power consumption in a liquid crystal driving circuit for driving the liquid crystal panel.
[0003]
In the following, a case where the conventional liquid crystal drive circuit has 64 gradations as the display gradation of the liquid crystal panel and the number of liquid crystal drive outputs is n is described.
[0004]
FIG. 6 is a circuit diagram of a conventional liquid crystal driving circuit. A gradation potential generating circuit 50 for generating gradation potentials V1 to V64, resistors 51 to 53 constituting the gradation potential generating circuit 50, and a gradation potential V1. Are selected by gradation selection signals CTL1 to CTLn, and gradation potentials VS1 to VSn selected by the gradation selection circuits 30 to 32 are subjected to low impedance conversion. It comprises buffers 33 to 35 that output as liquid crystal drive outputs OUT1 to OUTn. FIG. 7 is a diagram showing the relationship between the gradation potential applied to the liquid crystal panel and the transmittance of the liquid crystal panel. In order to perform gradation display smoothly, resistors 51 to 51 for generating gradation potentials V1 to V64 are shown. The ratio between 53 is determined.
[0005]
Next, the output operation of the liquid crystal drive outputs OUT1 to OUTn will be described for the liquid crystal drive circuit configured as described above.
[0006]
First, the gradation potential generation circuit 50 generates gradation potentials V1 to V64 for gradation display of the liquid crystal panel, and the gradation selection circuit 30 generates one gradation potential among the gradation potentials V1 to V64. This is selected by the gradation selection signal CTL1 and input to the buffer 33 as the gradation potential VS1. In the buffer 33, the inputted gradation potential VS1 is subjected to low impedance conversion and then output to the liquid crystal panel as the liquid crystal drive output OUT1. Similarly, OUT2 to OUTn are also output.
[0007]
[Problems to be solved by the invention]
In this conventional liquid crystal driving circuit, when the gradation selection circuits 30 to 32 are switched, the gradation potential sufficient to charge / discharge the parasitic capacitance in the gradation selection circuits 30 to 32 and the input capacitance of the buffers 33 to 35 is achieved. In order to ensure the current capability of V1 to V64, it is necessary to reduce the resistance values of the resistors 51 to 53 to some extent. For this reason, the through current I10 flowing from the gradation reference potential input VH to the gradation reference potential input VL via the resistors 51 to 53 is large, and there is a first problem that power consumption cannot be reduced.
[0008]
In addition, since the relationship between the gradation potential applied to the liquid crystal panel and the transmittance of the liquid crystal panel is different for each type of liquid crystal panel (transmission type panel, reflection type panel, transflective type panel, each panel manufacturer, etc.), The second problem of not being able to handle various liquid crystal panels with the same circuit configuration and the change in the appearance of the liquid crystal panel display in the middle because the gradation display cannot be changed during the liquid crystal panel display. There was a third problem that could not be done.
[0009]
The present invention solves the above-described conventional problems, has low power consumption, can cope with transmittance characteristics of various liquid crystal panels, and can change the appearance of the liquid crystal panel display by changing the gradation display in the middle. An object is to provide a liquid crystal driving circuit.
[ 0010 ]
[Means for Solving the Problems]
In the liquid crystal driving circuit according to the present invention, a plurality of gradation potentials are generated by a first resistance dividing circuit from a plurality of gradation reference potential inputs, and one of the plurality of gradation potentials is selected as a plurality of gradations. In a liquid crystal driving circuit that supplies a liquid crystal panel as a plurality of liquid crystal driving outputs through a plurality of impedance reduction circuits after selection by the circuit, a second potential that generates the same potential as the predetermined potential in the first resistance dividing circuit A resistance divider circuit; a buffer that receives the predetermined potential generated by the second resistor divider circuit as an input; and outputs the reduced potential; an output of the buffer; and the predetermined potential portion in the first resistor divider circuit; And a plurality of second transfer gates for connecting the second resistance dividing circuit and the plurality of gradation reference potential inputs, and the first resistance component. Only when it is desired to lower the impedance of the circuit, the first transfer gate and the plurality of second transfer gates are turned on, and the output of the buffer and the predetermined potential portion in the first resistance divider circuit are connected. The second resistor divider circuit and the plurality of gradation reference potential inputs are connected, and the buffer is also turned off when the first transfer gate is turned off. Is.
[ 0011 ]
According to the present invention, the power consumption of the first resistance divider circuit is reduced, the power consumption of the buffer is reduced, and a buffer having a large offset voltage, which is the difference between the output potential and the input potential, is used as the buffer. In addition , the power consumption of the second resistor divider circuit can be reduced.
[ 0012 ]
In another liquid crystal driving circuit according to the present invention, a plurality of gradation potentials are generated from a plurality of gradation reference potential inputs by a first resistance dividing circuit, and one of the plurality of gradation potentials is plural. In a liquid crystal driving circuit that supplies a plurality of liquid crystal driving outputs to a liquid crystal panel through a plurality of impedance reduction circuits after selection by the gradation selection circuit, a source and a drain are connected to a predetermined potential portion in the first resistance dividing circuit. One of the N-channel MOS transistors connected to the other and a first power supply to the other, and one of the source and drain connected to the predetermined potential portion in the first resistor divider circuit, and the other A first potential that is lower than the sum of the threshold voltage of the N-channel MOS transistor and the predetermined potential, and a P-channel MOS transistor having a second power source connected to the P-channel MOS transistor; A second resistance dividing circuit for generating a second potential higher than the sum of the absolute value of the threshold voltage of the channel MOS transistor and the predetermined potential, and the gate of the N-channel MOS transistor has the second One potential is connected, and the second potential is connected to the gate of the P-channel MOS transistor.
[ 0013 ]
According to the present invention, the with the first power consumption of the resistance division circuit can, it can be realized in control without a small circuit scale.
[ 0014 ]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Figure 1 shows a circuit diagram of the first liquid crystal driving circuit of the real 施形 condition of the present invention. In the present embodiment, a case will be described in which the number of liquid crystal drive outputs is n, and the display gradation of the liquid crystal panel is 64 gradations, and the 64 gradation potentials are selected from 8 basic potentials.
[ 0015 ]
Reference numeral 1 denotes a resistance dividing circuit having a function of generating gradation basic potentials V1, V2 (1) to V2 (8), V3 (1) to V63 (8), and V64 by resistors 2-7. Reference numeral 10 denotes a resistance divider circuit, which has a function of generating a potential VM0 equal to a predetermined potential VM in the resistor divider circuit 1 by means of the resistors 11 and 12. Reference numeral 13 denotes a transfer gate, which is a gradation reference potential input VH and a resistor. 11 is a transfer gate, and 14 is a transfer gate, and has a function of connecting the gradation reference potential input VL and the resistor 12. Reference numeral 15 denotes a buffer, which has a function of reducing and outputting the impedance with the potential VM0 as an input, and 16 is a transfer gate, which has a function of connecting the output of the buffer 15 to the potential VM in the resistance dividing circuit 1. Reference numerals 20 to 22 denote potential selection circuits, each of which is selected from eight potentials among the gradation basic potentials V2 (1) to V2 (8) and V3 (1) to V63 (8). And has a function of outputting as gradation potentials V2 to V63. Reference numerals 30 to 32 denote gradation selection circuits, which have a function of selecting one of the gradation potentials V1 to V64 and outputting it as gradation potentials VS1 to VSn, and 33 to 35 are buffers. It has a function of outputting as liquid crystal drive outputs OUT1 to OUTn after low impedance conversion using the potentials VS1 to VSn as inputs.
[ 0016 ]
Next, the gradation potential selection operation of the liquid crystal driving circuit having this configuration will be described.
[ 0017 ]
The relationship between the gradation potential applied to the liquid crystal panel and the transmittance of the liquid crystal panel differs depending on the type of liquid crystal panel (transmission type panel, reflection type panel, transflective type panel, each panel manufacturer, etc.). In order to generate the gradation potential V2, first, the gradation basic potential V2 (1) corresponding to the transmittance characteristic 1 is obtained when the transmittance characteristic of the pixel is between the transmittance characteristics 1 to 8 in FIG. 8 to the gray scale basic potential V2 (8) corresponding to the transmittance characteristic 8 are generated by the resistance dividing circuit 1, and the gray scale basic potential V2 (1) is generated. ) To V2 (8), one potential corresponding to the transmittance characteristic of the liquid crystal panel is selected by the potential selection circuit 20 using the gradation basic potential selection signal SEL2, and is output as the gradation potential V2. In this case, the transmittance of the gradation basic potential V2 (1) corresponding to the transmittance characteristic 1 and the gradation basic potential V2 (8) corresponding to the transmittance characteristic 8 are equal. Similarly, gradation potentials V3 to V63 are also generated.
[ 0018 ]
By doing so, it is possible to cope with the transmittance characteristics of various liquid crystal panels, and in the middle, the gradation basic potential V2 by the gradation basic potential selection signals SEL2 to SEL63 by the potential selection circuits 20-22. If the selection potential of (1) to V63 (8) is changed, the gradation display can be changed and the appearance of the liquid crystal panel display can be changed.
[ 0019 ]
Next, the output operation of the liquid crystal drive outputs OUT1 to OUTn will be described with reference to FIG. 2 of the timing chart.
[ 0020 ]
First, in accordance with the transmittance characteristics of the liquid crystal panel, the potential selection circuits 20 to 22 use the gradation basic potential selection signals SEL2 to SEL63 to adjust the eight potentials of the gradation basic potentials V2 (1) to V63 (8). One of these potentials is selected and output as gradation potentials V2 to V63.
[ 0021 ]
In the first period T1, the transfer gates 13, 14, and 16 are turned off by the control signals SWON, RON1, and RON2, and the buffer 15 is turned off by the control signal BUFON. Further, the gradation selection circuits 30 to 32 select one of the gradation potentials V1 to V64 (selection states 1a to na) based on the gradation selection signals CTL1 to CTLn, and the gradation potentials VS1 to VSn are selected. Input to buffers 33-35. The buffers 33 to 35 are in a state where the input gradation potentials VS1 to VSn are converted to low impedance and then output to the liquid crystal panel as liquid crystal drive outputs OUT1 to OUTn.
[ 0022 ]
In the period T2, the transfer gates 13 and 14 are turned on by the control signals RON1 and RON2, and the buffer 15 is turned on by the control signal BUFON.
[ 0023 ]
Next, in the period T3, the transfer gate 16 is turned on by the control signal SWON, and the output of the buffer 15 is supplied to the potential VM portion in the resistance dividing circuit 1.
[ 0024 ]
In the subsequent period T4, due to the change in the gradation selection signals CTL1 to CTLn, the gradation selection circuits 30 to 32 reselect one of the gradation potentials V1 to V64 (selection states 1b to nb). The adjusted potentials VS1 to VSn are input to the buffers 33 to 35. In the buffers 33 to 35, the inputted gradation potentials VS1 to VSn are subjected to low impedance conversion, and then output to the liquid crystal panel as liquid crystal drive outputs OUT1 to OUTn. When the gradation selection circuits 30 to 32 are switched, a current for charging / discharging the parasitic capacitance in the gradation selection circuits 30 to 32 and the input capacitance of the buffers 33 to 35 is resistance through the potential selection circuits 20 to 22. Supplied from the dividing circuit 1.
[ 0025 ]
In the period T5, the transfer gate 16 is turned off by the control signal SWON, and the output of the buffer 15 to the potential VM portion in the resistance dividing circuit 1 is lost.
[ 0026 ]
In the next period T1, the transfer gates 13 and 14 are turned off by the control signals RON1 and RON2, and the buffer 15 is turned off by the control signal BUFON.
[ 0027 ]
By repeating the periods T1 to T5 as described above, the output operation of the liquid crystal drive outputs OUT1 to OUTn is performed.
[ 0028 ]
As described above, when the gradation selection circuits 30 to 32 are switched, the potential VM is supplied to the resistance dividing circuit 1 by the buffer 15 with a low impedance, so that the series resistance in the resistance dividing circuit 1 is compared with the conventional case. The value can be increased. For example, when the potential VM is a half potential between the gradation reference potential inputs VH and VL, the series resistance value in the resistance dividing circuit 1 can be doubled compared to the conventional case. The through current I2 flowing through 1 can be halved compared to the conventional case, and the power consumption can be reduced. Further, when the gradation potentials V1 to V64 after switching of the gradation selection circuits 30 to 32 are stable, the supply of the potential VM from the buffer 15 is stopped, and the potential VM portion in the resistance dividing circuit 1 has a resistance division ratio. Therefore, even a buffer having a large output offset voltage (difference between the output potential of the buffer 15 and the input potential) due to the circuit configuration (such as a voltage follower circuit using an operational amplifier) can be used as the buffer 15. . Further, when the buffer 15 is not used, it is stopped (stopped by the control signal BUFON) and the supply of the gradation reference potential inputs VH and VL to the resistance dividing circuit 10 is stopped (the transfer gates 13 and 14 are turned off). Since the through current I1 in the resistance dividing circuit 10 is eliminated, the power consumption can be further reduced.
[ 0029 ]
Note that in this embodiment, the display gradation of the liquid crystal panel is 64 gradations, and the case where the 64 gradation potential is selected from the eight potentials of the basic potential has been described. However, multi-gradation display other than 64 gradations is described. In this case, the same operation can be explained. Further, the same operation can be explained even when the gradation potential is selected from the m potentials of the basic potential. In this case, the potential selection circuit may be configured to select one potential from m potentials.
[ 0030 ]
(Second Embodiment)
Figure 4 shows a circuit diagram of a second liquid crystal driving circuit of the real 施形 condition of the present invention. In the present embodiment, a case will be described in which the number of liquid crystal drive outputs is n, and the display gradation of the liquid crystal panel is 64 gradations, and the 64 gradation potentials are selected from 8 basic potentials.
[ 0031 ]
The functions of the resistance dividing circuit 1, resistors 2 to 7, potential selection circuits 20 to 22, gradation selection circuits 30 to 32, and buffers 33 to 35 are the same as those in the first embodiment.
[ 0032 ]
Reference numeral 40 denotes a resistor divider circuit, which is composed of resistors 41 to 43, and has a function of generating the potential VGN and the potential VGP with the gradation reference potential inputs VH and VL as inputs. Reference numeral 45 denotes an N-channel MOS transistor having a potential VGN connected to the gate input, a power supply VH0 connected to one of the source and drain inputs, and a potential VM portion in the resistance dividing circuit 1 connected to the other. A P-channel MOS transistor 46 has a potential VGP connected to the gate input, a power source VL0 connected to one of the source and drain inputs, and a potential VM portion in the resistance dividing circuit 1 connected to the other. When the threshold voltage of the N-channel MOS transistor 45 is VTN, the potential VGN has a relationship of (VGN <VM + VTN), and the power supply VH0 has a relationship of (VH0 ≧ VM). When the absolute value of the threshold voltage of the P-channel MOS transistor 46 is | VTP |, the potential VGP has a relationship of (VGP> VM− | VTP |), and the power supply VL0 is (VL0 ≦ VM). Are in a relationship.
[ 0033 ]
Next, the gradation potential selection operation of the liquid crystal driving circuit having this configuration will be described.
[ 0034 ]
The relationship between the gradation potential applied to the liquid crystal panel and the transmittance of the liquid crystal panel differs depending on the type of liquid crystal panel (transmission type panel, reflection type panel, transflective type panel, each panel manufacturer, etc.). In order to generate the gradation potential V2, first, the gradation basic potential V2 (1) corresponding to the transmittance characteristic 1 is obtained when the transmittance characteristic of the pixel is between the transmittance characteristics 1 to 8 in FIG. 8 to the gray scale basic potential V2 (8) corresponding to the transmittance characteristic 8 are generated by the resistance dividing circuit 1, and the gray scale basic potential V2 (1) is generated. ) To V2 (8), one potential corresponding to the transmittance characteristic of the liquid crystal panel is selected by the potential selection circuit 20 using the gradation basic potential selection signal SEL2, and is output as the gradation potential V2. In this case, the transmittance of the gradation basic potential V2 (1) corresponding to the transmittance characteristic 1 and the gradation basic potential V2 (8) corresponding to the transmittance characteristic 8 are equal. Similarly, gradation potentials V3 to V63 are also generated.
[ 0035 ]
By doing so, it is possible to cope with the transmittance characteristics of various liquid crystal panels, and in the middle, the gradation basic potential V2 by the gradation basic potential selection signals SEL2 to SEL63 by the potential selection circuits 20-22. If the selection potential of (1) to V63 (8) is changed, the gradation display can be changed and the appearance of the liquid crystal panel display can be changed.
[ 0036 ]
Next, the output operation of the liquid crystal drive outputs OUT1 to OUTn will be described with reference to FIG. 5 of the timing chart.
[ 0037 ]
First, in accordance with the transmittance characteristics of the liquid crystal panel, the potential selection circuits 20 to 22 use the gradation basic potential selection signals SEL2 to SEL63 to adjust the eight potentials of the gradation basic potentials V2 (1) to V63 (8). One of these potentials is selected and output as gradation potentials V2 to V63.
[ 0038 ]
In the first period T1, the gradation selection circuits 30 to 32 select one of the gradation potentials V1 to V64 (selection states 1a to na) by the gradation selection signals CTL1 to CTLn, and the gradation potentials. VS1 to VSn are input to the buffers 33 to 35. The buffers 33 to 35 are in a state where the input gradation potentials VS1 to VSn are converted to low impedance and then output to the liquid crystal panel as liquid crystal drive outputs OUT1 to OUTn.
[ 0039 ]
In the period T2, the gradation selection circuits 30 to 32 reselect one of the gradation potentials V1 to V64 (selection states 1b to nb) due to the change in the gradation selection signals CTL1 to CTLn. The potentials VS1 to VSn are input to the buffers 33 to 35. In the buffers 33 to 35, the inputted gradation potentials VS1 to VSn are subjected to low impedance conversion, and then output to the liquid crystal panel as liquid crystal drive outputs OUT1 to OUTn. When the gradation selection circuits 30 to 32 are switched, a current for charging / discharging the parasitic capacitance in the gradation selection circuits 30 to 32 and the input capacitance of the buffers 33 to 35 is resistance through the potential selection circuits 20 to 22. The potential of the potential VM portion is temporarily raised and lowered by this current supplied from the dividing circuit 1. At this time, the N-channel MOS transistor 45 or the P-channel MOS transistor 46 is turned on, and the potential VM portion is changed. Return to the original potential determined by the resistance ratio of resistors 2-7. For example, when the potential VM portion is shifted to the low potential side, (potential VGN−potential VM) becomes larger than the threshold voltage VTN of the N-channel MOS transistor 45, and therefore the N-channel MOS transistor 45 is turned on, After the potential VM is raised to the high potential side until VM> VGN−VTN), the N-channel MOS transistor 45 is turned off. At this time, the P-channel MOS transistor 46 is in an off state. Further, when the potential VM portion is swung to the high potential side, (potential VM−potential VGP) becomes larger than the absolute value | VTP | of the threshold voltage of the P-channel MOS transistor 46. Therefore, the P-channel MOS transistor 46 Is turned on and the potential VM is lowered to the low potential side until (VM <VGP + | VTP |), and then the P-channel MOS transistor 46 is turned off. At this time, the N-channel MOS transistor 45 is in an off state.
[ 0040 ]
As described above, when the gradation selection circuits 30 to 32 are switched, the N-channel MOS transistor 45 or the P-channel MOS transistor 46 is turned on to return the potential VM portion to the original potential with low impedance. Compared to the above, the series resistance value in the resistance dividing circuit 1 can be increased without additional control. For example, when the potential VM is a half potential between the gradation reference potential inputs VH and VL, the series resistance value in the resistance dividing circuit 1 can be doubled compared to the conventional case. The through current I2 flowing through 1 can be halved compared to the conventional case, and the power consumption can be reduced. Further, it can be realized with a smaller circuit configuration than that of the first embodiment.
[ 0041 ]
Note that in this embodiment, the display gradation of the liquid crystal panel is 64 gradations, and the case where the 64 gradation potential is selected from the eight potentials of the basic potential has been described. However, multi-gradation display other than 64 gradations is described. In this case, the same operation can be explained. Further, the same operation can be explained even when the gradation potential is selected from the m potentials of the basic potential. In this case, the potential selection circuit may be configured to select one potential from m potentials.
[ 0042 ]
【The invention's effect】
According to the liquid crystal driving circuit of the present invention, the first resistor divider circuit can be reduced in power consumption, the buffer power consumption can be reduced, and the offset voltage which is the difference between the output potential and the input potential can be used as a buffer. A large buffer can be used , and the power consumption of the second resistor divider circuit can be reduced.
[ 0043 ]
According to the liquid crystal driving circuit according to the present invention, low power consumption along with possible of the first resistive divider circuit as compared with the conventional, can be realized in control without a small circuit scale.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention according to claims 1 to 4 and 6; FIG. 2 is a timing chart according to an embodiment of the present invention according to claims 1 to 4; A graph showing the relationship between the gradation potential and the transmissivity of the liquid crystal panel in an embodiment of the present invention as set forth in claims 1 to 4 and 6. FIG. 4 in an embodiment of the present invention as set forth in claims 5 and 6. FIG. 5 is a timing diagram in one embodiment of the present invention according to claim 5. FIG. 6 is a circuit diagram of a conventional liquid crystal driving circuit. FIG. 7 is a gradation potential of a conventional liquid crystal driving circuit. Graph showing the relationship between the liquid crystal panel and the transmittance of the liquid crystal panel
1, 10, 40, 50 Resistance dividing circuit 2-7, 11, 12, 41-43, 51-53 Resistance 13, 14, 16 Transfer gate 15, 33-35 Buffer 20-22 Potential selection circuit 30-32 gradation Selection circuit 45 N channel type MOS transistor 46 P channel type MOS transistor VH, VL Gradation reference potential input RON1, RON2, SWON, BUFON Control signal SEL1 to SEL63 Gradation basic potential selection signal CTL1 to CTLn Gradation selection signal V1 to V63 , VS1 to VSn Gradation potential V2 (2) to V63 (8) Gradation basic potential VM0, VM potential VGN, VGP Gate potential VH0, VL0 Power supply I1, I2, I10 Through current

Claims (2)

In a liquid crystal driving circuit that supplies a plurality of gradation potentials generated by a first resistance dividing circuit from a plurality of gradation reference potentials to a liquid crystal panel as a plurality of liquid crystal driving outputs, the predetermined potential in the first resistance dividing circuit is A second resistor dividing circuit that generates the same potential; a buffer that receives the predetermined potential generated by the second resistor dividing circuit as an input; and outputs the reduced potential; and an output of the buffer and the first resistor divider A first transfer gate that connects the predetermined potential portion in the circuit, and a plurality of second transfer gates that connect the second resistance dividing circuit and the plurality of gradation reference potential inputs, wherein when the gradation potentials to be the liquid crystal drive output is switched, the plurality of gradation reference potential and said second resistor divider circuit by turning on said plurality of second transfer gate After connecting the input, the first by turning on the transfer gate is connected with said predetermined potential areas of the output and the first resistor divider circuit of the buffer, turns off the first transfer gate liquid crystal drive circuit after, characterized by turning off the second transfer gate.   In a liquid crystal driving circuit that supplies a plurality of gradation potentials generated by a first resistance dividing circuit from a plurality of gradation reference potentials to a liquid crystal panel as a plurality of liquid crystal driving outputs, a predetermined potential portion in the first resistance dividing circuit One of the source and the drain is connected to the N-channel MOS transistor having the first power supply connected to the other, and either the source or the drain is connected to the predetermined potential portion in the first resistor divider circuit. And a P-channel MOS transistor connected to the other power source, and generates a first potential lower than the sum of the threshold voltage of the N-channel MOS transistor and the predetermined potential. A second resistance divider circuit for generating a second potential that is higher than the sum of the absolute value of the threshold voltage of the P-channel MOS transistor and the predetermined potential, Le type the first potential is connected to the gate of the MOS transistor, a liquid crystal drive circuit, characterized in that for connecting the second potential to the gate of the P-channel type MOS transistor.

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