JP3233580B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit for converting the level of an input signal to a different level.

[0002]

2. Description of the Related Art When driving a display element such as a liquid crystal display panel, desired display is performed by applying a high voltage to the display element. When the display panel is, for example, an active matrix display panel, a gate driver and a source driver are provided to drive the display panel.
If the configuration of each driver is a high withstand voltage configuration, the structure of each transistor in the circuit must be, for example, a double diffusion structure, which increases the configuration of the driver. In order to prevent the configuration of the driver from becoming large, processing is performed at a relatively low voltage in the signal processing stage, and the display element is driven by converting the voltage level immediately before applying the voltage to the display element.

FIG. 33 shows a configuration of a gate driver 11 which is a typical conventional example, FIG. 34 shows a level shifter 13 included in the gate driver 11, and FIG. 35 shows a relationship between inputs and outputs in the gate driver 11. .

[0004] As shown in FIG.
Is configured to include a shift register 12, a level shifter 13, and an output buffer 14. The gate driver 11 is connected to, for example, n electrodes.

The gate driver 11 is supplied with a plurality of voltages from a power supply circuit (not shown). Since the gate driver 11 is a gate driver that outputs a positive voltage based on a negative voltage or a ground voltage, a voltage VSS on the negative power supply side is commonly applied to each component. The output buffers 14 are supplied with the voltages VDD and VSS, the level shifter 13 is supplied with the voltages VDD and VSS, and the shift register 12 is supplied with the voltages VSS and VCC.
Is supplied. For example, the voltage VDD is 30 V, the voltage VCC is 5 V, and the voltage VSS is 0 V, that is, the ground voltage.

The shift register 12 has a clock signal C
K and the start pulse S indicating the signal level shown in FIG.
Each time P is input and the clock signal CK is input, a signal S1 shown in FIG. 35B is output to the level shifter 13. The high level of the clock signal CK and the start pulse SP is set to the voltage VCC, and the low level is set to the voltage VSS, that is, 0V. The level shifter 13 is a circuit that shifts the level of an input signal and outputs the shifted signal. FIG. 34 shows a level conversion circuit disclosed in Japanese Patent Application Laid-Open No. 62-69719 as an example of the configuration of the level shifter 13. In the following description, the level shifter 13 will be described.

The level shifter 13 includes an inverter circuit 16
And P-channel MOS (Metal Oxide Semiconductor) transistors Q1, Q2 and N-channel MOS transistors Q3, Q4. Also, the inverter circuit 16 has P
Channel MOS transistor Q5 and N-channel MOS
And a transistor Q6. In the inverter circuit 16, the voltage V is applied to the source of the transistor Q6.
SS is applied, and a voltage V
CC is given.

The signal input to the level shifter 13 is a P-channel MOS transistor Q5 of the inverter circuit 16.
And the gate of N-channel MOS transistor Q6,
It is supplied to the gate of N-channel MOS transistor Q4.

The output of inverter circuit 16, ie, the voltage at the drains of transistors Q5 and Q6, is an N-channel MOS transistor Q having a threshold set at about 1V.
3 gates. The drain of N-channel MOS transistor Q3 is connected to P-channel MOS transistor Q
1 and the gate of the P-channel MOS transistor Q2.

P channel MOS transistors Q1, Q2
Is supplied with a voltage VDD set to a level higher than the voltage VCC applied to the input stage. The voltage VSS is supplied to the sources of the N-channel MOS transistors Q3 and Q4. The drain of N-channel MOS transistor Q4 and P-channel MOS transistor Q
The voltage at the connection point with the drain 2 is supplied to the output buffer 14 as the output of the level shifter 13. The output of the level shifter 13 is shown as a signal S2 in FIG.

The level shifter 13 includes a shift register 1
2, a signal that changes between the voltages VCC and VSS, that is, a signal having an amplitude of 5 V is input. When the level of the signal changes from 5V to 0V, N-channel MOS transistor Q6 shuts off and P-channel MOS transistor Q6
5 conducts. As a result, the output of inverter circuit 16 becomes voltage VCC, that is, 5 V, and N-channel MOS transistor Q3 set to a threshold value of 1 V is turned on, and the gate potentials of P-channel MOS transistors Q1 and Q2 are lowered and turned on. On the other hand, input is 5V
Is changed from to 0V, the N-channel MOS transistor Q4 whose threshold value is set to 1V is cut off and has a high resistance. Therefore, the voltage level of the output of the level shifter 13 becomes the voltage VDD.

Similarly, when the level of the input signal is 0 V to 5 V
, The P-channel MOS transistor Q5 is turned off, and the N-channel MOS transistor Q6 is turned on. The output of the inverter circuit 16 is the voltage VS
S, that is, 0 V, so that the N-channel MOS transistor Q3 is cut off to have a high resistance. By shutting off N channel MOS transistor Q3,
P channel MOS transistors Q1 and Q2 are shut off,
The resistance becomes high. When the level of the signal input to level shifter 13 is 5 V, N-channel MOS transistor Q4 is turned on. Therefore, the voltage level of the output of the level shifter 13 becomes the voltage VSS.

The output buffer 14 outputs the output of the level shifter 13 to each electrode at a predetermined timing. The output of the output buffer 14 is shown as a signal S3 in FIG.

In the gate driver 11 shown in FIG. 33, the voltage VSS on the negative power supply side is used as the reference voltage. Therefore, the level shifter 13 shown in FIG. 34 can be used. However, when the voltage on the positive power supply side is used as the reference voltage. , The level shifter 13 cannot be used.

FIG. 36 shows a configuration of a gate driver 11a to which a voltage VDD on the positive power supply side is commonly supplied. FIG. 37 shows a level shifter 17 in the gate driver 11a. FIG. 38 shows a relationship between an input and an output in the gate driver 11a. Is shown.

In the gate driver 11a, the level shifter 13 of the gate driver 11 is replaced by a level shifter 17. In addition, since the input voltage of each of the other components is different from that of the gate driver 11, the components are denoted by reference characters a and are distinguished, and the description of the configuration is omitted.

Since the gate driver 11a outputs a negative voltage based on a positive voltage, the output buffer 14a is supplied with the voltage VDD and the voltage VSS, and the level shifter 17 is supplied with the voltage VDD and the voltage VSS. Is supplied to the shift register 12a, and the voltage VDD and the voltage VCC are supplied to the shift register 12a. For example, voltage VDD is set to 5V, voltage VSS is set to -25V, and voltage VCC is set to 0V.

The level shifter 17 includes an inverter circuit 16
And P-channel MOS transistors Q11 and Q12,
It is configured to include N-channel MOS transistors Q13 and Q14. The level shifter 17 has a configuration in which the MOS transistors Q1 to Q4 in the level shifter 13 are replaced with MOS transistors Q11 to Q14 having different conductivity types, respectively, and a voltage output when the level of the voltage input to each MOS transistor is different. Are different. In the inverter circuit 16, the source of the transistor Q6 is supplied with the voltage VCC, and the source of the transistor Q5 is supplied with the voltage VDD. Voltage VDD is supplied to the sources of P-channel MOS transistors Q11 and Q12, and voltage VSS is supplied to the sources of N-channel MOS transistors Q13 and Q14.

FIG. 38 given to shift register 12a
The high level of the start pulse SP shown in FIG.
Is a signal whose low level is 0V. Shift register 1
2a has a voltage VDD of 5V and a voltage V of 0V.
When the start pulse SP is input, the signal S6 shown in FIG. 38B is output based on the signal level of the start pulse SP. The level shifter 17 outputs a signal S7 shown in FIG. 38C based on the output from the shift register 12a. The output buffer 14a is controlled based on the signal level of the signal S7 as shown in FIG.
Is output to each electrode at a predetermined timing.

[0020]

Here, if the power supply of the display device for supplying a voltage to the gate driver 11 uses a voltage of a predetermined level on the negative power supply side as a reference voltage, the level shifter shown in FIG. 13 can be used as it is, but when the display device has a configuration in which a voltage of a predetermined level on the positive power supply side is used as a reference voltage, the level shifter 17 whose polarity is inverted as shown in FIG. 37 is used. Required.

Conventionally configured gate drivers 11 and 11a
Includes a level shifter 1 operating at one of the voltages.
Since either one of 3, 17 is provided, the gate drivers 11, 11a must be selectively provided depending on whether the power supply of the display device is based on a positive voltage or a negative voltage. No. Since the gate drivers 11 and 11a are selectively manufactured according to the configuration of the power supply of the display device, it is not possible to reduce the manufacturing cost due to mass production. Further, if the level shifters 13 and 17 are provided in common and the gate driver is switched according to the configuration of the power supply, there is a case where the power supply of the display device is based on a negative voltage even if the power supply is based on a positive voltage. However, the configuration of the gate driver becomes large.

It is an object of the present invention to provide a level conversion circuit capable of converting a voltage level serving as a reference of an input signal to, for example, either positive or negative according to a power supply voltage to be supplied.

[0023]

According to the present invention, an input signal applied to a signal input terminal and changing within a predetermined amplitude with a reference voltage level between a first voltage level and a second voltage level is converted to a different voltage. A level conversion circuit for converting a level to a reference has one output electrode, the other output electrode and a control electrode, one output electrode being connected to a power supply voltage of a first voltage level, and the other output electrode being connected to a second voltage. The control electrode is connected to a signal input terminal, and a voltage level within a predetermined amplitude of the input signal is set as a threshold, and the input signal is connected to the first voltage level side or the second voltage level side. An input-side switching element that changes so as to be interrupted or conductive between one output electrode and the other output electrode, and the other output electrode of the input-side switching element and a second voltage An input-side load means connected between the power supply voltage and the power supply voltage, and a power supply terminal having a third voltage level supplied to one power supply terminal, the other power supply terminal, a signal output terminal, and a control terminal; A power supply voltage having a fourth voltage level different from the third voltage level is supplied to the other power supply terminal in a direction in which the second voltage level is different from the first voltage level, and the control terminal is connected to the other output electrode of the input-side switching element. And a threshold of a voltage level between the first voltage level and the second voltage level, while the voltage level of the output electrode is closer to the first voltage level than the threshold by the second voltage level.
Depending on the voltage level, the third
An output-side switching means for deriving a voltage closer to the voltage level or a voltage closer to the fourth voltage level, respectively. According to the present invention, the level conversion circuit includes an input-side switching element, an input-side load unit, and an output-side switching unit. One output electrode of the input-side switching element is connected to the power supply voltage of the first voltage level, and the other output electrode is connected to the power supply voltage of the second voltage level via the input-side load means. Also, the other output electrode of the input side switching element is
Connected to the control terminal of the output side switching means. Whether to conduct or cut off between the one output electrode and the other output electrode of the input side switching element is determined based on the signal level of the input signal supplied to the control electrode via the signal input terminal. When the signal level of the input signal is on the first voltage level side from the threshold value, the voltage level on the other output electrode is the first voltage level, and when the signal level is on the second voltage level side from the threshold value, the voltage on the other output electrode is The level becomes the second voltage level. A power supply voltage of a third voltage level is supplied to one power supply terminal of the output-side switching means, and a fourth voltage different from the third voltage level in a direction in which the second voltage level is different from the first voltage level is supplied to the other power supply terminal. Level power supply voltage is supplied. The output-side switching means is configured to determine whether the voltage level of the other electrode of the input-side switching element is the first voltage level or the second voltage level with respect to the reference voltage level. Is output from the signal output terminal. Therefore, the polarity of the voltage output from the output-side switching means with respect to the reference voltage level is determined depending on whether the third voltage level is on the first voltage level side or the second voltage level side with respect to the reference voltage level. Thus, the reference voltage level of the input signal can be converted to the positive voltage side or the negative voltage side.

Further, the input-side load means of the present invention comprises: first load means which operates when the third voltage level is on the first voltage level side with respect to a reference voltage level of the input signal; And a second load means that operates when the level is on the level side. According to the present invention, the first load means and the second load means are connected to the other output electrode of the input side switching element. The first load means operates when the third voltage level is set on the first voltage level side of the reference voltage level of the input signal. The second load means operates when the third voltage level is set on the second voltage level side of the reference voltage level of the input signal. Therefore,
Depending on whether the third voltage level is the first voltage level side or the second voltage level side with respect to the reference voltage level, one of the load means operates, and the characteristics of the first load means and the second By making the characteristics of the load means different from each other, the level conversion circuit can be operated according to the voltage level supplied as the third voltage level.

In the present invention, the first load means and the second load means are connected in parallel, and when the third voltage level is closer to the first voltage level than the reference voltage level of the input signal, the second load means is connected to the second voltage means. The resistance value of the load means is larger than the resistance value of the first load means, and when it is on the second voltage level side, the resistance value of the first load means is larger than the resistance value of the second load means. I do. According to the present invention, the first output electrode is connected to the other output electrode of the input-side switching element.
The load means and the second load means are connected in parallel. When the third voltage level is closer to the first voltage level than the reference voltage level of the input signal, the resistance value of the second load means is smaller than the resistance value of the first load means. growing. When the third voltage level is closer to the second voltage level than the reference voltage level of the input signal, the resistance value of the first load means becomes larger than the resistance value of the second load means. Therefore, the resistance value of the first and second load means is determined depending on whether the third voltage level is the first voltage level side or the second voltage level side with respect to the reference voltage level, and one of the load means Operate as a load. By making the characteristics of the first load means and the characteristics of the second load means different from each other, the level conversion circuit can be operated according to the voltage level supplied as the third voltage level.

Further, the first load means of the present invention includes one output electrode, the other output electrode and a control electrode, one output electrode is connected to a power supply voltage of the second voltage level, and the control electrode is connected to the third voltage. And the other output electrode is connected to the other output electrode side of the input-side switching element and is always in a conductive state, and the resistance of the conductive state is larger than the resistance of the input-side switching element in the conductive state. And a load element having a resistance value smaller than the resistance value in the cutoff state. According to the invention, one output electrode of the load element in the first load means is connected to the power supply voltage of the second voltage level, and the other output electrode is connected to the other output electrode of the input-side switching element. The control electrode of the first load means is connected to the power supply voltage of the third voltage level, and the first load means is always in a conductive state. The resistance value of the first load means when the load element is in a conductive state is larger than the resistance value when the input-side switching element is in a conductive state, and smaller than the resistance value when the input-side switching element is in a cutoff state. Therefore, when the input-side switching element is in a conductive state, the power supply voltage at the first voltage level applied to one output electrode of the input-side switching element becomes a voltage applied to the control terminal of the output-side switching means. When in the cutoff state, the power supply voltage at the second voltage level applied to the other output electrode of the load element in the first load means becomes the voltage applied to the control terminal of the output-side switching means.

Further, the second load means of the present invention includes one output electrode, the other output electrode and a control electrode, one output electrode is connected to the power supply voltage of the second voltage level, and the control electrode is connected to the first voltage. And the other output electrode is connected to the other output electrode side of the input-side switching element and is always in a conductive state, and the resistance of the conductive state is larger than the resistance of the input-side switching element in the conductive state. And a load element having a resistance value smaller than the resistance value in the cutoff state. According to the invention, one output electrode of the load element in the second load means is connected to the power supply voltage of the second voltage level, and the other output electrode is connected to the other output electrode of the input-side switching element. The control electrode of the second load means is connected to the power supply voltage at the first voltage level, and the second load means is always in a conductive state. The resistance value of the second load means when the load element is in a conductive state is larger than the resistance value when the input-side switching element is in a conductive state, and smaller than the resistance value when the input-side switching element is in a cutoff state. Therefore, when the input-side switching element is in a conductive state, the power supply voltage at the first voltage level applied to one output electrode of the input-side switching element becomes a voltage applied to the control terminal of the output-side switching means. When in the cutoff state, the power supply voltage at the second voltage level applied to the other output electrode of the load element in the second load means becomes the voltage applied to the control terminal of the output-side switching means.

The output-side switching means of the present invention includes one output electrode, the other output electrode, and a control electrode, one output electrode being connected to the other power supply terminal, and the other output electrode being connected to the signal output terminal. A control element connected to the control terminal, the switching element having a threshold of a voltage level between the first voltage level and the second voltage level, the other output electrode of the switching element, and the one power supply terminal And an output-side load means connected between the first and second power supply means. According to the invention, the output-side switching means includes a switching element and an output-side load means. The switching element has a threshold of a voltage level between the first voltage level and the second voltage level. One output electrode of the switching element is connected to the other power supply terminal, the other output electrode is connected to the signal output terminal, and the control electrode is connected to the control terminal. The other output electrode of the switching element is further connected to one power supply terminal via output side load means. The third and fourth power supply voltages can be selectively output according to whether the voltage level of the input signal is on the first voltage level side or the second voltage level side with respect to the reference voltage. .

The output-side switching means of the present invention includes one output electrode, the other output electrode, and a control electrode, and has the same conductivity type as the input-side switching element. One output electrode is connected to the one power supply terminal. Connected, the other output electrode is connected to the signal output terminal, the control electrode is connected to the control terminal one switching element, and one output electrode, the other output electrode and the input side switching element having a control electrode and Have complementary conductivity types,
The one output electrode is connected to the other power terminal, the other output electrode is connected to the signal output terminal, and the control electrode includes the other switching element connected to the control terminal. According to the invention, the output-side switching means includes one switching element of the same conductivity type as the input-side switching element, and the other switching element of the conductivity type complementary to the input-side switching element. On the other hand, one output electrode of the switching element is connected to one power supply terminal, and the other output electrode is connected to a signal output terminal. One output electrode of the other switching element is connected to the other power supply terminal, and the other output electrode is connected to the signal output terminal. The control electrodes of one and the other switching elements are both connected to a control terminal. Therefore, according to the voltage level of the other output electrode of the input-side switching element applied to each control electrode via the control terminal, only one of the one and the other switching element conducts, and a voltage is output to the signal output terminal. As a result, there is no continuity between one and the other power supply terminals to which power supply voltages of different voltage levels are supplied, and the current flowing through the output-side switching means can be reduced.

The output-side switching means of the present invention includes one output electrode, the other output electrode and a control electrode, and has the same conductivity type as the input-side switching element, while the output electrode is connected to the first voltage level. A first switching element, which is connected to a power supply voltage of the input signal, is supplied with a reference voltage level of the input signal to a control electrode, and is always in a conductive state; and one output electrode, the other output electrode, and a control electrode. The switching element has a complementary conductivity type, one output electrode is connected to the power supply voltage of the second voltage level, the other output electrode is connected to the other output electrode of the first switching element, and the control electrode is connected to the control electrode. A second switching element connected to the terminal and having a threshold between the first voltage level and the second voltage level; and the same conductivity type as the first switching element. A bridge circuit formed by third and fourth switching elements having the same conductivity type and fifth and sixth switching elements having the same conductivity type as the second switching element, wherein one output electrode of the fifth and sixth switching elements is provided. Is connected to the other power supply terminal, one output electrode of the third and fourth switching elements is connected to the one power supply terminal, and the other output electrode of the third and fifth switching elements and the control electrode of the fourth switching element are common. And the other output electrode of the fourth and sixth switching elements and the control electrode of the third switching element are connected in common and connected to the signal output terminal. The control electrode of the sixth switching element is connected to the other output electrode of the one switching element. And a bridge circuit connected to the According to the present invention, the output-side switching means includes a first switching element having the same conductivity type as the input-side switching element, a second switching element having a conductivity type complementary to the input-side switching element,
And a bridge circuit. The other output electrodes of the first and second switching elements are commonly connected and connected to the control electrode of the sixth switching element. One output electrode of the first switching element is connected to the power supply voltage at the first voltage level. The control electrode is supplied with the reference voltage level of the input signal, and is always in a conductive state. The second switching element has a threshold between the first voltage level and the second voltage level. One output electrode of the second switching element is connected to the power supply voltage at the second voltage level, and the control electrode is connected to the control terminal. The bridge circuit is the first
The third and fourth switching elements have the same conductivity type as the switching element, and the fifth and sixth switching elements have the same conductivity type as the second switching element. One output electrode of the fifth and sixth switching elements is connected to the other power supply terminal, and one output electrode of the third and fourth switching elements is connected to one power supply terminal. The other output electrode of the third and fifth switching elements and the control electrode of the fourth switching element are commonly connected. The other output electrodes of the fourth and sixth switching elements and the control electrode of the third switching element are commonly connected and are connected to a signal output terminal. Therefore, the voltage level of the other output electrode of the input side switching element is inverted by the first and second switching elements, and the voltage is output from the bridge circuit by the voltage level of the other output electrode of the input side switching element and the inverted voltage level. Since the voltage levels are determined, there is no continuity between one and the other power supply terminals to which power supply voltages of different voltage levels are supplied, and the current flowing through the output-side switching means can be reduced.

[0031]

FIG. 1 is a circuit diagram of a level conversion circuit 31 according to a first embodiment of the present invention. The level conversion circuit 31 includes a switching element 32 and a load circuit 33.
And an output circuit 34. In the level conversion circuit 31, a P-channel M
An OS transistor P1 is provided, and an N-channel MOS transistor N1 is provided as a load circuit 33. The output circuit 34 includes a P-channel MOS transistor P2 as a switching element and an N-channel M
OS transistor N2.

In the level conversion circuit 31, the input terminal T
1 is supplied to a gate serving as a control electrode of a P-channel MOS transistor P1. The drain of the other output electrode of the P-channel MOS transistor P1 is connected to the drain of the transistor N1. P
A voltage V1 at a first voltage level is supplied to a source, which is one output electrode of the channel MOS transistor P1.

The threshold voltage of P-channel MOS transistor P1 and the amplitude of the input signal are determined so that the threshold voltage is included in the amplitude of the input signal. Conducts, and when high, the transistor P1 is shut off.

N-channel M operating as load circuit 33
The voltage V5 is applied to the gate of the OS transistor N1 and is always in a conductive state. N channel MOS
The voltage of the second voltage level V2 is supplied to the source of the transistor N1. The voltage of each drain of the transistors P1 and N1 is applied as a signal OUT1 to the gate of an N-channel MOS transistor N2 via a signal input terminal 36 described later. The voltage V1 and the voltage V2 are equal to the voltage V
1 is set to a higher voltage, and the threshold voltage of the N-channel MOS transistor N2 is included between the two voltages.

Therefore, the relationship between the voltage V1, the voltage V2, and the threshold voltage of the N-channel MOS transistor N2 is expressed as follows: V2 <threshold voltage of the N-channel MOS transistor N2 <V1 (1) .

In the output circuit 34, the voltage V3 at the third voltage level is applied to the source of the transistor P2, and the voltage V4 at the fourth voltage level is applied to the source of the transistor N2. The drain of the transistor P2 and the drain of the transistor N2 are connected, and the voltage at the connection point is output as the output signal OUT.

The voltage V6 is applied to the gate of the transistor P2, and is always in a conductive state. The resistance value of the transistor P2 is determined to be sufficiently larger than the ON resistance of the transistor N2, and the transistor N2 operates as a load transistor. A signal OUT1 which is a voltage at a connection point between the transistors P1 and N1 is supplied to a gate of the transistor N2, and conduction / interruption of the transistor N2 is controlled according to a signal level of the signal OUT1. When the signal OUT1 is at a high level, that is, the voltage V1
Then, the transistor N2 becomes conductive, and the output signal OUT becomes the voltage V4. Further, when the signal OUT1 goes to a low level, that is, the voltage V2, the transistor N2 is turned off, and the output signal OUT goes to the voltage V3. The voltage V3 and the voltage V4 are determined so that the voltage V3 is higher. The amplitude of the signal output from the level conversion circuit 31 is determined by the voltages V3 and V4.

The relationship between the voltage V3 and the voltage V4 is expressed by the following equation: V4 <V3 (2)

The voltages at the drains of the transistors N2 and P2 are commonly connected and input to a shift register 42 described later. In this embodiment, the signal OUT output from the level conversion circuit 31 via the output terminal T2 is
For example, since the signal amplitude is determined to be 5 V, the shift register 42 can be configured to operate at a low voltage.

Since the gate of the N-channel MOS transistor N1 is supplied with the voltage V5 which is equal to or higher than the threshold value of the transistor N1, the transistor N1 is always in a conductive state. Therefore, the voltage V
The relationship between 5 and the threshold voltage of the N-channel MOS transistor N1 is expressed by the following equation: V5 ≧ the threshold voltage of the N-channel MOS transistor N1 (3)

The resistance value of the transistor N1 is designed to be sufficiently larger than the on-resistance of the P-channel MOS transistor P1, and is configured as a load transistor.

On the other hand, P-channel MOS transistor P2
Is supplied with the voltage V6 determined to be equal to or lower than the threshold value of the transistor P2, the transistor P2 is always in a conductive state. Therefore,
The relationship between the voltage V6 and the threshold voltage of the P-channel MOS transistor P2 is expressed by the following equation: V6 ≦ the threshold voltage of the P-channel MOS transistor P2 (4).

The resistance value of the transistor P2 is designed to be sufficiently larger than the on-resistance of the transistor N2, and is configured as a load transistor like the transistor N1.

The above-mentioned voltages V1 to V6 may have different voltage values. In addition, if the expressions (1) to (4) defined as the conditions for each voltage described above are satisfied,
A plurality of voltages may have the same voltage value.

If a signal having an amplitude of 5 V is input to the input terminal and the signal changes from 5 V to 0 V, the P channel M
The OS transistor P1 is turned on, and the next-stage N-channel MO
The voltage V1 is applied to the gate of the S transistor N2 to make the transistor N2 conductive. When the transistor N2 is turned on, the voltage V
4 is output. When a 5V signal is input,
Since the P-channel MOS transistor P1 is shut off,
The voltage V2 is applied to the transistor N2 at the next stage via the transistor N1 which is always conductive when the voltage V5 is applied to the gate. When the voltage V2 is given,
The transistor N2 is shut off, and the voltage V4 is not output. However, the voltage V3 is output from the level conversion circuit 31 by the transistor P2 which is always on when the voltage V6 is supplied. Therefore, the signal output from level conversion circuit 31 is equal to voltage V5 and voltage V5.
6 and amplitude.

FIG. 2 shows a configuration of a gate driver 41 provided with the level conversion circuit 31, and FIG.
FIG. 4 shows the relationship between the input and output of the gate driver 41.

The display device 51 includes a gate driver 41,
It includes a source driver 52, a liquid crystal display panel 53, a control circuit 54, and a power supply circuit 55. The liquid crystal display panel 53 is a TFT (thin film transistor) type liquid crystal display panel, and has source lines s1, s2, s3,...
), And the gate lines g1, g2, g3,.
n (the reference numeral g is used when collectively referred to). The TFTs k11, k12,..., Knm (the reference character k is used when collectively referred to) are provided near the intersection of the source line s and the gate line g.
, znm to the pixel electrodes z11, z12,.
(The reference numeral z is used when collectively referred to). A counter electrode is provided to face the pixel electrode z with the liquid crystal layer interposed therebetween.

The operation of the source driver 52 and the gate driver 41 for applying signals to the source line s and the gate line g is controlled based on the signal supplied from the control circuit 54. For example, the gate driver 41 receives at least the clock signal CK and the start pulse SP. A power supply circuit 55 is provided in each of the drivers 41 and 52.
Supplies a plurality of types of voltages.

As shown in FIG. 2, the gate driver 41
Are input level conversion circuit 31 and shift register 42
, A level shifter 43, and an output buffer 44. In the gate driver 41, description of the same components as those of the gate driver 11 described above is omitted, and different points including the input level conversion circuit 31 will be described. The clock signal CK and the start pulse SP are input to the input level conversion circuit 31. The clock signal CK is directly supplied to the shift register 42.

The gate driver 41 is supplied with a plurality of voltages from a power supply circuit 55. Gate driver 41
Is a gate driver provided in a display device that uses a positive voltage as a reference level, so that the output buffer 44 is supplied with the voltages VDD and VSS, and the level shifter 43 is supplied with the voltages VDD and VSS. The shift register 42 is supplied with voltages VDD and VCC. 1, the voltage VDD is supplied as the voltage V3, and the voltage VCC is supplied as the voltage V4. A ground voltage is supplied as the voltages V2 and V6, and a voltage V is used as the voltages V1 and V5.
LS is supplied. When gate driver 41 outputs a positive voltage, for example, voltage VDD is 30 V and voltage V
CC is 25V, voltage VLS is 5V and voltage VLS
SS is 0V, that is, the ground voltage.

As for the start pulse SP whose signal level is shown in FIG. 4A, the high level is the voltage VLS and the low level is the voltage VSS. The level of the start pulse SP is converted by the level conversion circuit 31 and FIG.
Signal S11 shown in FIG. The signal S11 has a high level of the voltage VDD and a low level of the voltage VCC. Signal S1
1 is input to the level shifter 43 and the level is shifted to become a signal S12 shown in FIG. Signal S12
Means that the high level is the voltage VDD and the low level is the voltage VSS
It is. Signal S12 output from level shifter 43
Is a signal S13 shown in FIG. 4D from the output buffer 44 at a predetermined timing from the gate lines g1, g2,
, Gn. The signal S13 has a high level of the voltage VDD and a low level of the voltage VSS.

When the gate driver 41 outputs a negative voltage, the voltages VDD and VLS are 5V and the voltage VC
C is 0V and voltage VSS is -25V. When the gate driver 41 outputs a negative voltage, the start pulse SP shown in FIG. 4E has a high level of the voltage VLS and a low level of the voltage VCC. The start pulse SP is
The signal S1 shown in FIG.
6 is converted. The signal S16 has a high level of the voltage VL.
At S, the low level is the voltage VCC. The signal S16 is input to the level shifter 43 and the level is shifted.
A signal S17 shown in FIG. The signal S17 has a high level of the voltage VDD and a low level of the voltage VSS. The signal S17 output from the level shifter 43 is
(H) is output from the output buffer 44 to the gate lines g1, g2,..., Gn at a predetermined timing as a signal S18. The signal S18 has a high level of the voltage VDD and a low level of the voltage VSS.

FIG. 5 is a timing chart of each signal in the gate driver 41. In this timing chart, the signal S18 given to the gate line g is given the same reference numeral as the gate line g. The clock signal CK is a signal that is input at every predetermined cycle. The signals g1, g2, and gn are output at the falling timing of the clock signal CK, respectively. The start pulse SP rises every time the clock signal CK falls at least n times.

FIG. 6 is a diagram for explaining the operation of the level conversion circuit 31 in the case of the positive power supply specification. (1) shows the configuration of the input stage of the level conversion circuit 31, and (2) shows an equivalent circuit of the input stage of the level conversion circuit 31 in the case of a positive power supply specification.

Assuming that the level conversion circuit 31 has a positive power supply specification, that is, the voltages VLS and VCC are determined to be equal,
The transistors N1 and P1 constituting the input stage operate in the resistance operation region. When the input signal IN is at a low level, the gate of the transistor P1 is supplied with the ground voltage GND.
Becomes Further, the transistor N1 has the voltages VLS and VCC.
Are determined to be equal, the signal level of the signal OUT1 does not become higher than the voltage VCC applied to the gate, so that it is equivalent to the resistance RN.

Although the level of the signal OUT1 when the input signal IN is at the low level is ideally the voltage VLS, it is actually a level obtained by dividing the voltage VLS based on the resistances RP and RN.

FIG. 7 shows the relationship between the voltage value of the voltage V5 in the level conversion circuit 31 and the signal level of the signal OUT1. The horizontal axis indicates the voltage value (V) of the voltage V5, and the vertical axis indicates the signal level (V) of the signal OUT1. Transistor N1
Characteristic line 4 indicating the voltage value of voltage V5 applied to the gate of
6 rises from the voltage VCC to the voltage VLS, the characteristic line 47 indicating the signal level of the signal OUT1 also rises. When the voltage V5 is set to the voltage VCC, the power supply specification is used. When the voltage V5 is set to the voltage VLS, the power supply specification is used. The relationship between the voltage value of the voltage VLS and the signal level of the signal OUT1 is determined based on the equivalent resistance values of the resistors RP and RN.

FIG. 8 shows the configuration of the gate driver 41a, and FIG. 9 shows the relationship between inputs and outputs in the gate driver 41a.

The gate driver 41a is a gate driver that uses a predetermined negative voltage as a reference voltage, whereas the gate driver 41a uses a predetermined positive voltage as a reference voltage. Therefore, the gate driver 41 is different from the gate driver 41 only in the type of voltage input to each component, and is distinguished by the reference numeral a, and the description of the configuration and operation is omitted.

In the gate driver 41a, the voltages VDD and VSS are supplied to the output buffer 44a.
Voltages VDD and VSS are supplied to the level shifter 43a, and voltages VSS and VCC are supplied to the shift register 42a.
Is supplied. Referring to FIG. 1, the input level conversion circuit 31a is supplied with the voltage VCC as the voltage V3.
The voltage VSS is supplied as the voltages V4 and V6. Also,
The voltage VLS is supplied as the voltages V1 and V5,
2, a ground voltage is supplied. When the gate driver 41a outputs a positive voltage, the voltage VDD is 30V, the voltages VCC and VLS are 5V, and the voltage VSS is 0V, that is, the ground voltage.

The start pulse SP whose signal level is shown in FIG. 9A has a high level of the voltage VLS and a low level of the voltage VSS. The start pulse SP is converted by the level conversion circuit 31a, and the signal S2 shown in FIG.
Becomes 1. The signal S21 has a high level of the voltage VLS and a low level of the voltage VSS. The signal S21 is input to the level shifter 43a and the level is shifted.
The signal S22 shown in FIG. The signal S22 has a high level of the voltage VDD and a low level of the voltage VSS. The signal S22 output from the level shifter 43a is
The signal S23 shown in (d) is output from the output buffer 44 to the gate lines g1, g2,..., Gn at a predetermined timing. The signal S23 has a high level of the voltage VDD and a low level of the voltage VSS.

When the gate driver 41a outputs a negative voltage, the voltages VDD and VLS are 5V and the voltage V
CC is -20V and voltage VSS is -25V.
The amplitude of the stage before the conversion is 5 V (the high level is the voltage VDD,
VLS, low level is 0 V), and the converted amplitude is 30 V
(Low level is voltage VSS and high level is voltage VDD)
The operation of the level conversion circuit 31a in the case described above will be described below. The voltage VLS or the voltage VDD is supplied to the gate of the N-channel MOS transistor N1 of the level conversion circuit 31, and the transistor N1 is in a conductive state.

When a signal having an amplitude of 5 V is input to the input terminal and the signal changes from 5 V to 0 V, the P-channel MOS transistor P1 is turned on, and the transistor N2 in the next stage is turned on. Thereby, from the level conversion circuit 31a,
A voltage of approximately −25 V, which is higher than the voltage VSS by the threshold voltage of the transistor N2, is output. When a voltage of 5 V is applied to the input terminal, P-channel MOS transistor P1 is shut off, voltage V2 from transistor N1 is applied to transistor N2, and transistor N2 is shut off. The transistor P2 is always on because the voltage VSS is applied to the gate. Therefore, the output from the level conversion circuit 31a becomes the voltage VCC. The level conversion circuit 31a outputs the voltage VSS (−25) according to the signal level of the input signal IN.
V) and the voltage VCC (−20 V) are selectively output.

The start pulse SP whose signal level is shown in FIG. 9E has a high level of the voltage VLS and a low level of 0.
V signal. The level of the start pulse SP is converted by the level conversion circuit 31a to become a signal S26 shown in FIG. The signal S26 has a high level of the voltage V
The low level at CC is the voltage VSS. The signal S26 is
The level is input to the level shifter 43a, and the level is shifted.
This is the signal S27 shown in FIG. The signal S27 has a high level at the voltage VDD and a low level at the voltage VSS. The signal S27 output from the level shifter 43a is
As a signal S28 shown in FIG. 9 (h), the gate lines g1, g2,.
gn. The signal S28 has a high level of the voltage V
In DD, the low level is the voltage VSS.

FIG. 10 shows a level conversion circuit 81 as another configuration example of the first embodiment. In the level conversion circuit 81, the same components as those in the level conversion circuit 31 are denoted by the same reference numerals, and description thereof will be omitted. Level conversion circuit 81
Is configured to include a P-channel MOS transistor P1, an N-channel MOS transistor N1, and an output circuit 84. A feature of the level conversion circuit 81 is that an output circuit 84 is provided in place of the output circuit 34 in the level conversion circuit 31.

The output circuit 84 includes a P-channel MOS transistor P3 and an N-channel MOS transistor N3. The source of the transistor P3 is supplied with the voltage V3, and the drain is the transistor N3.
3 is connected to the drain. The voltage V4 is applied to the source of the transistor N3. Transistor N
3 and P3 are supplied with a signal OUT1.
Either 3 or P3 conducts. Transistors N3 and P
3 is output as the output signal OUT.

When the signal OUT1 becomes high level, that is, the voltage V1, the transistor N3 is turned on and the transistor P3 is turned off, so that the signal level of the output signal OUT becomes the voltage V4. When the signal OUT1 is at a low level,
That is, when the voltage reaches the voltage V2, the transistor P3 is turned on and the transistor N3 is turned off.
The signal level of T becomes the voltage V3. The signal level of the output signal OUT is a voltage obtained by inverting the signal level of the input signal IN with respect to the reference ground voltage GND.

In the output circuit 84, the signal level of the output signal OUT is determined by turning on one of the transistors P3 and N3 in accordance with the signal level of the signal OUT1 and cutting off the other. At the same time, the conduction state does not occur, and the through current flowing between the voltages V6 and V5 can be reduced. By reducing the through current, the current consumption in the level conversion circuit 81 can be reduced.

FIG. 11 shows a level conversion circuit 91 which is still another configuration example of the first embodiment. In the level conversion circuit 91, the same components as those in the level conversion circuit 31 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 91 includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, and an output circuit 94. A feature of the level conversion circuit 91 is that an output circuit 94 is provided in place of the output circuit 34 in the level conversion circuit 31.

Output circuit 94 includes P-channel MOS transistors P4, 5, 6 and N-channel MOS transistors N4, 5, 6. The voltage V1 is applied to the source of the transistor P4, and the drain is connected to the drain of the transistor N4. The gate of the transistor P4 is supplied with the ground voltage GND, and is always in a conductive state. The voltage V2 is applied to the source of the transistor N4.
The signal OUT1 is given to the gate of the fourth. The voltage at the connection point between the transistors N4 and P4 is supplied to the gate of the transistor N6 as a signal OUT2. Signal OUT1
And the signal OUT2 have inverted signal levels.

The source of each of the transistors P5 and P6 is supplied with the voltage V3, and the drain is connected to the transistor N5 and P6.
Each is connected to the drain of N6. Transistor P
The gates of P5 and P6 are connected to the drains of transistors N6 and N5, respectively. Therefore, transistor N
The drain of transistor 5 is connected to the drain of transistor P5 and the gate of transistor P6, and the drain of transistor N6 is connected to the drain of transistor P6 and the gate of transistor P5. The voltage at the connection point between transistors P6 and N6 is output as output signal OUT. The voltage V is applied to the sources of the transistors N5 and N6.
4 are given.

When the signal OUT1 is at a high level, the transistor N5 is turned on and the transistor N6 is turned off. When the transistor N5 is turned on, the voltage V4 is applied to the gate of the transistor P6.
Becomes conductive. At this time, since the transistor N6 is shut off, the voltage V3 is output as the output signal OUT. When the signal OUT1 is at a low level, the transistor N6 is turned on and the transistor N5 is turned off.
When the transistor N6 is turned on, the voltage V4 is applied to the gate of the transistor P5, and the transistor P5 is turned on. At this time, since the transistor N5 is shut off, the voltage V3 is applied to the gate of the transistor P6,
Transistor P6 is turned off. Therefore, the voltage V4
Is output as the output signal OUT.

As described above, according to the present embodiment, the level conversion circuits 31, 31a, 81, and 91 apply the voltages V3, V4
Is output according to the level of the input signal, so that a level conversion circuit 31 and the like are provided.
For example, even if the display device 51 including the gate drivers 41 and 41a operates using any of the positive and negative voltage levels as the reference voltage, the gate driver 41, 41a
It can be used without changing the configuration of 41a.
Further, it is not necessary to separately create a gate driver for each display device having a different reference voltage, so that the manufacturing cost of the gate driver can be reduced.

Each transistor in this embodiment can be replaced with a transistor of a complementary conductivity type. Each MO in the level conversion circuit 31
The same effect as that of the level conversion circuit 31 can be obtained even when the polarities of the S transistors P1, P2, N1, and N2 are reversed. N channel MOS transistors N1, N
Assuming that 2 is replaced by P channel MOS transistors P1 and P2 in this order, the voltages V1 to V6 are determined so as to satisfy the following equations (5) to (8).

V1 <threshold voltage of P-channel MOS transistor P2 <V2 (5) V3 <V4 (6) V5 ≦ threshold voltage of P-channel MOS transistor P1 (7) V6 ≧ N-channel MOS transistor Threshold voltage of N2 (8) Although the configuration in which the transistor N1 is provided as the input-side load is shown, a configuration in which a plurality of transistors are provided in series may be employed.

FIG. 12 is an equivalent circuit of the level conversion circuit 31 in the case of the positive power supply specification and the negative power supply specification.
(1) shows an equivalent circuit 401 when the level conversion circuit 31 is used with a positive power supply specification. Transistor N1 is equivalently shown as resistor RN. (2) shows an equivalent circuit 402 when the level conversion circuit 31 is used with a negative power supply specification. In the case of the negative power supply specification, the transistor N1 operates in the saturation region, and equivalently, the constant current source C
Shown as S. The liquid crystal display panel 53 is equivalently shown as a capacitor C.

While the input signal IN is at the low (L) level, the capacitor C is charged with electric charge, and when the input signal is at the high (H) level, discharging of the charged electric charge is started. In the equivalent circuit 401, the electric charge is discharged via the resistor RN connected in series with the capacitor C. In the equivalent circuit 402, when the input signal IN becomes high level, electric charges are discharged via the constant current source CS connected in series to the capacitor C. In the case where electric charges are discharged via the constant current source CS, the time required for discharging is longer than in the case where electric charges are discharged via the resistor RN.

Further, depending on the range specification of the power supply voltage, the power supply voltage is raised from, for example, 30 V to 42 V, the electric charge charged in the capacitor C is increased, and the time required for discharging is further prolonged.

FIGS. 13 to 15 show the second embodiment of the present invention.
It is a figure for explaining the outline of the 5th form. A feature of the level conversion circuits shown in the second to fifth embodiments is that loads are provided in parallel as input-side load means.

FIG. 13 is a circuit diagram of the level conversion circuit 101. In the level conversion circuit 101, the same components as those in the level conversion circuit 31 described above are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 101 includes a P-channel MOS transistor P1, a positive power supply load 102,
It is configured to include a load 103 for a negative power supply and an output circuit 34.

The transistor P1 serving as an input-side switching element has a gate supplied with the input signal IN, a source provided with the voltage V1 at the first voltage level, and a drain provided with a positive power supply as input-side load means. A voltage V2 which is the second voltage level is applied via the load 102 and the negative power supply load 103. The positive power supply load 102 and the negative power supply load 103 are connected in parallel to the drain of the transistor P1. The drain voltage of the transistor P1 is equal to the signal O
The signal UT1 is given to the gate of the transistor N2 in the output circuit 34.

Load 102 for positive power supply and load 103 for negative power supply
Means that one of the voltages V1 and V3 operates as a load depending on which voltage is higher. Level conversion circuit 101
Is a positive power supply specification, the voltage V1 and the voltage V3 are determined to be equal, and the positive power supply load 102 operates as a load. When the level conversion circuit 101 has a negative power supply specification, the voltage V1 is set to be higher than the voltage V3, and the negative power supply load 103 operates as a load.

FIG. 14 is a circuit diagram of the level conversion circuit 111. In the level conversion circuit 111, the same components as those in the above-described level conversion circuits 81 and 101 are denoted by the same reference numerals, and description thereof is omitted. The level conversion circuit 111
P-channel MOS transistor P1 and positive power supply load 1
02, a negative power supply load 103, and an output circuit 84. The configuration of the input stage of the level conversion circuit 111 is the same as that of the level conversion circuit 101, and the signal OUT1
1 is applied to each gate of the transistors P3 and N3 of the output circuit 84.

FIG. 15 is a circuit diagram of the level conversion circuit 121. In the level conversion circuit 121, the same components as those in the above-described level conversion circuits 91 and 101 are denoted by the same reference numerals, and description thereof is omitted. The level conversion circuit 121
P-channel MOS transistor P1 and positive power supply load 1
02, a negative power supply load 103, and an output circuit 94. The configuration of the input stage of the level conversion circuit 121 is the same as that of the level conversion circuit 101, and the signal OUT1
1 is given to each gate of the transistors P3 and N3 of the output circuit 94. A signal obtained by inverting the signal level of the signal OUT11 is referred to as a signal OUT12. Signal OUT12 is provided to the gate of transistor N6.

FIG. 16 shows a level conversion circuit 131 according to a second embodiment of the present invention, and FIG. 17 shows a relationship between an input signal and an output signal in the level conversion circuit 131.

In the level conversion circuit 131, the same components as those in the level conversion circuit 31 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 131 includes a P-channel MOS transistor P1, N-channel MOS transistors N11 and N12, and an output circuit. The feature of the level conversion circuit 131 is that the positive power supply load 1
02 and the load 103 for the negative power supply
11 and N12 are provided. In the level conversion circuit 131, the voltage VSS is applied as the voltages V2, V4, and V6, the voltage VLS is applied as the voltage V1, and the voltage VCC is applied as the voltage V3.

The transistor N11 has a drain connected to the drain of the transistor P1, and a source connected to the voltage VSS.
, And the voltage VCC is applied to the gate. The transistor N12 is connected in parallel with the transistor N11, and has the gate supplied with the voltage VLS.
The resistance values of the transistors N11 and N12 are set sufficiently large with respect to the on-resistance of the transistor P1, and the transistors N11 and N12 operate as load transistors.

When the voltage is determined so that voltage VLS≫VCC, level conversion circuit 131 outputs signal O
This is defined as a so-called negative power supply specification in which the low level of the UT becomes a negative voltage. At this time, for example, the voltage VLS is 5 V
And the voltage VCC is −20 V, and the voltage VSS is −
25V. It is assumed that the input signal IN is a signal having an amplitude of 5 V whose high level is the voltage VLS and whose low level is the ground voltage GND.

When the level of the input signal IN switches from the high level to the low level, the transistor P1 conducts and the voltage VLS is supplied to the output circuit 34 as the signal OUT21. Since the signal level of the signal OUT21 is the voltage VLS, the output circuit 34 outputs the voltage VSS to the output signal OUT.
Is output as When the level of the input signal IN switches from a low level to a high level, the transistor P1 is turned off. Since the voltage VLS≫VCC, the on-resistance of the transistor N12 becomes lower than the on-resistance of the transistor N11, and the transistor N12 becomes conductive. The voltage VSS is applied to the signal OU via the conducting transistor N12.
It is provided to the output circuit 34 as T1.

In the case of the negative power supply specification, for example, as shown in FIG.
The voltage VLS-GND is set to 3-5V, and the voltage VCC-VSS is set to 3-5V. The high level of the input signal IN is the voltage VLS, and the low level is the voltage GND. The high level of the output signal OUT, which is the output of the level conversion circuit 131, is the voltage VCC,
The low level is the voltage VSS.

When the voltage is set to the voltage VLS = VCC, the level conversion circuit 131 is set to a so-called positive power supply specification in which the low level of the output signal OUT becomes the ground voltage GND. At this time, for example, voltages VLS, VC
C is 5V and voltage VSS is 0V.

When operating with the positive power supply specification, the transistor N11 mainly operates as a load transistor because the on-resistance of the transistor N11 is set sufficiently smaller than the on-resistance of the transistor N12.
Since the signal level of the signal OUT1 is the same as that of the case of the negative power supply specification, the description is omitted. In the case of the positive power supply specification, as shown in FIG. 17 (2), for example, the voltage VLS-GND
Between the voltage VLS and VSS and between the voltage VCC and VSS
５5V. Input signal IN and output signal OU
T is the same as that in the case of the negative power supply specification, and the description is omitted.

FIG. 18 shows the relationship between the voltage value of the voltage VLS in the level conversion circuit 131 and the signal level of the signal OUT21. It is assumed that the voltage value of voltage VLS changes from voltage value VCC to voltage value VLS as shown by characteristic line 135. When the voltage value of the voltage VLS is the voltage value VCC, the level conversion circuit 131 has a positive power supply specification, and the voltage value VL
If it is S, the negative power supply specification is used.

A characteristic line 136 shows a change in the signal level of the signal OUT21 when only the transistor N11 serving as the positive power supply load is provided in the level conversion circuit 131. The characteristic line 136 is the same as the characteristic line 47 described above. A transistor N1 which is a load for a negative power supply
A change in the signal level of the signal OUT21 when only 2 is provided is indicated by a characteristic line 137. When only the transistor N12 is provided, the signal level of the signal OUT1 decreases as the voltage value of the voltage VLS changes from the voltage value VCC to the voltage value VLS. The voltage VLS is
When the voltage value VA is between the voltage value VCC and the voltage value VSS, the characteristic lines 136 and 137 have the same signal level.
The voltage value VA at which the characteristic lines 136 and 137 intersect is determined by the resistance value of the transistors N11 and N12 when conducting.

A change in the signal level of the signal OUT21 when the transistors N11 and N12 are provided is indicated by a characteristic line 138. In the level conversion circuit 131, since the transistors N11 and N12 are both provided, the signal O
The signal level of the UT 21 is determined based on the lower one of the characteristic lines 136 and 137. Therefore, the characteristic line 138 changes along the characteristic line 136 when the voltage VLS changes from the voltage value VCC to the voltage value VA, and changes when the voltage VLS changes from the voltage value VA to the voltage value VLS.
37. When the voltage VLS takes a voltage value equal to or higher than the voltage value VA, the signal level of the signal OUT21 is determined based on the current flowing through the transistor N12, and an increase in the signal level can be suppressed.

FIG. 19 shows a level conversion circuit 141 as another configuration example of the second embodiment. Level conversion circuit 14
In FIG. 1, the same components as those of the level conversion circuit 131 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 141 includes a P-channel MOS transistor P1 and an N-channel MOS transistor P1.
It is configured to include channel MOS transistors N11 and N12 and an output circuit 84. The configuration of the input stage of the level conversion circuit 141 is the same as that of the input stage of the level conversion circuit 131, and the signal OUT21 is supplied to each gate of the transistors P3 and N3 of the output circuit 84.

FIG. 20 shows a level conversion circuit 151 which is still another configuration example of the second embodiment. In the level conversion circuit 151, the same components as those of the level conversion circuit 131 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 151 includes a P-channel MOS transistor P1
And N-channel MOS transistors N11 and N12;
An output circuit 94 is included. Level conversion circuit 1
The configuration of the input stage 51 is the same as that of the input stage of the level conversion circuit 131, and the signal OUT21 is supplied to the gates of the transistors N4 and N5 of the output circuit 94.

The transistors P4 and P4 in the output circuit 94
N4 has a configuration similar to the transistors P2 and N2 of the output circuit 34, but the ground voltage GND is applied to the gate of the transistor P4 and the voltage VLS is applied to the source of the transistor P4.
Is given. The signal level of the signal OUT22, which is the voltage at the connection point between the transistors P4 and N4, is the voltage VLS, VLS
SS. Signal OUT21 and signal OUT2
2 has a relationship where the signal level is inverted.

Since the signal OUT21 is provided to the gate of the transistor N5 and the signal OUT22 is provided to the gate of the transistor N6, one of the transistors N5 and N6 is turned on and the other is cut off. The transistors N5 and N6 control the conduction / cutoff of the transistors P5 and P6 whose sources are supplied with the voltage VCC, and determine the signal level of the output signal OUT.

FIG. 21 shows the level conversion circuit 151a.
The level conversion circuit 151a includes a transistor N13 having a gate supplied with the ground voltage GND, instead of the transistor N12 in the level conversion circuit 151. The operation is the same as that of the level conversion circuit 151.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and
When the level conversion circuits 131, 141, 151, and 151a operate with the negative power supply specification, the transistor N12 that operates as a load is provided in parallel with the transistor N11. The charge can be discharged quickly, and the delay time of the signal when the input signal IN rises can be shortened.
Further, the provision of the transistor N12 allows the signal O
Since the signal level of UT1 is reduced, the capacitor C
And the time required for discharging the charges is reduced, and the signal delay time when the input signal IN rises can be shortened.

FIG. 22 shows a level conversion circuit 161 according to a third embodiment of the present invention. Level conversion circuit 161
In FIG. 7, the same components as those of the level conversion circuit 31 are denoted by the same reference numerals, and description thereof will be omitted. Level conversion circuit 1
61 includes a P-channel MOS transistor P1, N-channel MOS transistors N11, N12, and N14, and an output circuit 34.

A feature of the level conversion circuit 161 is that a transistor N14 operating as a resistor is provided in series with the transistor N12 between the drain of the transistor N12 and the drain of the transistor P1. The source of the transistor N14 is connected to the drain of the transistor N12, and the drain and the gate are connected.

The operation of the transistors N11 and N12 in the level conversion circuit 161
The description is omitted because it is the same as 31. In the level conversion circuit 161, the transistor N14 is connected in series to the transistor N12, and the resistance value as the load for the negative power supply increases. The drain voltage of the transistor P1 is supplied as a signal OUT31 to the gate of the transistor N2 of the level conversion circuit 34.

FIG. 23 is a circuit diagram of a level conversion circuit 171 as another configuration example of the third embodiment. In the level conversion circuit 171, the same components as those in the level conversion circuit 161 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 171 includes a P-channel MOS transistor P
1 and N-channel MOS transistors N11, N12,
N14 and an output circuit 84. The input stage of the level conversion circuit 171 has the same configuration as that of the input stage of the level conversion circuit 161.
4 provided to the gates of the transistors P3 and N3.

FIG. 24 is a circuit diagram of a level conversion circuit 181 which is still another configuration example of the third embodiment. In the level conversion circuit 181, the same components as those of the level conversion circuit 161 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 181 includes a P-channel MOS transistor P1, an N-channel MOS transistor N11,
N12 and N14 and an output circuit 94 are included. The input stage of the level conversion circuit 181 has the same configuration as that of the input stage of the level conversion circuit 161, and the signal OUT31 is supplied to each gate of the transistors N4 and N5 of the output circuit 94. The signal OUT32 obtained by inverting the signal level of the signal OUT31 is supplied to the gate of the transistor N6.

FIG. 25 shows the level conversion circuit 181a.
The level conversion circuit 181a is provided with a transistor N13 having a gate supplied with the ground voltage GND instead of the transistor N12 in the level conversion circuit 181. The operation is the same as that of the level conversion circuit 181.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and the level conversion circuits 161, 171, 181, and 181 a are of the positive power supply specification or the negative power supply specification. The transistor N14 that operates as a resistor is provided in series with the transistor N12 whose resistance value changes during conduction depending on whether
The value of the combined resistance when operating with the negative power supply specification can be controlled by the resistance value of the transistor N14. Further, in the case of the positive power supply specification, the transistor N14 can reduce the signal level of the signal OUT1, and can increase the margin of the input inversion level. Since the transistor operates as a resistor, the level conversion circuit can be formed smaller than when a resistor having the same resistance value is formed.

FIG. 26 shows a level conversion circuit 191 according to a fourth embodiment of the present invention. Level conversion circuit 191
In FIG. 7, the same components as those of the level conversion circuit 31 are denoted by the same reference numerals, and description thereof will be omitted. Level conversion circuit 1
Reference numeral 91 denotes a P-channel MOS transistor P1, N-channel MOS transistors N11 and N12, and a resistor R1.
And an output circuit 34.

A feature of the level conversion circuit 191 is that a resistor R1 is provided in series with the transistor N12 between the drain of the transistor N12 and the drain of the transistor P1. The operation of the transistors N11 and N12 in the level conversion circuit 191 is the same as that of the level conversion circuit 131, and thus the description is omitted. In the level conversion circuit 191, the resistor R1 is connected in series to the transistor N12, and the resistance value as the load for the negative power supply increases. The drain voltage of the transistor P1 is given as a signal OUT41 to the gate of the transistor N2 of the output circuit 34.

FIG. 27 shows a level conversion circuit 201 as another configuration example of the fourth embodiment. Level conversion circuit 20
In FIG. 1, the same components as those of the level conversion circuit 191 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 201 includes a P-channel MOS transistor P1 and an N-channel MOS transistor P1.
Channel MOS transistors N11 and N12 and a resistor R
1 and an output circuit 84. The configuration of the input stage of level conversion circuit 201 is the same as the configuration of the input stage of level conversion circuit 191, and signal OUT 41 is applied to the gates of transistors N 3 and P 3 of output circuit 84.

FIG. 28 is a circuit diagram of a level conversion circuit 211 which is still another configuration example of the fourth embodiment. In the level conversion circuit 211, the same components as those in the level conversion circuit 191 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 211 includes a P-channel MOS transistor P1, an N-channel MOS transistor N11,
The circuit includes an N12, a resistor R1, and an output circuit 94. The configuration of the input stage of level conversion circuit 211 is the same as the configuration of the input stage of level conversion circuit 191, and signal OU
T41 is applied to the gates of the transistors N4 and N5 of the output circuit 94. The signal OUT42 obtained by inverting the signal level of the signal OUT41 is supplied to the gate of the transistor N6.

FIG. 29 shows the level conversion circuit 211a.
The level conversion circuit 211a includes a transistor N13 having a gate supplied with the ground voltage GND, instead of the transistor N12 in the level conversion circuit 211. The operation is the same as that of the level conversion circuit 211.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained.
Depending on whether the level conversion circuits 191, 201, 211, and 211 a are of the positive power supply specification or the negative power supply specification, the resistor R <b> 1 is provided in series with the transistor N <b> 12 whose resistance value changes during conduction. The value of the combined resistance when operating according to the specifications can be determined by controlling the resistance value of the resistor R1. Further, in the case of the positive power supply specification, the transistor N14 can reduce the signal level of the signal OUT1, and can increase the margin of the input inversion level.

FIG. 30 shows a level conversion circuit 221 according to a fifth embodiment of the present invention. Level conversion circuit 221
In the figure, the same components as those of the level conversion circuit 101 are denoted by the same reference numerals, and description thereof is omitted. The level conversion circuit 221 includes a P-channel MOS transistor P1, an N-channel MOS transistor N11, and a resistance circuit 222.
And an output circuit 34. A feature of the level conversion circuit 221 is that a resistance circuit 222 is provided in parallel with the transistor N11.

The resistance circuit 222 includes n N-channel MOS transistors NT1 to NTn (n is 2
The above integers; the collective reference numeral NT is used) are connected in series. The number of saws n of the transistors NT connected in series is determined based on the following equation (9). Note that each transistor N
Let the threshold voltage of T be voltage Vth.

N × Vth = VCC × VSS (9) The transistor NT connected in series outputs the signal OUT51.
Operates as a resistor when the signal level becomes higher than the voltage VCC. Therefore, transistor NT operates as a resistor only when level conversion circuit 221 operates with the negative power supply specification.

FIG. 31 shows a level conversion circuit 231 as another configuration example of the fifth embodiment. Level conversion circuit 23
In FIG. 1, the same components as those of the level conversion circuit 111 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 231 includes a P-channel MOS transistor P1 and an N-channel MOS transistor P1.
Channel MOS transistor N11 and resistance circuit 222
And an output circuit 84. The configuration of the input stage of the level conversion circuit 231 is the same as the configuration of the input stage of the level conversion circuit 221.
4 are provided to the gates of the transistors P3 and N3.

FIG. 32 is a circuit diagram of a level conversion circuit 241 which is still another configuration example of the fifth embodiment. In the level conversion circuit 241, the same components as those of the level conversion circuit 121 are denoted by the same reference numerals, and description thereof will be omitted. The level conversion circuit 241 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N11.
, A resistance circuit 222, and an output circuit 94. The configuration of the input stage of level conversion circuit 241 is the same as the configuration of the input stage of level conversion circuit 221, and signal OU
T51 is supplied to the gates of the transistors N4 and N5 of the output circuit 94. The signal OUT52 obtained by inverting the signal level of the signal OUT51 is provided to the gate of the transistor N6.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and
When operating with the negative power supply specification, even when the difference between the voltage VCC and the voltage VSS is large and the resistance value of the resistor provided in parallel with the transistor N11 needs to be determined to be large, the plurality of transistors operating as resistors Are connected in series to form a resistor having a desired resistance value, so that the area of the substrate can be reduced when an integrated circuit is formed.

In each of the above-described embodiments, the transistors P1 and N1 constituting the input stage can be configured to have a low withstand voltage since no high voltage is applied.
The circuit portion is smaller than the configuration of the output stage to which a voltage of 0 to 40 V is applied, and the area of the level conversion circuit can be reduced. Further, the input and output transistors constituting the level conversion circuit have a so-called medium withstand voltage configuration that can operate even when a voltage of 20 to 40 V is applied, so that the input and output stages have different withstand voltages. Variations in characteristics can be suppressed as compared with the case of a configuration.

[0122]

As described above, according to the present invention, whether the third voltage level is the first voltage level side or the second voltage level side from the reference voltage level depends on the signal level of the input signal. The level of the output signal can be, for example, a positive voltage or a negative voltage with respect to the reference voltage level, and the level of the input signal is converted to either positive or negative according to the voltage supplied to the output side switching means. be able to.

Further, according to the present invention, whether the third voltage level is the first voltage level side or the second voltage level side with respect to the reference voltage level, the third voltage level is the reference voltage level of the input signal. And a second load unit that operates when the third voltage level is set to the second voltage level side of the reference voltage level of the input signal. Since either one of the load means operates, the characteristic of the first load means and the characteristic of the second load means are different from each other, so that the voltage level supplied as the third voltage level is reduced. Accordingly, it is possible to operate the load means having characteristics suitable for converting the level of the input signal to the reference voltage level, for example, either positive or negative.

Further, according to the present invention, the resistance values of the first and second load means are determined depending on whether the third voltage level is the first voltage level side or the second voltage level side with respect to the reference voltage level. Since one of the load means operates as a load, the characteristic of the first load means and the characteristic of the second load means are respectively different from each other, so that the characteristic of the first load means is different from the characteristic of the second load means. Thus, the load means having a characteristic suitable for converting the level of the input signal to the reference voltage level, for example, either positive or negative, can be operated.

Further, according to the present invention, the resistance value of the first load means in which the power supply voltage of the first voltage level is applied to the control electrode so that the input side switching element is in the conductive state so that the control electrode is always in the conductive state. Greater than a certain resistance value,
Since the resistance value is set to be smaller than the resistance value in the cutoff state, the control terminal of the output side switching means is given to one output electrode of the input side switching element when the input side switching element is in the conductive state. The power supply voltage at the first voltage level is applied, and when the power supply is in the cutoff state, the power supply voltage at the second voltage level applied to the other output electrode of the load element in the first load means can be applied.

Further, according to the present invention, the resistance value of the second load means, in which the power supply voltage of the first voltage level is applied to the control electrode so as to be always in the conductive state, is determined when the input side switching element is in the conductive state. Greater than a certain resistance value,
Since the resistance value is set to be smaller than the resistance value in the cutoff state, the control terminal of the output side switching means is given to one output electrode of the input side switching element when the input side switching element is in the conductive state. The power supply voltage at the first voltage level is applied, and when the power supply is in the cutoff state, the power supply voltage at the second voltage level applied to the other output electrode of the load element in the first load means can be applied.

Further, according to the present invention, the third and fourth voltage levels are changed according to whether the voltage level of the input signal is on the first voltage level side or the second voltage level side with respect to the reference voltage. The power supply voltage can be selectively output.

Further, according to the present invention, according to the voltage level of the other output electrode of the input-side switching element applied to each control electrode via the control terminal, only one of the one and the other switching element is made conductive. Since the voltage is output to the signal output terminal, power supply voltages of different voltage levels are supplied to the control electrode, so that conduction between one and the other power supply terminals does not occur, and the current flowing through the output side switching means is reduced. be able to.

Further, according to the present invention, the output-side switching means includes a first switching element, a second switching element, and a bridge circuit, and outputs the other output electrode of each of the first and second switching elements. The voltage level is provided to the bridge circuit. The bridge circuit is the first
The third and fourth switching elements have the same conductivity type as the switching element, and the fifth and sixth switching elements have the same conductivity type as the second switching element. One output electrode of the fifth and sixth switching elements is connected to the other power supply terminal, and one output electrode of the third and fourth switching elements is connected to one power supply terminal. The other output electrode of the third and fifth switching elements and the control electrode of the fourth switching element are commonly connected. The other output electrodes of the fourth and sixth switching elements and the control electrode of the third switching element are commonly connected and are connected to a signal output terminal. Since the voltage level output from the bridge circuit is determined by the voltage level of the other output electrode of the input-side switching element and the inverted voltage level, power supply voltages of different voltage levels are supplied between one and the other power supply terminals. Are not conducted, and the current flowing through the output-side switching means can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit 31 according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a gate driver 41.

FIG. 3 is a block diagram illustrating a configuration of a display device 51.

FIG. 4 is a diagram showing a relationship between an input and an output in a gate driver 41.

FIG. 5 is a timing chart of each signal in the gate driver 41.

FIG. 6 is a diagram for explaining the operation of the level conversion circuit 31 in the case of a positive power supply specification.

FIG. 7 is a graph showing a relationship between a voltage value of a voltage VLS and a signal level of a signal OUT1 in a level conversion circuit 31;

FIG. 8 is a block diagram illustrating a configuration of a gate driver 41a.

FIG. 9 is a diagram illustrating a relationship between an input and an output in a gate driver 41a.

FIG. 10 is a circuit diagram of a level conversion circuit 81 as another configuration example of the first embodiment.

FIG. 11 is a circuit diagram of a level conversion circuit 91 as still another configuration example of the first embodiment.

FIG. 12 is an equivalent circuit diagram of the level conversion circuits 31, 81, and 91 when a positive power supply specification and a negative power supply specification are used.

FIG. 13 is a circuit diagram of the level conversion circuit 101.

14 is a circuit diagram of the level conversion circuit 111. FIG.

FIG. 15 is a circuit diagram of the level conversion circuit 121.

FIG. 16 is a circuit diagram showing a configuration of a level conversion circuit 131 according to the second embodiment of the present invention.

FIG. 17 is a diagram showing a relationship between an input signal and an output signal in the level conversion circuit 131.

FIG. 18 is a diagram illustrating a relationship between a voltage value of a voltage VLS and a signal level of a signal OUT21 in the level conversion circuit 131.

FIG. 19 is a circuit diagram of a level conversion circuit 141 as another configuration example of the second embodiment.

FIG. 20 is a circuit diagram of a level conversion circuit 151 which is still another configuration example of the second embodiment.

FIG. 21 is a circuit diagram of a level conversion circuit 151a similar to the level conversion circuit 151.

FIG. 22 is a circuit diagram showing a configuration of a level conversion circuit 161 according to the third embodiment of the present invention.

FIG. 23 is a circuit diagram of a level conversion circuit 171 as another configuration example of the third embodiment.

FIG. 24 is a circuit diagram of a level conversion circuit 181 as still another configuration example of the third embodiment.

FIG. 25 is a circuit diagram of a level conversion circuit 181a similar to the level conversion circuit 181.

FIG. 26 is a circuit diagram showing a configuration of a level conversion circuit 191 according to a fourth embodiment of the present invention.

FIG. 27 is a circuit diagram of a level conversion circuit 201 as another configuration example of the fourth embodiment.

FIG. 28 is a circuit diagram of a level conversion circuit 211 as still another configuration example of the fourth embodiment.

FIG. 29 is a circuit diagram of a level conversion circuit 211a similar to the level conversion circuit 211.

FIG. 30 is a circuit diagram showing a configuration of a level conversion circuit 221 according to a fifth embodiment of the present invention.

FIG. 31 is a circuit diagram of a level conversion circuit 231 as another configuration example of the fifth embodiment.

FIG. 32 is a circuit diagram of a level conversion circuit 241 as still another configuration example of the fifth embodiment.

FIG. 33 is a block diagram showing a configuration of a gate driver 11 generally used conventionally.

FIG. 34 is a circuit diagram of a level shifter 13 included in the gate driver 11.

FIG. 35 is a diagram showing a relationship between an input and an output in the gate driver 11.

FIG. 36 shows another conventional gate driver 11a.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 37 is a circuit diagram of a level shifter 17 included in the gate driver 11a.

FIG. 38 is a diagram showing a relationship between an input and an output in the gate driver 11a.

[Explanation of symbols]

20, 31, 81, 91, 101, 111, 121, 1
31, 141, 151, 151a, 161, 171, 1
81, 181a, 191, 201, 211, 211a,
221, 211, 241 Level conversion circuit 32 Switching element 33 Load 34, 84, 94 Output circuit 36 Control terminal 37 One power supply terminal 38 The other power supply terminal 39 Signal output terminal 41, 41a Gate driver 42, 42a Shift register 43, 43a Level shifter 44 , 44a Output buffer 51 Display device 52 Source driver 53 Liquid crystal display panel 54 Control circuit 55 Power supply circuit P1-P6 P-channel MOS transistors N1-N6, N11-N14, NT1-NTn N-channel MOS transistors

Claims (8)

(57) [Claims] An input signal, which is applied to a signal input terminal and changes between a first voltage level and a second voltage level as a reference voltage level and changes within a predetermined amplitude, is converted to a different voltage level as a reference. A level conversion circuit having one output electrode, the other output electrode and a control electrode, one output electrode being connected to a power supply voltage of a first voltage level, and the other output electrode being supplied with a power supply voltage of a second voltage level;
The control electrode is connected to the signal input terminal, and sets a voltage level within a predetermined amplitude of the input signal as a threshold value, and according to whether the input signal is on the first voltage level side or the second voltage level side,
An input-side switching element that changes so as to be interrupted or conductive between one output electrode and the other output electrode, and an input-side load connected between the other output electrode of the input-side switching element and a power supply voltage at a second voltage level Means, one power supply terminal, the other power supply terminal, a signal output terminal and a control terminal, one power supply terminal is supplied with a power supply voltage of a third voltage level, and the other power supply terminal is supplied with a second voltage level of the first voltage level.
A power supply voltage having a fourth voltage level different from the third voltage level is supplied in a direction different from the voltage level, the control terminal is connected to the other output electrode of the input-side switching element,
A threshold value of a voltage level between the voltage level and the second voltage level, while determining whether the voltage level of the output electrode is on the first voltage level side or on the second voltage level side of the threshold value Output level switching means for respectively deriving a voltage closer to the third voltage level or closer to the fourth voltage level from the signal output terminal. 2. The input-side load unit operates when the third voltage level is closer to the first voltage level than the reference voltage level of the input signal, and
2. The level conversion circuit according to claim 1, further comprising: a second load unit that operates when the voltage level is on the voltage level side. 3. The first load means and the second load means are connected in parallel, and when the third voltage level is closer to the first voltage level than a reference level of the input signal, the second load means The resistance value becomes larger than the resistance value of the first load means.
3. The level conversion circuit according to claim 2, wherein the resistance value of the load means is larger than the resistance value of the second load means. 4. The first load means includes one output electrode, the other output electrode and a control electrode, one output electrode being connected to the power supply voltage of the second voltage level, and the control electrode being connected to the third voltage level. The other output electrode is connected to the power supply voltage, the other output electrode is connected to the other output electrode side of the input-side switching element, and is always in a conductive state. 4. The level conversion circuit according to claim 3, further comprising a load element having a resistance value smaller than the resistance value in the state. 5. The second load means includes one output electrode, another output electrode, and a control electrode, one output electrode being connected to a power supply voltage of the second voltage level, and a control electrode being connected to the first voltage level. The other output electrode is connected to the power supply voltage, the other output electrode is connected to the other output electrode side of the input-side switching element, and is always in a conductive state. 4. The level conversion circuit according to claim 3, further comprising a load element having a resistance value smaller than the resistance value in the state. 6. The output-side switching means includes one output electrode, another output electrode, and a control electrode, one output electrode is connected to the other power supply terminal, and the other output electrode is connected to the signal output terminal, A control element connected to the control terminal, the switching element having a threshold of a voltage level between the first voltage level and the second voltage level; and a second output electrode of the switching element and the one power supply terminal. 2. The level conversion circuit according to claim 1, further comprising: an output-side load means connected between the two. 7. The output-side switching means includes one output electrode, the other output electrode, and a control electrode, has the same conductivity type as the input-side switching element, and has one output electrode connected to the one power supply terminal. The other output electrode is connected to the signal output terminal, and the control electrode is connected to the control terminal. The switching element has one output electrode, the other output electrode and a control electrode, and is complementary to the input side switching element. One output electrode is connected to the other power supply terminal, the other output electrode is connected to the signal output terminal, and the control electrode includes the other switching element connected to the control terminal. The level conversion circuit according to claim 1, wherein: 8. The output-side switching means includes one output electrode, the other output electrode, and a control electrode, and has the same conductivity type as the input-side switching element, while the output electrode has a power supply of the first voltage level. A first switching element which is connected to a voltage, is supplied with a reference voltage level of the input signal to a control electrode, and is always in a conductive state; and an output electrode, the other output electrode and a control electrode, the input-side switching element comprising: Has a complementary conductivity type, one output electrode is connected to the power supply voltage of the second voltage level, the other output electrode is connected to the other output electrode of the first switching element, and the control electrode is connected to the control terminal. A second switching element connected and having a threshold between the first voltage level and the second voltage level; and having the same conductivity type as the first switching element. A bridge circuit formed by third and fourth switching elements and fifth and sixth switching elements having the same conductivity type as the second switching element, wherein one output electrode of the fifth and sixth switching elements is One output electrode of the third and fourth switching elements is connected to the other power supply terminal, and the other output electrode of the third and fifth switching elements and the control electrode of the fourth switching element are commonly connected. , The other output electrode of the fourth and sixth switching elements and the control electrode of the third switching element are commonly connected and connected to the signal output terminal, and the control electrode of the sixth switching element is connected to the other output electrode of one switching element. 2. The level conversion circuit according to claim 1, further comprising a bridge circuit.