JPS6321918B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an acoustic signal generation circuit.

2. Description of the Related Art Conventionally, there has been a clock that generates an electronic melody as an alarm sound, and a melody generating circuit such as that shown in FIG. 1 has been used as the melody generating circuit. Regarding this configuration, the melody circuit M in which the melody is programmed in advance is a clock pulse generator.
In response to the output from the CL, an audible frequency signal with a frequency corresponding to the scale of each note that makes up the melody is generated at the output terminal _m1 as shown in Figure 2A, and an audible frequency signal is generated at the output terminal _m2 in synchronization with the start of generation of each note. As a result, attack pulses are generated as shown in Figure 2B, and each envelope circuit E
is supplied to the switching circuit S of. The switching circuit S consists of an analog switch, and the structure of the melody circuit M is described in detail in Japanese Patent Application Laid-Open No. 158967/1983 by the present applicant, and will therefore be omitted here.

Now, the envelope circuit E is provided with a time constant circuit consisting of a resistor _R1 and a capacitor _C1 ,
This time constant amplitude-modulates the audio frequency signal shown in FIG. 2A as shown in FIG. 2C. This modulated signal is supplied to the amplifier circuit A via the volume adjusting resistor _R2 , and the amplified signal is supplied from the terminal a to a speaker (not shown) to play a melody with a lingering sound.

However, according to this, the inverter V of the melody circuit M, the switching circuit S, and the amplifier circuit A
and a part consisting of field effect transistors f ₁ and f ₂
A′ is integrated, but the time constant circuit for amplitude modulation, the transistors T ₁ and T ₂ of the amplifier circuit A for amplifying the modulation signal, and the resistor
R ₃ , R ₄ and capacitors C ₂ to _{C 4} must be attached externally, which increases the number of external parts.

Further, since the amplifier circuit A is of a feedback type, oscillation and distortion may occur due to variations in elements. Furthermore, since an idle current flows, there is a drawback that current consumption increases.

In addition to the above, there is a method that generates attenuated sound by reducing the duty of the audio frequency signal in time series, but according to this, when the duty becomes smaller, the sound pressure decreases and the timbre changes, For example, if you use a square wave as an audio frequency signal, the square wave has a certain spectral distribution that determines the sound quality, and changing the duty of the audio frequency signal will cause the volume to change. At the same time, the spectral distribution also changes. Therefore, as the volume changes, the sound quality also changes. This also applies when a sine wave is used as the audio frequency signal.

The present invention eliminates the above-mentioned drawbacks of the conventional art, and particularly provides an audio signal generating circuit that extremely reduces the number of external parts and produces comfortable sound with a constant tone color and only a change in sound pressure.

An embodiment of the present invention will be described below based on the drawings. In FIG. 3, _CT1 is a 3-bit counter, and in this example, the terminal _l0 of the clock pulse generator CL.
A 32KHz pulse for pulse width modulation is generated from terminal _Q13 by receiving a 256KHz pulse from the terminal Q13. W is a one-shot pulse generator that generates a narrow pulse by the fall of this pulse, and _F1 is a flip-flop circuit that generates a carrier pulse. In this example, the frequency of the carrier pulse is set to 32KHz,
This carrier pulse is generated in synchronization with an audio frequency signal, and the duty of the carrier pulse is reduced almost logarithmically, thereby providing an envelope function. CT ₂ is a 4-bit counter that specifies the duty of the carrier pulse based on the sound pressure control information for performing the above envelope, B is a coincidence circuit, G ₁ and G ₂ are gate circuits, and D
is a frequency divider circuit, SE ₁ is a selection circuit, and from terminals l ₁ to _{l 3}
It receives pulses of 16Hz, 8Hz, and 4Hz and selects one of them. The above configuration is integrated into a single-chip integrated circuit, and the only external elements are a volume adjustment resistor _R2 , an amplification transistor _T3 , and a capacitor _C5.The output of the transistor _T3 is connected to a speaker SP. be.

Next, the operation will be explained. Melody circuit M
are the same as the same reference numerals in Figure 1, and the terminals m ₁ ,
_m2 generates the audio frequency signals and attack pulses shown in FIGS. 2A and 2B, respectively.
When the audio frequency signal is “1”, the counter _CT1 is reset, and the counter is reset by the attack pulse.
CT ₂ and frequency divider circuit D are reset.

Therefore, first, counter CT ₂ and gate circuit
Explain the output generated from G ₁ . These outputs are for logarithmically decreasing the duty of the carrier pulse. When the counter _CT2 is reset by the attack pulse P in FIG. 4A, all of its terminals _Q21 to _Q24 are held at "0". This opens the gate circuit G ₁ and selects the 16 Hz pulse from the terminal l ₁ by the selection circuit SE ₁ , which is supplied to the matching circuit B and the counter CT ₂ via the gate circuit G ₁ . . Figure 4B shows the output pulses from the gate circuit _G1 . When four pulses are supplied and the terminal _Q23 becomes "1", the selection circuit _SE1 outputs an 8Hz pulse from the terminal _L2 . selected. When two pulses are supplied and the terminals Q ₂₂ and Q ₂₃ become "1", the selection circuit SE ₁ selects the 4 Hz pulse from the terminal l ₃ . Therefore, terminal Q ₂₁ of counter CT ₂ ~
Pulses are generated from Q ₂₃ as shown in Figure 4 C, D, and E, respectively. Then, the duty of the carrier pulse is specified by the 4-bit output, in which the output from the gate circuit _G1 is the LSB and the output from the terminal _Q23 is the MSB, and the carrier pulse is generated as follows. . First, the operation within time _t1 immediately after the reset by the attack pulse P in FIG. 4A is released will be described. The audio frequency signal from terminal _m1 of melody circuit M is “1”
When , the counter _CT1 is reset and the gate circuit _G2 is closed. Then, when the audio frequency signal is reversed to "0" as shown in Figure 5A,
The reset of the counter _CT1 is released and the gate circuit _G2 is opened. Therefore, the counter CT ₁ counts 256 KHz pulses from the terminal l ₀ (FIG. 5B), and the output terminals Q ₁₁ to _{Q 13} generate pulses as shown in FIGS. 5C, D, and E, respectively. When terminals l ₀ , Q ₁₁ , Q ₁₂ and Q ₁₃ are all "0", a coincidence pulse is generated from coincidence circuit B as shown in FIG. 5F, and flip-flop circuit F ₁ is set. Also,
The fall of the pulse from the terminal _Q13 generates a narrow pulse from the one-shot pulse generator W as shown in FIG. 5G, which is supplied to the reset input of the flip-flop circuit _F1 at the same time as the coincidence pulse.
However, since the pulse width of the coincidence pulse is longer, the flip-flop circuit _F1 is held in the set state, and its output Q is held at "1". That is, as shown in FIG. 5H, the duty of the carrier pulse Pc is maintained at "1". Therefore, when the audio frequency signal is shown in FIG. 6A, during time _t1 , a pulse whose level is inverted is generated from the gate circuit _G2 as shown in FIG. 6B, and the maximum sound pressure is emitted from the speaker Sp. A sound is produced.

Next, at time t ₂ in Fig. 4, the gate circuit
Since only the output of G ₁ is "1", when only the pulse shown in FIG. 5B from terminal l ₀ is "1", a matching pulse is generated from matching circuit B as shown in FIG. ₁ is set. On the other hand, the one-shot pulse generator W generates a pulse as shown in FIG. 7B in the same manner as above, and the flip-flop circuit _F1 is reset. Therefore, a carrier pulse Pc with a duty of 15/16 is generated from the output Q of the flip-flop circuit _F1 as shown in Fig. 7C.
This passes through gate circuit _G2 as shown in Figure 6C,
The sound pressure from speaker Sp drops very slightly.

Similarly, from time _t3 to _{time t8} , the duty of the carrier pulse Pc decreases by 1/16 at regular intervals as shown in Figure 8, and at time _t9 , the duty decreases to 1 as shown in Figure 6D. /2. Then, from time t ₉ to t ₁₂ , the duty of the carrier pulse Pc decreases by 1/16 at a time interval that is twice the above value, and from time t ₁₃ to t ₁₆ , at a time interval that is twice that above. The duty decreases by 1/16. At time t ₁₆ , carrier pulse Pc
The duty is 1/16 as shown in Figure 6E.

As described above, gate circuit G ₂ generates an AND output between the audio frequency signal and the carrier pulse.
The duty of this carrier pulse decreases approximately logarithmically as shown in FIG. Therefore, high-quality sound with a lingering sound is generated from the speaker SP. Only the volume of this sound changes depending on the duty of the carrier pulse, and the sound quality does not change. The reason for this is explained below. Generally, an electromagnetic speaker is used in this type of speaker, and its output characteristics are set so that it is flat in the audible frequency band, and so that no output is produced in the inaudible frequency band. Therefore, when the duty of the carrier pulse is changed, a change in the spectral distribution occurs in a region higher than the audible frequency, and within the audible region, the spectral distribution does not change, and only the magnitude of each spectral component changes uniformly. Therefore, only the volume changes without changing the sound quality.

By the way, when the terminal Q ₂₄ of the counter CT ₂ becomes "1", the gate circuits G ₁ and G ₂ are closed and the generation of the above-mentioned sound is stopped, and when the next attack pulse arrives, the same operation as above is performed.

Note that the above example is not limited to the above example, and it is also possible to preset the contents of the counter CT ₂ for duty specification into a preset counter, and to detect when the contents of this counter become all "0" or all "1". The duty may be controlled by

By the way, in the above example, the pulse supplied to counter CT ₁ has a high frequency of 256KHz, so
When a match is made in match circuit B, the counter CT ₁ ,
The delay time associated with the carry of CT ₂ poses a problem in actual circuit design, and may cause malfunctions, but this can be temporarily resolved by using a synchronous counter. However, 1.5V C-MOS LSI
When configured as
Hz), it is difficult to guarantee the operation of matching circuits and the like.

Therefore, an embodiment that eliminates the above-mentioned danger will be described below.

In Fig. 9, CT ₃ and CT ₄ are 4-bit counters, G ₃ to _{G 6} are gate circuits, F ₂ to _{F 4} are flip-flop circuits, V ₁ and V ₂ are inverters, and WR is a retriggerable one shot. Pulse generator, SE ₂ is the selection circuit. Note that the same reference numerals as in FIG. 3 indicate the same parts.

In the above configuration, counter CT ₃ has terminal l ₀
The 256KHz pulse shown in Fig. 10A is supplied from the output terminals _Q31 to _Q34, respectively.
As shown in Figures B to E, pulses of 128, 64, 32, and 16KHz are generated. Therefore, when an attack pulse is supplied to terminal _m2 , a pulse with a width of about 1 second is generated from the one-shot pulse generator WR, and the gate circuit
G ₄ opens.

The flip-flop circuit _F3 is reset by the attack pulse, and the selection circuit _SE2 selects the 16 Hz pulse from the terminal _l1 based on its output and supplies it to the flip-flop circuit _F2 . The flip-flop circuit _F2 converts the above 16Hz pulse rise and fall from the terminal _l0 .
This is to synchronize with the falling edge of the 256KHz pulse. When the generation of the attack pulses stops, the reset of the flip-flop circuit _F3 is released and the flip-flop circuit _F4 is reset.
The D input of becomes “0” and the terminal of counter _CT4
The fall of the pulse from _Q34 inverts the output of the flip-flop circuit _F4 to "0", and the counter
CT ₄ reset is released. In other words, at the same time that the contents of counter CT ₃ become (0000), the counter
CT ₄ reset is released. Moreover, the selection circuit
The 16Hz pulse from the terminal _l1 selected by _SE2 and the attack pulse are synchronized, and immediately after the attack pulse stops generating, the terminal _l1
Since the pulse from the flip-flop circuit _F2 is "0", one input of the gate circuit _G3 becomes "0" due to the output of the flip-flop circuit F2. Therefore, the same pulse as the pulse from the terminal _l0 is generated from the gate circuit _G3 , and the counters _CT3 and _CT4 are counted up in exactly the same way. Therefore, the pulses from each output terminal Q ₃₄ and Q ₄₄ match, the output of gate circuit G ₆ is held at “1”, and the audio frequency signal from terminal m ₁ is directly passed through gate circuit G ₇ . pass. That is,
The duty of the carrier pulse is 1.

On the other hand, an AND output of the pulses shown in FIG. 10C and D is generated from the gate circuit _G5 , and a pulse whose level is inverted is generated from the inverter _V1 as shown in FIG. 10F, and its fall causes the output of the inverter _V2. is written to flip-flop circuit _F3 . now,
Since the output of inverter _V2 is held at "0", flip-flop circuit _F3 holds the above state.

Then, the 16Hz pulse from terminal _l1 is inverted to "1", and the output of flip-flop circuit _F2 becomes the 11th
When inverted to “1” as shown in Figure A, the gate circuit
The output pulse from _G3 is level inverted as shown in FIG. 11B. Therefore, the output pulse of the counter CT ₄ lags the output pulse of the counter CT ₃ by 1/256 x 1/2 x 10 ^-3 seconds, and a pulse is generated from the terminal Q ₄₄ as shown in FIG. 11C. Therefore, terminal Q ₃₄ ,
The above phase difference occurs in the pulse from Q ₄₄ , and a carrier pulse of 32 KHz and duty 15/16 is generated from gate circuit G ₆ as shown in FIG. 11D.

And the above 16Hz pulse from terminal _l1 is
When the output of the flip-flop circuit _F2 is inverted to "0", the level of the output pulse from the gate circuit _G3 is inverted again. Therefore, the same phase difference as above is further added to the output pulse of the counter CT ₄ , and the duty of the carrier pulse from the gate circuit G ₆ becomes 14/16.

Similarly, the duty of the carrier pulse decreases by 1/16 each time the level of the 16 Hz pulse from terminal _l1 is reversed. Then, when the duty of the carrier pulse becomes 4/16, the output of the inverter _V2 is inverted to "1" in synchronization with the fall of the pulse shown in FIG. 10F from the inverter _V1 , so the output of the flip-flop circuit _F3 is reversed. This selects a 4Hz pulse from terminal _l3 ,
Thereafter, the duty of the carrier pulse decreases by 1/16 each time the level of this 4 Hz pulse is reversed.

In this way, the duty of the carrier pulse from the gate circuit _G6 changes stepwise as shown in FIG. When one second has elapsed since the generation of the attack pulse, the pulse from the one-shot pulse generator WR is stopped and the gate circuit _G7 is closed.

Note that when playing short notes continuously,
The next attack pulse arrives before the above operation is completed, but this causes the output pulse from the one-shot pulse generator WR to be extended for 1 second.
The above operation is performed from the beginning.

According to this embodiment, only the most significant bits of the counters CT ₃ and CT ₄ are compared in phase, and the inputs of each counter are synchronized, so there is no danger as in the previous embodiment. will disappear.

As described above, according to the present invention, the audio frequency signal is modulated into a pulse with a sufficiently shorter period than this, and the duty of this pulse is changed in stages, so that the entire configuration can be integrated. By simply attaching an external amplifier circuit with an extremely simple configuration and supplying output to it, a high-quality sound with a lingering resonance can be generated from a sound generating device. As an amplifier circuit, only a single transistor is required, and the sensitivity to variations in the electrical constants of the transistor is low. Furthermore, unlike conventional devices, oscillation and distortion do not occur, and since no idle current flows, current consumption is reduced, and the maximum sound pressure is also improved. Furthermore, since only the sound pressure decreases and the tone remains constant, extremely high-quality and comfortable acoustics such as damped sound can be obtained.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram showing a conventional example, Fig. 2 is a time chart explaining the operation, Fig. 3 is an electric circuit diagram showing an embodiment of the present invention, and Figs. 4 to 7 are respective operation diagrams. A time chart for explanation, FIG. 8 is an explanatory diagram showing the duty change of the output pulse of FIG. 3, FIG. 9 is an electric circuit diagram showing another embodiment, and FIGS. 10 and 11 are explanations of the respective operations. FIG. 12 is an explanatory diagram showing the duty change of the output pulse in FIG. 9. CT ₁ , CT ₂ ... Counter, B ... Matching circuit, F ₁
...flip-flop circuit, G ₁ , G ₂ ... gate circuit, SE ₁ ... selection circuit, W ... one-shot pulse generator, CT ₃ , CT ₄ ... counter, F ₂ , F ₃ ...
...Flip-flop circuit, G ₃ to G ₇ ... Gate circuit, V ₁ , V ₂ ... Inverter, SE ₂ ... Selection circuit.

Claims (1)

[Scope of Claims] 1. An acoustic signal generation circuit comprising a modulation circuit that modulates an audio frequency signal into a pulse with a sufficiently shorter period than this, and a control circuit that controls the duty of the pulse based on sound pressure control information. 2. The acoustic signal generating circuit according to claim 1, wherein the control circuit reduces the duty of the pulse approximately logarithmically.