JPS6321862U - - Google Patents
Info
- Publication number
- JPS6321862U JPS6321862U JP11609186U JP11609186U JPS6321862U JP S6321862 U JPS6321862 U JP S6321862U JP 11609186 U JP11609186 U JP 11609186U JP 11609186 U JP11609186 U JP 11609186U JP S6321862 U JPS6321862 U JP S6321862U
- Authority
- JP
- Japan
- Prior art keywords
- detection
- delay
- sensor
- inverter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 230000005856 abnormality Effects 0.000 claims description 2
Landscapes
- Indicating Or Recording The Presence, Absence, Or Direction Of Movement (AREA)
Description
第１図は本考案の実施例を示す速度異常検出回
路、第２図は第１図における近接スイツチ、第１
オンデイレイ、インバータ、第２オンデイレイ夫
々から出力される波形、第３図は従来の速度異常
検出回路、第４図は第３図における近接スイツチ
、オフデイレイ、インバータ夫々から出力される
波形である。
１…検出カム、２…近接スイツチ（センサー）
、４…第１オンデイレイ、５…インバータ、６…
ＯＲ素子、７…第２オンデイレイ。
FIG. 1 shows a speed abnormality detection circuit showing an embodiment of the present invention, and FIG. 2 shows a proximity switch in FIG.
FIG. 3 shows the waveforms output from the on-delay, inverter, and second on-delay, respectively. FIG. 4 shows the waveforms output from the proximity switch, off-delay, and inverter in FIG. 3, respectively. 1...Detection cam, 2...Proximity switch (sensor)
, 4...first on-day lay, 5...inverter, 6...
OR element, 7...second on-delay.
Claims (1)
配置された検出体と、該検出体を検出するセンサ
ーと、該センサーの検出信号が印加される第１オ
ンデイレイと、前記センサーの検出信号が印加さ
れるインバータと、該インバータの出力信号が印
加される第２オンデイレイと、前記第１オンデイ
レイと第２オンデイレイの出力信号が印加される
ＯＲ素子とからなるコンベア等の速度異常検出回
路。 a detection cam connected to a rotating shaft, a detection object disposed on the detection cam, a sensor for detecting the detection object, a first on-delay to which a detection signal of the sensor is applied, and a detection signal of the sensor A speed abnormality detection circuit for a conveyor or the like, comprising an inverter to which voltage is applied, a second on-delay to which an output signal of the inverter is applied, and an OR element to which output signals of the first on-delay and the second on-delay are applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11609186U JPS6321862U (en) | 1986-07-29 | 1986-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11609186U JPS6321862U (en) | 1986-07-29 | 1986-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6321862U true JPS6321862U (en) | 1988-02-13 |
Family
ID=31000358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11609186U Pending JPS6321862U (en) | 1986-07-29 | 1986-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6321862U (en) |
-
1986
- 1986-07-29 JP JP11609186U patent/JPS6321862U/ja active Pending
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