JPS632170B2 - - Google Patents

Info

Publication number
JPS632170B2
JPS632170B2 JP11093280A JP11093280A JPS632170B2 JP S632170 B2 JPS632170 B2 JP S632170B2 JP 11093280 A JP11093280 A JP 11093280A JP 11093280 A JP11093280 A JP 11093280A JP S632170 B2 JPS632170 B2 JP S632170B2
Authority
JP
Japan
Prior art keywords
input
filter
capacitor
switched capacitor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11093280A
Other languages
Japanese (ja)
Other versions
JPS5735410A (en
Inventor
Seiji Kato
Norio Ueno
Mitsuo Tsunoishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11093280A priority Critical patent/JPS5735410A/en
Publication of JPS5735410A publication Critical patent/JPS5735410A/en
Publication of JPS632170B2 publication Critical patent/JPS632170B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00Networks using time-varying elements, e.g. N-path filters
    • H03H19/004Switched capacitor networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Description

【発明の詳細な説明】 本発明はバイカツド(Biquad)回路を使用す
るフイルタにおいて入・出力端子の信号極性が同
相にできるフイルタに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a filter using a biquad circuit in which signal polarities at input and output terminals can be made in phase.

従来複数のスイツチドキヤパシタと積分器2段
で構成したバイカツド回路を使用するフイルタは
第1図に示す構成であつた。演算増幅器OP1
OP2と積分用コンデンサC1,C2(但しC1=C2=C
とする)による積分器を2段縦続接続し、スイツ
チドキヤパシタをK0C,K1C,K2C、K4Cの4
個、通常コンデンサK3Cとを使用したフイルタで
は入力電圧V1と出力電圧V2は逆極性となつてい
る。今スイツチドキヤパシタを接続した積分関数
を近似的にアナログ積分関数−1/S(S=jω)で 表わすと第2図の等価回路が得られる。
Conventionally, a filter using a biquad circuit composed of a plurality of switched capacitors and two stages of integrators has the configuration shown in FIG. Operational amplifier OP 1 ,
OP 2 and integrating capacitors C 1 and C 2 (C 1 = C 2 = C
), two stages of integrators are connected in cascade, and the switched capacitors are connected in four stages: K 0 C, K 1 C, K 2 C, and K 4 C.
In a filter using a capacitor K 3 C, the input voltage V 1 and the output voltage V 2 have opposite polarities. If the integral function connected to the switched capacitor is expressed approximately as an analog integral function -1/S (S=jω), the equivalent circuit shown in FIG. 2 is obtained.

第2図において α0=K0/T、α1=K1/T、α2=K2/T α3=K3、α4=K4/T (たゞしTはスイツチドキヤパシタのサンプリン
グ周期を示す。) と置いてV1、Vn、V2の間の関係を式で示すと Vn=α0(−1/S)V1+α1(−1/S)V2 ……(1) V2=−α2(−1/S)Vn+α4(−1/S)V2−α3V1
…(2) (1)(2)式からVnを消去してV2/V1を求めると V2/V1=−(α0α2+α3S2)/α1α2+α4S+S
2……(3) (3)式の負符号は入力信号V1に対して出力信号
V2は極性が反転することを示している。そのた
めV1と同相の出力信号V2を得る場合には、第1
図の出力部(或いは入力部)に位相反転用演算増
幅器を付加使用する必要がある。そのため消費電
力が増大し、フイルタが大型化・高価となる欠点
があつた。
In Figure 2, α 0 =K 0 /T, α 1 =K 1 /T, α 2 =K 2 /T α 3 =K 3 , α 4 =K 4 /T (T is the switched capacitor ), and the relationship between V 1 , V n , and V 2 is expressed by an equation: V n = α 0 (-1/S) V 1 + α 1 (-1/S) V 2 ...(1) V 2 =-α 2 (-1/S) V n4 (-1/S) V 23 V 1
...(2) Eliminate V n from equations (1) and (2) to find V 2 /V 1 : V 2 /V 1 = - (α 0 α 2 + α 3 S 2 ) / α 1 α 2 + α 4 S+S
2 ...(3) The negative sign in equation (3) is the output signal for input signal V 1 .
V 2 indicates that the polarity is reversed. Therefore, when obtaining an output signal V 2 that is in phase with V 1 , the first
It is necessary to additionally use an operational amplifier for phase inversion at the output section (or input section) shown in the figure. As a result, power consumption increases, and the filter becomes larger and more expensive.

本発明の目的は前述の欠点を改善し簡易な構成
で入力と同相の出力信号を得るバイカツド回路を
使用するフイルタを提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a filter using a biquad circuit which improves the above-mentioned drawbacks and obtains an output signal in phase with the input with a simple configuration.

以下図面に示す本発明の実施例について説明す
る。第3図は本発明の第1実施例を示す回路構成
図で第1図と同一の符号は同様のものを示してい
る。K3Cはコンデンサで第1段の積分器を構成す
る演算増幅器OP1に対しスイツチドキヤパシタ
K0Cと並列接続され、入力信号V1を通過させて
いる。第2段の積分器を構成する演算増幅器OP2
の入力にはスイツチドキヤパシタK2Cに対し並列
接続されたコンデンサK6Cと、入力信号V1を直
接印加するためのスイツチドキヤパシタK5Cとが
接続されている。K3CとK6Cを接続使用したこと
による不要出力信号成分をキヤンセルするための
コンデンサK5Cを使用している。第2図と同様に
等価回路を画くと第4図のようになる。第2図と
同様にV1,Vn,V2の関係式を求めると次のよう
になる。
Embodiments of the present invention shown in the drawings will be described below. FIG. 3 is a circuit configuration diagram showing a first embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same components. K 3 C is a switched capacitor for operational amplifier OP 1 , which constitutes the first stage integrator.
It is connected in parallel with K 0 C and passes the input signal V 1 . Operational amplifier OP 2 that constitutes the second stage integrator
A capacitor K 6 C connected in parallel to the switched capacitor K 2 C and a switched capacitor K 5 C for directly applying the input signal V 1 are connected to the input of the switch. A capacitor K 5 C is used to cancel unnecessary output signal components caused by connecting K 3 C and K 6 C. If the equivalent circuit is drawn in the same manner as in FIG. 2, it will become as shown in FIG. 4. The relational expression among V 1 , V n , and V 2 is found as follows in the same manner as in Fig. 2.

α0=K0/T、α1=K1/T、α2=K2/T、α3=K3 α4=K4/T、α5=K5/T、α6=K6 Vn=−α0(−1/S)V1+α1(−1/S)V2−α3V1
…(4) V2=−α2(−1/S)Vn+α4(−1/S)V2−α5
− 1/S) −α6Vn ……(5) (4)(5)式からVnを消去してV2/V1を求めると V2/V1=α0α2−(α2α3−α5
+α0α6)S+α3α6S2/α1α2+(α4−α1α6)S
+S2……(6) ここで α5=α2α3+α0α6 ……(7) となるように各容量値を選定すると(6)式は V2/V1=α0α2+α3α6S2/α1α2+(α4−α1α6
)S+S2……(8) となり、(8)式は(3)式と同様帯域消去フイルタの関
数を示している。(8)式の右辺には負符号がない。
これはV1とV2の極性が同相であることを示して
いる。即ち第4図の回路により入出力信号の位相
が反転してない帯域消去フイルタを実現できる。
α 0 = K 0 /T, α 1 = K 1 /T, α 2 = K 2 /T, α 3 = K 3 α 4 = K 4 /T, α 5 = K 5 /T, α 6 = K 6 V n =-α 0 (-1/S)V 11 (-1/S)V 23 V 1
…(4) V 2 = −α 2 (−1/S) V n4 (−1/S) V 2 −α 5 (
− 1/S) −α 6 V n ……(5) Eliminate V n from equations (4) and ( 5 ) to find V 2 /V 1. V 2 /V 1 = α 0 α 2 − (α 2 α 3 − α 5
0 α 6 )S+α 3 α 6 S 21 α 2 +(α 4 −α 1 α 6 )S
+S 2 ...(6) Here, if each capacitance value is selected so that α 5 = α 2 α 3 + α 0 α 6 ...(7), equation (6) becomes V 2 /V 1 = α 0 α 23 α 6 S 21 α 2 +(α 4 −α 1 α 6
)S+S 2 ...(8) Equation (8), like equation (3), represents the function of the band elimination filter. There is no negative sign on the right side of equation (8).
This shows that the polarities of V 1 and V 2 are in phase. That is, the circuit shown in FIG. 4 can realize a band elimination filter in which the phases of input and output signals are not inverted.

なお容量値を次の条件を満たすように選定する
と入出力信号の位相が同じの低域通過フイルタ、
高域通過フイルタ、帯域通過フイルタを実現する
こともできる。
If the capacitance value is selected to satisfy the following conditions, a low-pass filter with the same phase of input and output signals,
It is also possible to implement a high-pass filter or a band-pass filter.

A 低域通過フイルタ α5=α2α3+α0α6 α3=0(又はα6=0)とする。A Low-pass filter α 52 α 30 α 6 α 3 =0 (or α 6 =0).

V2/V1=α0α2/α1α2+(α4−α1α6)S+S2
…(9) B 高域通過フイルタ α5=α2α3+α0α6 α0=0とする V2/V1=α3α6S2/α1α2+(α4−α1α6)S+S2
……(10) C 帯域通過フイルタ α0=0、α3=0とする V2/V1=α5S/α1α2+(α4−α1α6)S+S2……(
11) 次に第5図は本発明の第2実施例として、入力
信号に対し同相逆相の2個の出力信号を得る場合
の回路構成図である。V1端子からの入力に対し
てはV2の出力が同相で、V3端子からの入力に対
してはV2の出力が逆相となる。そして演算増幅
器OP1の入力端子についてV3端子からの入力が
スイツチドキヤパシタを介しての経路が存在し、
この経路による動作は第1図の場合と同じで、ま
たV1端子からの入力の場合は第3図の動作を行
なうので、適宜切替え使用できる。また同時に使
用できる。
V 2 /V 10 α 21 α 2 + (α 4 −α 1 α 6 )S+S 2
…(9) B High-pass filter α 5 = α 2 α 3 + α 0 α 6 α 0 = 0 V 2 /V 1 = α 3 α 6 S 21 α 2 + (α 4 −α 1 α 6 )S+S 2
...(10) C Band pass filter α 0 = 0, α 3 = 0 V 2 /V 1 = α 5 S/α 1 α 2 + (α 4 −α 1 α 6 )S+S 2 ……(
11) Next, FIG. 5 is a circuit diagram showing a second embodiment of the present invention in which two output signals having the same phase and opposite phase with respect to the input signal are obtained. The output of V 2 is in phase with respect to the input from the V 1 terminal, and the output of V 2 is in reverse phase with respect to the input from the V 3 terminal. As for the input terminal of the operational amplifier OP 1 , there is a path for the input from the V 3 terminal to pass through the switched capacitor.
The operation using this path is the same as that shown in FIG. 1, and when the input is from the V1 terminal, the operation shown in FIG. 3 is performed, so it can be used by switching as appropriate. They can also be used at the same time.

このようにして本発明によるとバイカツド回路
を使用するフイルタにおいて入力信号に対し出力
信号が同相となる構成が容易に得られるので小
型・簡易である。
In this way, according to the present invention, in a filter using a biquad circuit, a configuration in which the output signal is in phase with the input signal can be easily obtained, so that the filter is small and simple.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフイルタの回路構成図、第2図
は第1図の等価回路図、第3図は本発明の第1実
施例の回路構成図、第4図は第3図の等価回路
図、第5図は本発明の第2実施例の回路構成図で
ある。 OP1,OP2……演算増幅器、C1,C2……コンデ
ンサ、K0C,K1C,K2C,K4C,K5C……スイツ
チドキヤパシタ。
Fig. 1 is a circuit diagram of a conventional filter, Fig. 2 is an equivalent circuit diagram of Fig. 1, Fig. 3 is a circuit diagram of the first embodiment of the present invention, and Fig. 4 is an equivalent circuit diagram of Fig. 3. 5 are circuit configuration diagrams of a second embodiment of the present invention. OP 1 , OP 2 ... operational amplifier, C 1 , C 2 ... capacitor, K 0 C, K 1 C, K 2 C, K 4 C, K 5 C ... switched capacitor.

Claims (1)

【特許請求の範囲】 1 複数のスイツチドキヤパシタと積分器2段で
構成したバイカツド回路を使用するフイルタにお
いて、第1段積分器に対しスイツチドキヤパシタ
と並列接続して入力信号を直接結合させるコンデ
ンサを具備し、第2段積分器の入力には前記第1
段積分器出力をスイツチドキヤパシタを介して入
力させる接続回路と、該接続回路と並列接続され
たコンデンサと、第1段積分器入力を他のスイツ
チドキヤパシタを経由して第2段積分器に入力さ
せる接続回路とを具備することを特徴とするバイ
カツド回路を使用するフイルタ。 2 第1段積分器入力には他のスイツチドキヤパ
シタのみを経由し、第2段積分器入力にはスイツ
チドキヤパシタとキヤパシタの並列接続回路を経
由する入力端子を更に設けたことを特徴とする特
許請求の範囲第1項記載のバイカツド回路を使用
するフイルタ。
[Claims] 1. In a filter using a biquad circuit composed of a plurality of switched capacitors and two stages of integrators, the input signal is directly coupled to the first stage integrator by connecting the switched capacitor in parallel. The input of the second stage integrator is provided with a capacitor to
A connection circuit that inputs the stage integrator output via a switched capacitor, a capacitor connected in parallel with the connection circuit, and a second stage integration that inputs the first stage integrator input via another switched capacitor. A filter using a biquad circuit, characterized by comprising a connection circuit for inputting an input to a filter. 2 The first stage integrator input is connected only through another switched capacitor, and the second stage integrator input is further provided with an input terminal that goes through a parallel connection circuit of a switched capacitor and a capacitor. A filter using a biquad circuit according to claim 1.
JP11093280A 1980-08-11 1980-08-11 Filter using bi quad circuit Granted JPS5735410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11093280A JPS5735410A (en) 1980-08-11 1980-08-11 Filter using bi quad circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11093280A JPS5735410A (en) 1980-08-11 1980-08-11 Filter using bi quad circuit

Publications (2)

Publication Number Publication Date
JPS5735410A JPS5735410A (en) 1982-02-26
JPS632170B2 true JPS632170B2 (en) 1988-01-18

Family

ID=14548250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11093280A Granted JPS5735410A (en) 1980-08-11 1980-08-11 Filter using bi quad circuit

Country Status (1)

Country Link
JP (1) JPS5735410A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07109972B2 (en) * 1986-12-29 1995-11-22 ソニー株式会社 Filter circuit

Also Published As

Publication number Publication date
JPS5735410A (en) 1982-02-26

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