JPS63216159A - Bus priority control system - Google Patents

Abstract

PURPOSE:To improve the processing speed of the entire system by placing the bus priority of the device to the lowest priority when plural device requests are in contention and one device occupies the bus for a prescribed time. CONSTITUTION:The titled system is provided with a discrimination circuit 21, an encoder 22, an OR gate 23, an AND gate 24, a register (A) 25, a register (B) 26, a code comparator 27 and a priority control circuit 28. Then the bus occupancy state of each device is monitored by a priority rotating clock and if plural device requests are in contention, a priority control circuit 28 brings the bus priority of the device occupying the bus for a prescribed time or over to the lowest order in response to the bus occupancy state of each device. Thus, the processing speed of the entire system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a bus priority control method for a processor control device, etc., and in particular to a bus priority control method that can improve the processing speed of the entire system. Priority control either fixes the priority or rotates the priority, so a device with a higher priority occupies the bus for a long time, preventing other devices from using the bus and reducing the overall system efficiency. There was a problem in that it was difficult to improve processing performance.

For example, as shown in FIG. 3, in the method of rotating the bus priority in units of the cycle of the priority rotation clock, each device a-c
The priority order is changed regardless of the bus occupancy time, which increases the waste of bus replacement. Incidentally, if the period is lengthened, the fixed order method % expression % An object of the present invention is to improve such problems and prevent one mask device from occupying the bus when multiple device requests conflict. An object of the present invention is to provide a bus priority control method that can improve the processing speed of the entire system.

Configuration To achieve the above object, the bus priority control method of the present invention responds to multiple device requests according to the bus priority, and in a bus priority control system in which one device occupies the bus, the bus priority control system of the present invention The bus occupancy status is monitored by a priority rotation clock, and when multiple device requests conflict, the priority control circuit sets the bus priority of the device that has occupied the bus for a certain period of time or longer according to the bus occupancy status of each device. It is characterized by its lower rank.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a functional configuration diagram of a bus priority control device according to an embodiment of the present invention, and FIG. 1 is a timing chart of the bus priority control device according to an embodiment of the present invention.

The bus priority control device of this embodiment is as shown in FIG.
Discrimination circuit 21, encoder 22, OR gate 23, AN
D gate 24, register (A) 25, register (B) 2
6, a code comparator 27 and a priority control circuit 28, and monitors the bus occupancy state of each device using a priority rotation clock with one period T.

Furthermore, the state of device A-C permission for each device A-C request is converted from a 4-bit code to a 2-bit code via the encoder 22.

This 2-bit code consists of register (A) 25 sampled by the rank rotation clock and register (A) 25, which is sampled by the rank rotation clock.
B) 26, and the timing of priority rotation is created based on the match.

That is, a signal RD indicating the current device permission state, a signal AC1 indicating the device permission state in the previous cycle, and a signal BC indicating the device permission state in the two previous cycles.
The bus occupancy status is recognized and the priority order is determined.

Further, when the priority order is rotated due to a match output, the code of the permitted device is forcibly entered into the register (B) 26 in preparation for the next match operation.

In addition, the method for changing the bus priority order is executed as follows.

(i) A device that has occupied the bus for a period greater than or equal to period T and up to 2T is given the lowest priority in synchronization with the ranking rotation clock.

(ii) Change the ranking of only that occupied device, and do not change the ranking of other devices.

Change the bus priority using the above method.

However, if the number of device requests is one or less, the function is masked with a signal indicating one device request.

Furthermore, if there is no permitted device, the code value is φ, so there is no chance of a match between φ and φ.

For example, as shown in FIG. 1, the bus occupancy status of each device is monitored by a ranking rotation clock with period T, and at the timing of ■, the bus priority of device C is first,
Device C permission is output.

At timing ■, device C continues to occupy the bus, and its occupation time is longer than cycle T. Therefore, at timing ■, the bus priority order is rotated, and device C becomes the lowest priority, and device B becomes the highest priority. becomes.

Furthermore, the device B permission is outputted according to the bus priority changed at the timing (3). Also, the register (B
) 26, the device B permission code is forcibly input.

In this case, since the bus occupation time of device B is shorter than the period T, the bus priority order is not changed.

At timing (2), device B continues to be in first place, but since there is no request for device B, device permissions are output to device C and device A in that order in accordance with other device requests.

This device A also occupies the bus at the timing ■, and the bus occupation time becomes longer than the period T, and at the timing ■, the ranking is rotated and becomes the lowest.

Note that the bus priority of device B is not changed.

In this way, even if the device C request, which has the highest bus priority, continues to request the bus for a long time, the device B request, which has a lower priority, can use the bus in parallel.

Note that the timing of actual bus exchange is determined by a clock having a higher frequency than this rank rotation clock.

Effects According to the present invention, a bus is connected to a plurality of devices for a long time.
Even if there are devices occupying the bus, the priority of the devices can be changed to periodically free up the bus, which can improve the processing speed of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a timing chart of a bus priority control device in an embodiment of the present invention, FIG. 2 is a functional configuration diagram of a bus priority control device in an embodiment of the present invention, and FIG. 3 is a conventional bus priority control device. 5 is a timing chart showing a control method. 21: Discrimination circuit, 22: Encoder, 23: OR gate, 24: AND gate, 25: Register (A), 26:
Register (B), 27: Code comparator. 28: Priority control circuit, ■~■: Timing of priority rotation, RD: Signal indicating current device status, AC:
Signal indicating the device permission state of the previous cycle, BC: 2
A signal indicating the device permission state for the previous cycle. Patent applicant Rico Co., Ltd. -7・、゛

Claims (1)

[Claims] (1) In a bus priority control system in which one device occupies the bus according to the bus priority in response to multiple device requests, a means for monitoring the bus occupancy state of each device, and a bus occupancy state of each device. and means for changing the bus priority according to the above, so that when multiple device requests compete and one device occupies the bus for a certain period of time, the bus priority of the device is set to the lowest. Characteristic bus priority control method.