JPS63215278A - Sequence converting circuit for video signal - Google Patents

Abstract

PURPOSE:To decrease the memory capacity required for a shuffling circuit by arranging the shuffling circuit on the pre-stage of a block forming circuit for a 3-dimensional block. CONSTITUTION:The sequence of the 3-dimensional block is converted into the sequence different from that of television scanning and converted into data of sequential 3-dimensional blocks. The shuffling circuit 2 has field memories 7A, 7B and at least either a write address or a readout address is controlled for shuffling in writing data to the field memories 7A, 7B or in reading the data from the field memories 7A, 7B. Since the two field memories are used in this way, the memory capacity is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal order conversion circuit for converting a digital video signal in a television scanning order to an order different from the television scanning order.

[Summary of the invention]

In the present invention, in a video signal order conversion circuit for converting an input digital video signal in a television scanning order to an order different from the television scanning order, the data order is made different from the scanning order (i.e., shuffling is performed). For this purpose, a shuffling circuit consisting of a memory bank of two field memories is provided before the blocking circuit, and a video signal order conversion circuit can be realized with a small memory capacity.

[Conventional technology]

In conventional digital VTRs, in order to prevent burst errors that occur during the recording/playback process from concentrating on a specific head within one screen, the order of recorded digital video signals is set in the television scanning order. A shuffling method is adopted that differs from the above.

In addition, in order to compress the amount of data transmitted when recording/playing digital video signals on a VTR, high-efficiency encoding methods have been proposed that reduce the number of bits per sample from the original, for example, 8 bits. . As one of the encoding methods, the applicant has proposed A D RC (Adapt
ive Dynamic Range Co-din
g) is proposed.

For example, as described in Japanese Patent Application No. 59-266407, the level difference (dynamic range) between the maximum and minimum values of multiple pixels included in a two-dimensional block is determined, and a code adapted to this dynamic range is used. transformation is done. Furthermore, as described in Japanese Patent Application No. 60-232789, there is also an apparatus for encoding a three-dimensional block formed from pixels of a two-dimensional head area included in each of a plurality of frames in a manner adapted to the dynamic range. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

Since the above-mentioned ADRC can significantly compress the amount of data to be transmitted, it is suitable for application to digital VTRs whose data transmission rate is not sufficiently high. ADRC, which performs encoding on a three-dimensional block basis, requires a blocking circuit that converts the order of input digital video signals into the order of three-dimensional blocks.

This blocking circuit requires memory to change the order of pixel data of multiple frames.

As a configuration in which both a three-dimensional blocking circuit and the above-mentioned shuffling circuit are provided, the configurations shown in FIGS. 27 and 28 can be considered. In FIG. 27, a digital video signal in television scanning order is supplied to an input terminal 21, and is converted into a three-dimensional block order in a blocking circuit 22. This blocking circuit 2
Shuffling circuit 23 where the output signal of No. 2 is shown surrounded by a broken line
supplied to

As an example, when a three-dimensional block spans two frames, the shuffling circuit 23 is provided with two two-frame memories 24A and 24B, and the two-frame memories 24A and 24B are connected to each other via a switch circuit 25. The entered input data is written. Furthermore, data read from the two-frame memories 24A and 24B is taken out to the output terminal 27 via the switch circuit 26. The switch circuit 25 and the switch circuit 26 perform switch operations in opposite phases to each other. For example, the switch circuit 25 is connected to the input terminal a, and data for two frames is written to the two frame memory 24A. When the switch circuit 26 is connected to the output terminal 24, the switch circuit 26 is connected to the output terminal
Data is read from B. 2 frame memory 24A
, 24B, the input data is written in the order of input,
Shuffled output data is obtained from the 2-frame memories 24A and 24B by controlling the read address.

In the configuration shown in FIG. 27, in addition to the memory required in the blocking circuit 22, the shuffling circuit 23 has two
There is a problem that frame memories 24A and 24B are required, resulting in an extremely large memory capacity.

FIG. 28 shows a blocking circuit and a shuffling circuit,
It has a configuration that also serves as a 2-frame memory.

That is, the input data from the input terminal 21 is input to the switch circuit 2.
The shuffled data is written to the 2-frame memories 24A, 24B via the switch circuit 26 and read from the 2-frame memories 24A, 24B via the switch circuit 26. When the switch circuit 25 is connected to the input terminal a side, data for two frames is written into one frame memory 24A, and data for one frame is written into the other frame memory 24A.
Previously written data is read from B via the switch circuit 26. By controlling this read address, both blocking and shuffling are performed.

[Problem that the invention seeks to solve]

Even in the case of the configuration shown in FIG. 28, there is a problem in that a minimum of two frame memories are required.

Therefore, an object of the present invention is to provide a video signal order conversion circuit that can reduce memory capacity when performing both shirtring and blocking.

[Means for solving problems]

In this invention, an input digital video signal having a scanning order is written alternately field by field, and the digital video signal is read field by field in reverse phase to the writing, and at least one of the write address and the read address is The first and second field memories 7A and 7B are controlled to obtain an output digital video signal in which the data order is different from the scanning order in units of two-dimensional areas formed by dividing one field. and,
The read data from the first and second field memories 7A and 7B is supplied, and block processing is performed to obtain sequential output data for each three-dimensional block consisting of two-dimensional areas each belonging to four fields that are continuous in time, for example. A circuit 3 is provided.

[Effect]

Since a shuffling circuit is provided before the blocks are formed, the order of digital video signals input in field units can be changed using the field memories 7A and 7B.
This can be done on a field-by-field basis. 4 where the 3D block belongs to each of 4 fields (2 frames)
When the field is formed from two-dimensional areas, shuffling is performed in units of these two-dimensional areas for each field.

Since it is sufficient to use two field memories for shuffling, it is possible to reduce the memory capacity.

〔Example〕

This invention will be explained below. This description will follow the order of the items below.

a, recording side and shuffling circuit A, reproducing side and deshuffling circuit C, block and blocking circuit d, 2-frame memory address control e, 9-line memory address control a, recording side and shuffling circuit 1 The figure shows the overall configuration of the recording side. In FIG. 1, a digital video signal having a sampling frequency of 13.5 (MHz), for example, is supplied to an input terminal indicated by 1. This input digital video signal is supplied to a shuffling circuit 2 shown surrounded by a broken line. The shuffling circuit 2 converts the order of video data into a lai order that is different from the television scanning order. The output signal of the shuffling circuit 2 is supplied to the blocking circuit 3, where it is converted into three-dimensional block order data.

The output data of the blocking circuit 3 is sent to the ADRC encoder 4.
The ADRC encoder 4 supplies output data whose data amount has been compressed.

In the ADRC encoder 4, the minimum value M I for each block
N, maximum value MAX, Guinamiso clean range DR (-MA
X-MIN) is detected, the number of bits corresponding to the dynamic range DR is set, the dynamic range DR is divided into the number of level ranges determined by this number of bits, and the level range to which the pixel data after minimum value removal belongs is divided. A corresponding code signal DT is formed.

Two additional data of the dynamic range DR, the maximum value MAX, and the minimum value MIN, such as the dynamic range DR, the minimum value MIN, and the code signal DT are supplied to the framing circuit 5.

In the framing circuit 5, the above data from the ADRC encoder 4 is converted into recording data having a frame structure. The framing circuit 5 encodes an error correction code as necessary.

Recorded data is taken out to an output terminal 6 of the framing circuit 5 and recorded on a magnetic tape by a rotating head (not shown).

If encoding is performed in units of three-dimensional blocks, AD
Not limited to RC, other encoding methods may be applied.

Is shuffling circuit 2 a field memory? A.

7B, and input digital video signals are written to these field memories 7A and 7B via a switch circuit 8 field by field.

Further, data for one field read out alternately from the field memories 7A and 7B is supplied to the blocking circuit 3 via the switch circuit 9. The switch circuit 8 and the switch circuit 9 are switched for each field and operate in opposite phases.

For example, in a field where one switch circuit 8 is connected to the terminal a side, the other switch circuit 9 is connected to the terminal a side.

When writing data to or reading data from the field memories 7A, 7B, at least one of the write address or the read address is controlled for shuffling.

-As an example, for field memories 7A and 7B-
The input digital video signals are written in input order (i.e. television scanning order) and are stored in field memory 7.
A.

Digital video signals are read out from 7B in a different order from the input.

Figure 3 conceptually shows shuffling.
Input digital video signals are written into one field memory in input order, and the contents of this one field memory are read out during the next field period. Shuffling is performed in units of two-dimensional regions numbered in FIG.

A three-dimensional block is formed by a set of four two-dimensional regions at corresponding positions in four consecutive fields (two frames). When reading from the field memory, spatially adjacent two-dimensional areas in the input field (9 two-dimensional areas are shown as an example in FIG. 3) are read so that they are spatially separated. The six output addresses are controlled and a shuffled output field is obtained. This shuffling disperses burst errors that occur during the recording/reproducing process of the VTR, making the errors less noticeable in the reproduced image.

b. Reproducing side and deshuffling circuit FIG. 2 shows the overall configuration of the reproducing side. In FIG. 2, an input terminal indicated by 11 is supplied with a digital reproduction signal reproduced by a VTR.

This digital reproduction signal is supplied to the frame decomposition circuit 12, and the dynamic range DR, ! l small value MIN and code signal DT are separated. The output signal of the frame decomposition circuit 12 is supplied to the ADRC decoder 13, and the original pixel data is restored. ADRC decoder 13
Since the output signal is in block order, it is supplied to the block decomposition circuit 14. The output signal of the block decomposition circuit 14 is supplied to a deshuffling circuit 15 shown surrounded by a broken line. The deshuffling circuit 15 reverses the order of data to the original order, that is, the shuffling circuit 2 on the recording side.
This is to restore the television scanning order, and its output terminal 1
6, a reproduced digital video signal is obtained.

Similar to the shuffling circuit 2, the deshuffling circuit 15 includes two field memories 17A.

17B and switch circuits 18 and 19. , the switch circuits 18 and 19 are connected to the field memory 17
The terminal A is connected to the field 17B, and the terminal A is connected to the field 17B. In one field, these switch circuits 18, 19 are connected to the terminal a side,
In the 0th order field where the field memory 17A performs a write operation and the field memory 17B performs a read operation, the connection state of the switch circuits 18 and 19 changes,
Now you can select the terminal. Therefore, the field memory 17A is in the read state, and the field memory 17A is in the read state.
B is in a writing state. By controlling one of the read and write addresses, the state is returned to a non-shuffling state.

C. Blocks and blocking circuits FIG. 4 shows three-dimensional blocks in this embodiment. In FIG. 4, fl, f2° f3 . f4 is
Each of the two-dimensional regions of four temporally continuous fields is shown. The size of one two-dimensional area is (2×4 pixels). Therefore, one block includes 32 pixel data.

The blocking circuit 3 converts the shuffled pixel data for each field into [line Lll of field f1→line L12 of field f1 - line L of field f2].
21 → line L22 of field f2 → field f3
Line L31 → Line L32 of field r3 → Line L41 of field f4 → Line L of field f4
42) '(The order of the four pixel data in each line is
scan order).

FIG. 5A shows the basic configuration of an example of the blocking circuit 3, and FIG. 5B shows the basic configuration of the block decomposition circuit 14. Input data from an input terminal indicated by 41 in FIG. 5A is supplied to a 2-frame memory 42, and processed into blocks in the time axis direction. That is, the order of input data of two temporally consecutive frames (four fields) constituting one block is converted. 4 fields r1. r2゜r3. The first line of each of r4 is Lll, L2
1, L31. If it is L41, the 2-frame memory 42 allows [L11→L21→L31-4L41]
The data order is changed to the order of . The data order of the second line is also changed in a similar order.

The output data of the 2-frame memory 42 is transferred to the 9-line memory 4.
3 (has a capacity for 9 lines). This 9-line memory 43 performs blocking in the horizontal and vertical directions. In the case of the block shown in FIG. 4, Lll,
L12 L21 L22...L41.
All data included in the line L42 is written to the 9-line memory 43. Then, from the 9-line memory 43 to the output terminal 44, output data is obtained in the order in which the data is divided into four pixel data units (that is, in the order of the blocks). 9
As mentioned later, we have the capacity for 1 line.
This is to deal with cases where the number of pixels in a line is not divisible by 8.

In FIG. 5B, block order input data is supplied to an input terminal 45 and supplied to a 9-line memory 46. In FIG. The 9-line memory 46 performs block decomposition in the horizontal and vertical directions, and the output data of the 9-line memory 46 is supplied to the 2-frame memory 47. This 2-frame memory 47 performs block decomposition in the time axis direction, and output data in the same order as television scanning is obtained at the output terminal 48.

The 2-frame memory and the 9-line memory can also be used for the blocking circuit 2 and the block decomposition circuit 15. FIG. 6 shows an example of a blocking/block decomposition circuit. In FIG. 6, 51 indicates a 2-frame memory, and 52 indicates a 9-line memory.

A switch circuit S1 and a switch circuit S2 are connected to the data input/data output side of the 2-frame memory 51, respectively, and a switch circuit S3 and a switch circuit S4 are connected to the data input/data output side of the 9-line memory 52, respectively. be done. Switch circuits S5 and S6 are connected to the data input terminal 53 and the data output terminal 54, respectively. Switch circuits S7 and S8 are respectively connected to the address signal supply path of the 2-frame memory 51, and the 9-line memory 52
Similarly, switch circuits S9 and SIO are respectively connected to the address signal supply path. The output signal of the switch circuit S7 is supplied to the 2-frame memory 51 as a write address, and the output signal of the switch circuit S8 is supplied to the 2-frame memory 51 as a read address. Further, the output signal of the switch circuit S9 is supplied to the 9-line memory 52 as a write address, and the output signal of the switch circuit S10 is supplied to the 9-line memory 52 as a read address.

Address signals for the 2-frame memory 51 are generated by frame memory control circuits 55 and 56, and address signals for the 9-line memory 52 are generated by line memory control circuits 57 and 58. Timing signals are received and passed between frame memory control circuits 55 and 56, and timing signals are similarly received and passed between line memory control circuits 57 and 58.

Switch circuit 5 INS10 and frame memory control circuit 5
A mode switching signal is supplied from a terminal to the line memory control circuit 57 and the line memory control circuit 57, and switching between blocking operation and block decomposition operation is performed. When functioning as the blocking circuit 3, the switching circuits 81 to S10 are connected to the terminal a side, as shown in FIG. 6, and when functioning as the blocking circuit 14, the switching circuits 51 to S10
lO is connected to the terminal side.

When the switch circuit 5t-310 is connected to the terminal a side, input data from the input terminal 53 is connected to the switch circuit S5.
and 31 to the two-frame memory 51,
Data read from the 2-frame memory 51 is written to the 9-line memory 52 via switch circuits S2 and S3. Data read from the 9-line memory 52 is taken out to the output terminal 54 via switch circuits S4 and S6. During this blocking operation, the address signal formed by the frame memory control circuit 55 is supplied to the 2-frame memory 51 as a write address, and the address signal formed by the frame memory control circuit 55 is supplied to the 2-frame memory 51 as a read address. supplied to Similarly, the address formed by the line memory control circuit 57 is supplied to the 9-line memory 52 as a write address, and the address formed by the line memory control circuit 58 is supplied to the 9-line memory 52 as a read address.

During the block decomposition operation when the switch circuits S1 to 5xoj are connected to the terminal side, the input data from the input terminal 53 is sent to the 9-line memory 5 via the switch circuits S5 and S3.
2 and read from the 9-line memory 52 are written to the 2-frame memory 51 via the switch circuits S4 and Sl, and data read from the 2-frame memory 51 is transferred via the switch circuits S2 and S6. and is taken out to the output terminal 54. During this block decomposition operation, the frame memory control circuit 55 and line memory control circuit 57 form a read address, and the frame memory control circuit 56 and line memory control circuit 58 form a write address. That is, in the blocking operation and the block decomposition operation, the address signals for the 2-frame memory 51 and the 9-line memory 52 have an opposite relationship between the write address and the read address.

d, Address of 2-frame memory t[al Address control of the 2-frame memory 51 when blocking is performed will be described below. This address control is [Write 1 →
Read 1 - Write 2 -> Read 2] is performed periodically so as to be completed in four frames. Figure 7, Figure 8,
Figure 9.

For simplicity, FIG. 10 shows address control when it is assumed that the l field is composed of 12 lines. The addresses of the two frame memories are Ax and Ay.

Given by ^2. Ax is horizontal direction (pixel unit)
, Ay indicates an address in the vertical direction (in units of lines), and AX indicates an address in the time direction (in units of fields).

The shuffled input digital video signal is first written into the 2-frame memory under write 1 address control. When address control is performed in write 1 mode, two frames are written to the memory in the order of input, as shown in FIG. 7A, FIG. 7B, and FIG. 7C. That is, address AX (Fig. 7C) is increased stepwise for each field of input data, and address A
y (FIG. 7B) is increased stepwise from 0 to 1.2 for each line within one field.

Data written in write 1 is read from the Z frame memory under address control in read 1. 8th
As shown in FIGS. A, 8B, and 8C, in read 1, four lines corresponding to four fields are sequentially read out. That is, address Ay (Fig. 8B) is (O~11)
Address Az (FIG. 8C) is changed to 0.1.2.3 while it is fixed at a predetermined line in . The write 1 and read 1 operations described above create blocks in the time axis direction using two frame memories.

The next four fields of input data after the input data written in write 1 are written to the 2-frame memory in write 2. Figure 9A, Figure 9B.

As shown in FIG. 9C, in write 2, one field is divided into four, and after writing the data for field A, the data for field A of the next field is written, so that each field is written one by one. Ru. That is, 1
If the field has 12 lines, 1 field has 3 lines.
It is divided line by line, and the address Ay (FIG. 9B) repeats changes for three lines while the address Az (FIG. 9C) is between predetermined values.

The data written in write 2 is read out under address control in read 2. As shown in Figures 10A, 10B, and 10C, in read 2, the first line of each A field of the same field is read out first, and then the second line of each is read out. Read out.

When this read operation is completed for that one field, a similar read operation is performed for the next field. That is, during one field' period when the address AX (FIG. 10C) is set to a predetermined value, the address static (first
0 figure B) is (0, 3, 6, 9) (1, 4° 7.10
)(2,5,8,11).

The next data written in write 2 is again written to the 2 frame memory under the address control of write 1. By the address control of 0 or more, the data read from the 2 frame memory is The first lines of data of the fields are output in order, then the second lines of the four fields are output in order, and in the same way, the corresponding lines of the four fields are output in order.

FIG. 11 is a diagram showing the phase relationship between a write operation and a read operation in a 2-frame memory when the l field is composed of 12 lines.

In FIG. 11, the vertical line indicates the length corresponding to the period during which the data of the 1 line occupies the corresponding address of the 2-frame memory.

That is, data written at the timing of one end on the upper side of this vertical line is read out at the timing of the other end on the lower side. The field order of the input data is (fol
-f02-f03 →f04 →fil -f12...
...f23→r24], the input data of the first four fields is changed by the write 1 address control.
The data is sequentially written to the 2-frame memory, and then this data is sequentially read from the 2-frame memory under address control of read 1. From the middle of this lead 1 period,
The input data of the next field f11 is written into the 2-frame memory under address control of write 2. From the middle of the write 2 period, the written data is read out under the read 2 address control. From the middle of the read 2 period, manual data in the next field f21 is written under write 1 address control. This first
As shown in FIG. 1, the vertical lines do not overlap, so that the input data is written to the memory with excess or deficiency (2 frames) and read out without any loss.

-m-wise, the first written data in write 1 is read by 1, the number of lines in 1 field is N.
If f is the timing of the line (3Nf-3).

The above is the address control of the 2-frame memory during the blocking operation. Address control during block decomposition involves swapping the write address and read address.

A specific example of an address counter for performing address control performed during the above-mentioned blocking is shown in FIG.
In Figure 2, CTx indicates a counter for generating address Ax, CTy-1°CTy-2 indicates a counter for generating address Ay, and CTz indicates a counter for generating address AX. The counter CTx shown has a count range of (0 to Nh-1), where the number of pixels included in l line is Nh, and the weight of one count is 1. Counter CTy-1 has address AV
When the maximum value of is Nv (=4xm, where m is a natural number), it has a count range of (0 to V4NV-1) and 1
The count weight is 1. The counter CTV-2 is (
It has a count range of 0 to 3), and the weight of 1 count is %.
It is NV. The counter CTz has a count range of (θ to 3), and one count has a weight of 1 (one field).

4 counters CTx, CTy-1, CTy-2, CT
z is configured to transmit the carry output of the lower counter to the upper counter. In FIG. 12A, a carry output is transmitted in order from a lower counter to an upper counter, and an address signal in the case of write 1 is formed.

As shown in FIG. 12B, the carry output of counter CTx is transmitted to counter CTz, the carry output of counter CTz is transmitted to counter CTy-1, and counter C
The address for lead 1 is formed by the structure in which the carry output of Ty-1 is transmitted to counter CTV-2.

As shown in FIG. 12C, the carry output of the counter CTx is transmitted to the counter CTy-1, and the carry output of the counter CTx is transmitted to the counter CTy-1.
The address for write 2 is formed by a structure in which a carry output of 1 is transmitted to the counter CTz, and a carry output of the counter CTz is transmitted to the counter CTV-2.

As shown in Figure 12, the counter CTxΦ carry output is transmitted to the counter CTy-2, and the counter C'ry
The address for lead 2 is formed by the configuration in which the carry output of -2 is transmitted to counter CTy-1 and the carry output of counter CTy-1 is transmitted to counter CTz.

As is clear from FIG. 12, the address counter requires systems corresponding to four types of address control. However, write 1 and write 2 do not overlap in time, only one counter configuration is required for address control during write operation, and switching between write 1 and write 2 is as follows:
The connection relationship between the counters may be switched using a gate circuit. Similarly, only one counter configuration is required for address control during a read operation, and the configuration of read 1 and 2 can be changed by switching the connection relationship between the counters.

e. Address control of 9-line memory By blocking using the 2-frame memory described above, 2 lines x 4-8 lines (2 lines x 4-8 lines) are not necessary to construct a 3-dimensional block in 4 temporally consecutive fields. The 0th order, where the data is divided into blocks in the time direction, and the 9
Each line is divided into four pixel data by the line memory, and the four pixels belonging to each of the eight lines are grouped into blocks in the horizontal and vertical directions.

Blocking using this 9-line memory will be explained below. For ease of understanding, one field consists of 8 lines, and the number of pixels in each line is divisible by 8 (8
The address control of the 9-line memory (n) is performed in the cycle of [Write 1-Read 1-Write 2→Read 2].

As shown in FIG. 13A, the first 8 lines of input data are written to the 9-line memory in the order in which they are input (
Light 1). The 9th line of the 9-line memory contains
The input data of the 0th order 8 lines on which no data is written is written into 8 lines for each n pixel formed by dividing each line into 8, as shown in FIG. 14A (Write 2) .

The data written under the write 1 address control is read out for each pixel at the same position in the vertical direction (read 1), as shown in FIG. 13B. These four consecutive columns of data (32 pixel data in total) constitute one three-dimensional block. Further, the data written by the write 2 address control is read out at every four pixels in the horizontal direction of each line (read 2), as shown in FIG. 14B. When one line is read out, the next line is read out in the same way. The data read out under the address control of read 2, like the data read out under the address control of read 1, consists of 32 temporally continuous pixel data forming one three-dimensional block.

Address control of the above-mentioned 9-line memory will be explained using an example in which the number of pixels Nh in one line is 32 (n=4). When controlling the address of write 1, as shown in FIGS. 15A and 15B, the address AV is (o, 1.2
．． ...7), and within the period of the address quiet predetermined value, the address Ax becomes (0, l, 2. ...31
．． 32 (-0)).

When controlling the address of lead 1, see Figure 16A and Figure 16.
As shown in Figure B, during the period when address Ax is a predetermined value, address Ay increases as (0, 1, 2...7°8 (=0)), and pixels at the same position are removed from each line. Read out sequentially.

When controlling the write 2 address, FIGS. 17A and 17
As shown in Figure B, the address Ax is (0°1.2.3)
The address Ay is incremented each time the address Ay changes.

When controlling the address of lead 2, FIGS. 18A and 18
[As shown in ff1B, address Ay is incremented every 32 pixel data period, and address Ax is incremented every 32 pixel data period.
Discrete values (0, 4, 8°...28) for each pixel (
1, 5, 9, ... 29) ... (3, 7, 11
,...31).

FIG. 19 is a diagram showing the phase relationship between a write operation and a read operation in a 9-line memory. Similar to FIG. 11 described above, in FIG. 19, the closed 1f, l area indicates a period during which one line of data occupies a predetermined address in the nine-line memory. That is, data written at the timing of one end on the upper side of this closed area is read out at the timing of the other end on the lower side. The first 8 lines of input data of the human input data are sequentially written into the 9-line memory under write 1 address control, and then this data is sequentially read from the 9-line memory under read 1 address control. From the middle of this read 1 period, the next 8 lines of input data are written into the 9 line memory under write 2 address control. From the middle of the write 2 period, the written data is read out under the read 2 address control. From the middle of the read 2 period, the next 8 lines of manual data are written under write 1 address control. As shown in FIG. 19, the closed regions do not overlap each other, so the input data is 9
It is written into the line memory and read out without any loss.

Generally, the first 8 lines of input data written into the 9 line memory are read out at the data timing of (7Nh-7).

The above is the address control of the 9-line memory during the blocking operation. Address control during block decomposition involves swapping the write address and read address.

Further, address control when the number of pixels Nh in one line is not divisible by 8 will be described below.

As described above, address control is performed at the cycle of [Write 1-I)-Do 1-Write 2→Read 2].

As shown in FIG. 20A, in write 1 address control, input data is sequentially written from the first line in the order of input. The 9-line memory has horizontal addresses corresponding to the number of pixels Nh in one line. This number of pixels N
h is (8n+Δ). Data written under write 1 address control is read from the 9-line memory under read 1 address control. As shown in FIG. 20B, in lead 1, pixel data at the same position in the vertical direction is sequentially read out. These write 1 and read 1 address controls are performed based on the number of pixels in one line, Nh.
This is the same as when is divisible by 8.

When writing the next 8 lines of input data, each group consisting of n pixel data and mod, (Nh.

8), and these groups are written over nine lines as shown in FIG. 21A (Write 2). Data written under write 2 address control is read from the 9-line memory under read 2 address control.

As shown in FIG. 21B, in read 2, reading is performed intermittently in the horizontal direction for every four pixels.

The address control when the number of pixels of the era line Nh is not divisible by 8 will be explained assuming that (Nh=34). Second
FIG. 2 shows addresses Ax and AV when data is written by the write 1 operation.

Address Ay (Figure 22B) is (0, 1, 2,...
・7) is increased every 34 pixels, and within the period when address 71)1 is a predetermined value, address Ax (Fig. 22A) becomes (
0, 1, 2,...34).

The data written by the write 1 operation described above is
It is read by the read 1 operation.

FIG. 23 shows addresses ^X and Ay when data is read out by the operation of lead 1. Since lead 1 sequentially reads out pixel data at the same position in the vertical direction from each line, address Ax (23rd Figure A) is (0
, 1, 2, ... 34), and is increased every 8 pixels, and within the period of the predetermined value of the address Ax, the address Ay
(Figure 23B) is changed to (0°1.2...7).

FIG. 24 shows addresses Ax and Ay when data is written by the write 2 operation. Within the period in which input data of 34 pixels for one line is supplied, the address Ay
(Fig. 24B) every 4 pixels (0, 1° 2, ... 8)
It changes. Further, within this four-pixel period, the address Ax (FIG. 24A) is changed to (,0°1.2.3).

The data written in this write 2 is read out from the 9-line memory by the read 2 operation.

As shown in FIG. 25B, the address Ay changes to (0, 1, 2...8) for each line period.

During one line period when the address Ay is a predetermined value, the address Ax (Fig. 25A) changes every four times, and one line of data is read by changing the address 8X four times. .

FIG. 26 shows a specific example of an address counter for performing address control during the aforementioned blocking in the horizontal and vertical directions. In FIG. 26, CTX-1 and CTx-2 represent counters for generating address Ax, and CTy represents a counter for generating address Ay. The counter CTx-1 is (0 to int
Counter CTx-2 has a count range of (Nh/8)-1), and the weight of one count is one pixel (however, in the horizontal direction). The weight is int (Nh/8) (in the horizontal direction). The counter CTY has a count range of (0 to 8), and each count has a weight of 1 (in the vertical direction).

FIG. 26A shows a connection configuration of a counter and a gate circuit when performing write 1 address control.

FIG. 26B shows the connection configuration of the counter and gate circuit when controlling the address of lead 1. Figure 26C is
This is a connection configuration of a counter and a gate circuit when performing address control for write 2. Figure 26 shows the connection configuration of the counter and gate circuit when controlling the address of lead 2.

As is clear from FIG. 26, the address counter requires systems corresponding to four types of address control. However, similar to the control of a two-frame memory, write 1 and write 2 do not overlap in time, and only one counter configuration is required for address control during write operation. The switching is done by the gate circuit.
All you have to do is switch the connection relationship between the counters. Furthermore, only one counter configuration is required for address control during read operation, and lead 1 and lead 2 can be changed by switching the connection relationship between the counters.

〔Effect of the invention〕

According to this invention, the memory capacity required by the shuffling circuit can be reduced by arranging the shuffling circuit before the blocking circuit for three-dimensional blocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a recording side of a digital VTR using a shuffling circuit according to the present invention, and FIG. 2 is a block diagram showing a configuration of a digital VTR using a deshuffling circuit.
A block diagram showing the configuration of the playback side of the TR, FIG. 3 is a route map showing an outline of shuffling, FIG. 4 is a route map for explaining the three-dimensional block in this embodiment, and FIGS. 5 and 6 are The figure is a block diagram of a blocking circuit and a block decomposition circuit, and FIGS. 7, 8, 9, and 10 are route diagrams for explaining address control of a 2-frame memory provided in the blocking circuit. FIG. 11 is a route diagram for explaining the address control of the 2-frame memory, and FIG. 12 is a block diagram showing the configuration of the address counter of the 2-frame memory.
FIG. 13 and FIG. 14 are route maps for explaining writing and reading of data to and from a 9-line memory, and FIG. Figures 16, 17, 18 and 19 are route maps for explaining the address counter of the 9-line memory;
0 and 21 are route maps for explaining other examples of writing and reading data to and from a 9-line memory.
2, 23, 24, and 25 are route diagrams for explaining other examples of address control, and FIG. 26 is a block diagram showing the configuration of an address counter of a 9-line memory.
FIG. 7 and FIG. 28 are block diagrams showing the configurations of one example and another example of the shirt ring circuit, respectively. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2: Shuffling circuit, 3 niblock circuit, 14 niblock decomposition circuit, 15: Deshuffling circuit, 51: 2 frame memory, 52: 9 Line level, 53: Data input terminal, 5
4; data output terminal, 55.56: frame memory control circuit, 57.58 two-line memory control circuit. Agent Patent Attorney Tadashi Sugiura Tomo 2 Kotoiiiii! ! Ij -1] Figure 2 1,000mm 17'' Lock Figure 4 Feel 1' Fluffy) 7 Shirt 1 Luxury Muffler 14th Row Figure 27-Ax Az=OAz=1 Az =2 A
z=3 A x Az = OAz=I Az=2 A
z=3Figure 9 A x Az=OAz=I Az22
Az=3 A x Az=OAz=I Az=2 Az
=351 To 1 Fig. 13 A 1 Tsudopa 1 Fig. 13 B Fig. 12 A Fig. 12 B Lee 12 Fig. 12 D Leet'2 Fig. 14 B Phyto 1 Phyto 2 Fig. 18 ° J God 2 71 + Cis- A x Wright 1
Lead 2 Figure 26C Figure 26D

Claims (1)

[Claims] An input digital video signal having a scanning order is written alternately field by field, and the digital video signal is read field by field in reverse phase to the writing, and the write address and read address are the first and second fields for obtaining an output digital video signal in which the data order is different from the scanning order in units of two-dimensional areas formed by dividing one field by controlling at least one of the first and second fields; A block to which read data from the memory and the first and second field memories is supplied, and to obtain sequential output data for each three-dimensional block consisting of the two-dimensional areas each belonging to a plurality of temporally continuous fields. 1. A video signal order conversion circuit comprising: