JPS63215219A - Three states cmos bus structure level clamp - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of the Invention This invention relates to a bus line, more specifically, to a three-state CMOS
It involves a level clamp to clamp the bus line to the final state in which it was set.

(B) Background of the Invention A bus in a CIOS system is usually provided with a number of bus lines. A plurality of elements (devices) can be connected to each of these bus lines. Elements connected to the bus line can have their outputs in any one of three possible states. The first of these conditions occurs when the output of the device is in a low impedance path to the lower voltage rail (usually circuit ground), a condition commonly referred to as a logic "0" state.

The output of an element is said to be in the second state when the element presents a high impedance at its output and is absent as far as other elements connected to the same bus line are concerned. A third possible state is when the output of the water child is connected through a low impedance path to the higher voltage rail, a state commonly referred to as the logic rlJ state.

A CMOS bus line typically has a number of buffer drivers connected to it to drive it into one of two possible low impedance states. If a bus line is not driven by any of the drivers for a long period of time, the bus line will be in one particular tftli buried state due to leakage and inherent capacitance to ground and/or higher rails. begins to drift from one state to the other. If the bus line is not held at the drain or source supply voltage, i.e. Vdd or Vss, the bus line will be at (Vdd - Vs
'Jlt of 30% to 70% of s)
1. The signal may eventually drift into the so-called "forbidden band." It is in this voltage band that the P and N channel input transistors of the CMOS gate connected to the busbar are simultaneously made conductive as the busbar line floats between the two rails.

This will result in excessive current flow through those input transistors connected to the bus line and thus overheating of these input transistors. A common way to correct the aforementioned problems is to tie a pull-up or pull-down resistor to the busbar. However, if a liquid film resistor is used, the bus bar will slowly reach the "forbidden band".
The bus may not be fully driven at the rail voltage level, and too much power may be dissipated.

(/→ PROBLEMS SOLVED BY THE INVENTION This invention solves the aforementioned problems by using a combination of non-inverting gates and feedback resistors to clamp the busbar to the last state it was set in by the active driver. prevent the occurrence of

It is further envisioned that a 0M08 circuit with standard input and high impedance output can be used as a replacement for the non-inverting gate and feedback resistor combination.

It is therefore an object of the present invention to provide a discrete component for eliminating all the aforementioned undesirable effects of using connecting resistors.

It is a further object of the invention to provide an active bus line clamp that drains current only during rail-to-rail switching.

It is a still further object of the invention to provide a bus line clamp which secures the bus line in the state in which it was last set.

The foregoing objects and advantages of the invention will become more apparent, and the invention itself may be best understood, by reference to the following description of embodiments thereof, taken in conjunction with the accompanying drawings.

2) Embodiment The usual way to hold or connect a non-driven bus line to a Vdd rail or a VSS rail is to connect a pull-down resistor or a pull-up resistor from the bus line to one of the rails, respectively, as illustrated in FIG. That's true. This resistor must have a fairly high impedance, for example 100 kilohms.

However, there are several problems with this technique.

First, the transition of the bus line through the forbidden band is slow because a fairly high impedance resistor is used. (If the resistance value of the resistor were made too small, another problem would arise - namely, that the bus line would be driven by the driver.) Second, the resistor would be opposed to being clamped. When the bus line is held in the rail, there is a continuous drain of power through the resistance.

A third drawback of this conventional technique is that the bus line cannot be driven all the way to the opposite rail to which the resistor is connected. Furthermore, the value of resistance used in conventional methods must be a compromise between conflicting factors. For example, the amount of current that a driver can supply to a rail through a resistor must be balanced for the desired output voltage level. Also, if a resistor is connected to a battery-assisted system or to a system with insufficient heat dissipation capability, the amount of current that can be dissipated under steady state conditions must be carefully apportioned and controlled. Furthermore,
The time that the bus line is driven through one forbidden band must be kept to a minimum to prevent excessive current drain into the input stages of the P and N channel transistors of the CMOS gate. It is therefore readily apparent that the conventional technique of tying a rail pull-up or pull-down resistor from the bus line has significant drawbacks.

FIG. 2A shows the transition from one rail, e.g., Vdd, to a second rail, e.g., Vss, when the bus line is no longer driven by any of the drivers connected to it.
This shows a curve representing the transition of the bus line to. As shown, in order to transition from one rail to the other, the busbar track must have Vdd-Vss coordinates between 30-70 percent marked areas and T1 and T,
The so-called "forbidden zone" must be passed, which is indicated on the time coordinate between the zones indicated by .

FIG. 2B shows the transient current peak 2 during time T and T2.
This shows that this often occurs. 70 bus lines
If it takes a relatively long transition time between % and 30%, then the 0MO8 connected to the bus line
The P and N channels of the device will be turned on when open for a relatively long time. If the time between TI and 12 is relatively long, the 0MO8 device may be overheated by this high current peak.

An embodiment of the invention for clamping a bus line in its last activated state is illustrated in FIG. 3, in which bus line 12 is shown. Bus line 12 may be driven by any of a variety of devices with king-state outputs, such as drivers 4 and 6. As is well known, the bus line includes a number of CMOS devices, such as inverters 8 and 10, which are shown connected thereto. As mentioned earlier, if only the driver and the input element are connected to the bus line when the bus line is not driven by any of the drivers, then This will tend to drift and, by chance, it could enter the "forbidden band" causing overheating of inverters 8 and 10.

To eliminate this, the clamping element 15 of the invention, consisting of a non-inverting driver 14 and a feedback resistor 16, is connected to the bus line 12 at point 22.

As can be seen, both ends of resistor 16 are connected to the output and input of non-inverting driver 14, respectively.

It should be noted with respect to the above discussion that drivers 4 and 6 are buffer elements of a common type, e.g.
4503B CuO2 element. Inverter 8 and 1
0 can be configured with a CD4049 inverter of the general type. As far as the invention itself is concerned, the non-inverting driver 14 is of the general type CD4050 0MO8.
The resistor 16 may have a resistance value of approximately 20 kilohms. It should further be noted that the general element types and resistance values described are provided for illustrative purposes only and are not limiting.

The theory of operation of the clamp element of this invention is as follows. Considering the non-inverting driver 14, as is well known,
There is a time delay, however small, between the time a non-inverting driver starts operating and the time an output is delivered from the driver. For example, if bus line 12 is being driven low, the non-inverting driver 140 input shown as 20 will also be low. However, 1
The output of the non-inverting driver 14, indicated at 8, becomes low only after a certain amount of time has elapsed since it takes a certain amount of time for current to flow between the semiconductor junctions of this non-inverting driver. Will. Therefore, during that period of time, output 18 remains high even though input 20 goes low. Since resistor 16 is connected to the non-inverting driver 140 input and output, current flows through resistor 16 during this period of time until output 18 catches up with input 20.

With the above discussion in mind, the clamp of the present invention operates as follows. Assume that driver 4, which is assumed to be the only driver driving bus line 12, has finished driving bus line 12 low. Since the bus line 12 is not being driven by any other driver, it will try to move from the state it was set to to another state, which the CMO3 structure inherently has. This is because it is natural for the capacitance to drift due to leakage and capacitance. As soon as the bus line 12 begins to drift from one state to the next, the non-inverting ringer 14
A potential difference immediately occurs between the input 20 and the output 18 of the . As a result, a current flows through the resistor 16. resistance 1
Since the current flowing through resistor 16' can far exceed the leakage current inherent in CMOS systems, it is clear that the current flowing through resistor 16' will tend to keep motherboard 811 path 12 low. The current flowing through the resistor 16 is the bus line 1
2, there is a positive feedback between the amount that the bus line 12 is drifting and the current drained by the resistor 16.

Therefore, even if the bus line 12 were to float from its last set state, it would be prevented from achieving any meaningful displacement due to the current draining through the resistor 16.

Assume that bus line 12 is in a high state instead of being low. The same result will occur - ie the bus line will remain in substantially the last state in which it was set. For this case, the bus line 12 has a tendency to float low. Since there is a potential difference between input 20 and output 18, current will flow through resistor 16, thereby causing the potential at input 20 to be substantially indistinguishable from the potential at output 18. Therefore, the clamp of this invention becomes self-limiting very quickly.

The only criteria that must be considered when designing this clamp is to choose the value of resistor 16 appropriately and set this value to -maIv! be small enough to ensure that line 12 is held at the value of output 18 and also sufficiently small that the entire transition of the bus line is not substantially slowed down when it is being driven by some driver, e.g. This is something that has to be made higher. However, it should be noted that
Instead of using all 14 separate non-inverting drivers,
A non-inverting element already connected to the bus line 12 can also be used for the purpose of the invention, provided that both ends of a stagnation resistor with the previously mentioned values are attached to the input and output of this non-inverting element. can be used. For this alternative it is essential that the load driven by the chosen element does not dissipate enough to overcome the resistance when connected to it. In fact, the chosen element will not slow down the transition due to its inherent additional capacitance. 0M0 with standard input and high impedance output
It is also conceivable to use three circuits instead of the non-inverting element and resistor combination.

To further elucidate the invention, FIG. 4 provides a time-current diagram to illustrate the operation of the clamp. As shown, the time axis is divided into 24 to 50 different time periods. A period 24 indicates an initial state period. In period 26, the logical value “1” changes from the logical value “1” to the logical value “1”.
There is a significant change in the output of the buffer driver 4 to the 0'' state. (It is assumed in this case that a low state is being considered.) When driver 4 goes from "1" to "0", bus line 12 also goes low. Period 28 represents a short period of stability that may exist between the time when driver 4 reaches a logic "0" state and the time when non-inverting clamp 15 begins to match the output of driver 4. ing. Depending on the exact time of the propagation delay due to the non-inverting crimp and the speed of the transition of driver 4, period 28 may or may not be present.

That is, if the transition time of the driver 4 is relatively long compared to the propagation delay time of the non-inverting clamp 15, this period does not exist. In other words, the non-inverting clamp 15 may start responding before the driver 4 has even reached ground potential. Non-reversing clamp 15 during period 300
The output of changes. During period 32, driver 4 has reached a logic "0" state and continues to drive bus line 12 to ensure that stability exists in the system.

The buffer driver 4 stops driving in period 34 and the system is now held by the output of the non-inverting clamp 15 through the resistor 16'. During period 36, buffer driver 6 (by some computing device, not shown)
turned on. It is driven to a logical value '0', but the system is already ((placed in this state. Therefore,
The system is not affected by it.

During period 38 the driver 6 is turned off. During this period, due to the clamping of the bus line 12 by the non-reversing clamp 15, the system oscillates into a stable period even when not driven by the driver, and the bus line 12 has a tendency to drift, but the clamp 15. After a period of 40Vc, the buffer driver 6 is turned on again. In period 42 it transitions and changes state, and the same state exists here as described for driver 4, except for the forward tilt. A short time later, in period 44, a plateau state is achieved by driver 6, representing a logic "1" state. Similarly, the bus i path 12 also has the logical value "1".
reach the state. However, the non-inverting clamp 15 must still respond. Beginning with period 46 and continuing during each period, non-inverting clamp 15 changes from a "0" state to a "1" state.
” to rise to the state. During this period, the driver 6 drives the bus line 12 to ensure that the system reaches steady state.
Continue to drive. Such a steady state is achieved during period 48. During period 50 the buffer driver 6 is turned off again, but the system remains held in this state, ie "1", by the non-inverting clamp 15 through the resistor 16. It can therefore be seen that the clamping element of the invention actually holds the bus line in the state in which it was last set in any state.

Now consider the outflow of current through the resistor 16. For purposes of this discussion, current drain is considered positive in resistor 16 when input 18 is positive with respect to output 20. During period 26, non-inverting clamp 15 is stable. However, the bus line 12 is driven by the buffer driver 4. During this period, current begins to flow between input 20 and output 18 as driver 4 and bus line 12 move away from the higher rail, ie, +5 volts. (It is during this transition period that both the P and N channel input transistors are turned on simultaneously.) Therefore, the current from output 18 attempts to reach equilibrium between input 20 and output 18 by resistor 1.
It is discharged through 6.

This stability is achieved during the period 28 when the bus line 12 is in the "0" state and held there by the buffer driver 4. And since the non-inverting clamp 15 has not yet changed state, a constant state exists in which a constant current flows through the resistor 16. The output of the non-inverting clamp 15 is period 3
It starts changing at the beginning of 0 and continues changing during this period. During this period, there is a drop in the current flow through the resistor 16 until finally at the beginning of the period 32 no current flows anymore. During the period 34, the bus line 12 is not being driven by any buffer driver and the system is therefore in a virtual steady state, so that the bus line 12 does not drift substantially from its last set state. Only the current that is determined to be rated is drained through the resistor 16. This stable state lasts until the beginning of period 42, during which bus line 12 is driven from low to high by buffer driver 6. At this point the current is again flowing through the resistor 16
through, but in the opposite direction.

During the period 44, the driver 6 and the bus line 12 remain high and therefore a maximum current drain occurs in which the resistor 16 flows in the other direction to catch up with this high condition. This current drain slowly decreases with the beginning of period 46 as non-inverting clamp 14 has now caught up to the logic "1" state of bus line 12. The driver 6 stops driving the bus line 12 at the beginning of the period 50, so that the system is again held in virtual stability by the clamp 15.

FIG. 5 shows a special non-inverting C.sub.
MOS driver drive 51 is shown. As shown, non-inverting driver 51 consists of two sets of P and N transistors, designated 52 and 54, respectively. Since there is double inversion, the output coming out of the non-inverting driver 51 will be in the state of the input tm. For this non-inverting driver, P and N1 are conventional CMOS gates that are fast but low impedance. On the other hand, P2 and N2
is a low power gate that is not powerful enough to overcome and substantially slow down any drivers such as those driving bus line 12. Therefore, circuit 1 in FIG.
It should be appreciated that by using the special CMO3 circuit 51 of FIG. 5 in place of 5, a feedback resistor such as 16 is no longer acceptable. It must be emphasized that the clamping function can be performed by any non-inverting gates connected in 3 m, by any series combination of an even number of inverting gates of one type or mixed types appropriately connected. or by any series combination of any number of non-inverting gates. Clamps can also be used for suitable direct control of inverting and non-inverting gates.
It can be formed by a combination.

It is to be understood that the invention is not limited to the precise details of the invention or construction shown and described herein, as obvious variations will occur to those skilled in the art.

[Brief explanation of the drawing]

Figure 1 is a complete illustration of the usual method of connecting bus lines. FIG. 2 illustrates current surges that cause overheating of devices connected to the bus line when the bus line is floating in or passing through a "forbidden band." FIG. 3 shows a CMOS bus line to which the driver, input and device of the invention are connected. FIG. 4 is a time/current diagram illustrating the operation of the present invention. FIG. 5 shows an integrated circuit that may be used as an alternative implementation of the invention. 3 and 5, 12 is a bus line, 14 is a non-inverting driver, 15 is a clamp element, 16 is a resistor, 18 is the output of the driver 14, 20 is its input, 51 is a non-inverting c
hros@active circuit, 52. 54 shows each set of P and N transistors, P, , N are normal (low impedance high speed) CMOS gates, and P2 and N2 are low power gates.

Claims (1)

[Scope of Claims] 1) An active bus line clamp for clamping a multi-state bus line of a CMOS system to a specific level of the bus line that would otherwise drift if not clamped, the bus line clamping comprising: Non-inverted C on the bus line to pull out
A MOS buffer driver is connected, the power being represented as a voltage at the input and output of the buffer driver, and a CMOS buffer driver is connected to the first set of low power gates connected to the second set of low power gates. It is equipped with an impedance gate and automatically limits the voltage difference between the input and output of the buffer driver by draining or sourcing current from the bus line, thereby The first end of the resistor is connected to the input of the buffer driver and the second end of this resistor is connected to the output of the buffer driver in order to clamp it to whatever level it was last set to. The clamp mentioned above. 2) having a three-state bus structure including a plurality of bus lines having a tendency to drift from a first state to a second state, a plurality of drivers and a gate connected to at least one of the bus lines; In a CMOS system with a resistor device connected at both ends to the input and output, respectively, of the non-inverting gate for regulating the flow of current to or from the bus line, thereby making the bus line available at any of the drivers. device for clamping the bus line in a particular state, in which the bus line is clamped in whatever state was last set by one of the 3) A device according to claim 2, wherein the non-inverting gate comprises a CMOS buffer driver. 4) A non-inverting CMOS buffer driver is connected to the multi-state bus line of the CMOS system to draw power from this bus line, and this power is expressed as a voltage at the input and output of the buffer amplifier; automatically limits the voltage difference between the buffer driver's input and output by draining or sourcing current to and from the buffer driver, thereby making the bus line consistent with whatever it was last configured to be. A multistate bus line of a CMOS system, in which the first end of the resistor is connected to the input of the buffer driver and the second end of this resistor is connected to the output of the buffer driver, in order to also clamp the level. Active bus line clamp for clamping to a specific level. 5) A non-inverting driver is connected to the multi-state bus line of the CMOS system to detect voltage from the bus line, the non-inverting driver comprising at least two sets of P and N transistors, the first the P and N transistors of the first set are low impedance high speed transistors, the last set of P and N transistors are high impedance low power transistors, and the output of the first set is connected to the input of the second set. and the first set and the last set act as the input and output, respectively, of the non-inverting driver, and the non-inverting driver connects the input of the first set of transistors and the output of the last set of transistors. An active busbar for clamping a multistate busline in a CMOS system to a specific level, clamping the busline at whatever voltage it was last set to by limiting the difference in voltage between track clamp. 6) Active bus line clamp according to claim 5, wherein the non-inverting driver has only one connection line to the bus line, which connection line acts as input and output. 7) Active bus line clamp according to claim 6, wherein the output of the last set of transistors is connected to the input of the first set of transistors. 8) The inputs of a first set of P and N transistors are connected to the multi-state bus line of the CMOS system to sense the voltage present along the bus line, the first set of transistors being low impedance high the inputs of a second set of P and N transistors are connected to the outputs of the first set of transistors, the second set of transistors being high impedance low power transistors for minimum current sinking or sinking; Yes, the output of the second set is the first
connected to the input of the second set, such that the voltage from the output of the second set reflects the voltage at the input of the first set, so that whatever voltage the bus line had at the end of this Active bus line clamps for clamping multi-state bus lines in CMOS systems to a specific voltage. 9) The first set and the second set of P transistors are connected to the first power supply, and the first set and the second set of N transistors are connected to the second power supply. Active busbar line clamps as described in .