JPS63214016A - Channel selection device - Google Patents

Abstract

PURPOSE:To quicken and simplify the confirmation of the storage content of a memory circuit by reading channel selection information from the memory circuit in response to a pulse generated from a pulse generating means, and operating the device. CONSTITUTION:A pulse counter 2 counts a pulse generated from a rotary encoder 1 as a pulse generating means and a decoder 3 converts the output of the pulse counter into an output designating the channel selection information. A control circuit 6 reads the channel selection information from a memory circuit 4 storing plural sets of channel selection information according to the designation by the output of a decoder 3 and displays the result on a display circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel selection device that selects the frequency of radio waves received by a device that receives radio waves transmitted from a broadcasting station or the like.

[Summary of the invention]

The present invention is a channel selection device that selects the frequency of radio waves received by a device that receives radio waves transmitted from a broadcasting station, etc.
A pulse generating means, a pulse counter that counts the pulses generated by the pulse generating means, a decoder that converts the output of the pulse counter into an output that specifies selected channel information, and a signal that is specified by the memory circuit according to the output of the decoder. By providing a control circuit for reading and operating the selected channel information, the device has a function of reading and operating the specified channel selected channel information from the memory circuit in response to the pulse generated by the pulse generating means. The present invention provides a channel selection device in which operations such as checking the memory contents of the memory circuit and storing data in the memory circuit can be performed quickly and easily by manually operating the pulse generating means.

[Conventional technology]

2. Description of the Related Art Conventionally, as a channel selection device for selecting the frequency of radio waves received by a device that receives radio waves transmitted from a broadcasting station, etc., a device equipped with a manually operable pulse generating means has been proposed. A rotary encoder is often used as the pulse generating means. This rotary encoder is configured to transmit a U/D signal indicating the rotation direction of the handle and a CLK signal indicating the rotation speed of the handle by manually rotating the handle. The U/D signal and CLK signal are guided through a plurality of logic circuits to a control circuit that operates a device that determines the reception frequency.

This control circuit receives the two types of signals that have passed through the logic circuit and controls a device that determines the receiving frequency, so that the U/D signal indicates the receiving frequency value at the speed indicated by the CLK signal. increase or decrease in the direction. Therefore, by rotating the handle of the rotary encoder in any direction at any speed,
It is possible to select a station by changing the receiving frequency in a direction and speed corresponding to the direction and speed.

The control circuit also controls the memory circuit to store a specific frequency value in the memory circuit using a manually operated key switch. Recalling the stored frequency value and controlling the device for determining the receiving frequency to cause the receiving frequency value to be the stored frequency value. This is called preset tuning, and if a specific frequency value is stored in the memory circuit in advance, the reception frequency can be set or selected simply by operating the key switch without using the rotary encoder. This means that you can control the station. Also,
The control circuit has a display function to display the frequency value being set.

[Problem that the invention seeks to solve]

By the way, in the conventional channel selection device as mentioned above, in order to check the contents stored in the memory circuit,
The control circuit has a so-called memory scan display function that sequentially displays the contents stored in the memory circuit according to the addresses on the memory circuit. In this function, the direction and speed of the sequential display described above are determined in advance according to conditions set and given to the control circuit. Therefore,
Since the time required for the above-mentioned sequential display is always constant, there is a problem in that it is not possible to display in any direction and speed as necessary, which impedes convenience in use.

Alternatively, the contents stored in the memory circuit can also be confirmed by operating all of the key switches, but especially in a channel selection device equipped with a large number of key switches, Operating the switch is a cumbersome task, which again poses the problem of hindering convenience in use.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a channel selection device that allows quick and easy operation of checking the contents stored in a memory circuit.

Means for Solving Problem c] In the channel selection device according to the present invention, a pulse generation means, a pulse counter for counting pulses generated by the pulse generation means, and an output of the pulse counter are specified as channel selection information. and a control circuit for reading and operating the designated channel selection channel information from a memory circuit storing a plurality of the channel selection channel information in accordance with the designation by the output of the decoder.

[Effect]

In the channel selection device according to the present invention, a pulse counter counts the pulses generated by the pulse generation means, a decoder converts the output of the pulse counter into an output specifying channel selection information, and a control circuit controls the decoder. By reading and operating the designated channel selection channel information from a memory circuit that stores a plurality of channel selection channel information according to the designation by the output, the channel selection is performed from the memory circuit in response to the pulse generated by the pulse generating means. Since it has a function of reading and operating channel information, it is possible to sequentially check the selected channel information according to the direction and speed of operating the pulse generating means.

〔Example〕

Hereinafter, the present invention will be described with reference to specific examples.

As shown in FIG. 1, the channel selection device according to the present invention has a rotary encoder 1 as a pulse generating means. This rotary encoder 1 has a pulse counter 2.
．． The decoder 3 is connected sequentially, and the memory circuit 4
and a display circuit 5 are connected via a switching circuit 7 to a control circuit 6 connected thereto. In this channel selection device, the control circuit 6 controls the frequency determining device 9 of the receiver main body 8 to perform a channel selection operation.

The rotary encoder 1 has a handle IO that is rotatably supported and can be rotated manually,
When the handle 10 is rotated, it generates two types of pulse signals as shown in FIG. The up/down signal U/D shown in FIG. 2 is output from the U/D signal terminal 11, and the clock signal CLK shown in FIG. 2 is output from the signal terminal 12 at CL. In Figure 2,
The section from A to B represents the output when the handle 10 is stopped, the section from B to C represents the output when the handle 10 is rotating clockwise, for example, and the section from C to D represents the output when the handle 10 is stopped. The outputs are shown when the handle 10 is rotating counterclockwise. Now, when the handle 10 is rotated in either direction, the U/
The up/down signal U/D and the clock signal CLK are output from the D terminal 11 and the CLK terminal 12, respectively, and each signal is input to the input terminal 13. of the pulse counter 2.
14 and the switching circuit 7, respectively. 2 above
The pulse counter 2 receives the types of pulse signals,
A signal representing a 4-bit binary number is output from the output terminal 15, and this output signal is determined in the direction of increase or decrease of the binary number by the amplifier down signal U/'D inputted to the input terminal 13. is determined, and the clock signal CLK input to the input terminal I4 is counted. The signal output from the output terminal 15 is input to the input terminal 16 of the decoder 3. This decoder 3 has an output terminal 17 composed of 10 terminals, and the 4-bit binary number represented by the signal input to the input terminal 16 is expressed as any one number from 1 to 10. The above output terminal 1 corresponds to the numerical value converted to decimal number
Voltage is output to one of the 10 terminals of 7.

The output of the output terminal 17 is input to the switching circuit 7. The switching circuit 7 receives the output from the output terminal 17, the up/down signal U/D which is the output of the rotary encoder 1, and the clock signal CLK, and has inputs into which the three types of signals described above are respectively input. It has terminals 18, 19 and 20. The switching circuit 7 also includes two manually operated switches 21.2.
It has two input terminals 23 and 24, each input from 2. The switching circuit 7 includes the plurality of input terminals 18,
19, 20, 23. 24 and multiple logic circuits, tri-state gates and AND gates.

Consists of knot gates. The plurality of logic circuits are controlled by signals input from the input terminals 18, 19, 20, 23, and 24. Above input terminal 1
8 consists of ten terminals, each of which is a tri-state gate 25. ...25 to the preset input terminal 26. of the control circuit 6. ... is connected to 26.

At the same time, the input terminal 18 is connected to the tristate gate 27. . . 27 to the program input terminal 28. of the control circuit 6. ... is connected to 28. The input terminal 19 is connected to input terminals of a tristate gate 29 and a not gate 30, respectively.

The output terminal of the NOT gate 30 is connected to the input terminal of a tristate gate 31. The output terminal of the tri-state gate 29 is connected to the control circuit 6.
The output terminal of the tristate gate 31 is connected to the frequency down terminal 33 of the control circuit 6. The input terminal 20 is connected to respective input terminals of an AND gate 34 and an AND gate 35.

The input terminal 23 is connected to the input terminals of the AND gate 34 and the input gate 136, respectively.

The input terminal 24 is connected to the input terminals of the AND gate 34, AND gate 37, and NOT gate 38, respectively. Further, the output terminal of the NOT gate 36 is connected to the input terminal of the AND gate 35, and the output terminal of the AND gate 35 is connected to the input terminal of the AND gate 37. The output terminal of the not gate 38 is connected to the control terminal of the tristate gate 27,
The output terminal of the AND gate 34 is connected to the control r8 terminal of the tri-state gate 25, and the output terminal of the AND gate 37 is connected to the dry-state gate 1-29, 3.
1 control terminal.

When the switch 22 is open, the input terminal 24 is @L”
At level, AND gate 34 and AND gate 37
Therefore, the tristate gates 29, 31 controlled by the output of the AND gate 37 and the tristate gates 25° . . . 25 controlled by the output of the AND gate 34 are blocked. Since the input terminal 24 is at the "L" level, the not gate 3
The output terminal of 8 becomes 1H''' level, and this output controls the tristate gates 27...27 to make the tristate gates 27...27 conductive.At this time, the rotary encoder When the handle 10 of No. 1 is operated to generate the up/down signal U/D and the clock signal CLK, the decoder 3 outputs the above through the process described above, and this output is sent to the input terminal 1.
8 to the above tristate gate 27. ... 27, passes through the tri-state gate 27, and is input to the program input terminal 28 of the control circuit 6.
．． ...28 Next, when the switch 22 is closed and the input terminal 24 is at the "H" level, this input is input to the AND gate 34 and the AND gate 37. is input to the knot gate 38.

Since the input terminal of the not gate 38 is at the "H" level, the output terminal becomes the "L" level, and therefore the tri-state gates 27...27 are cut off.At this time, the switch 21 is in the closed state. The input terminal 23 is “
If it is at H” level, this input is connected to the AND gate 34.
is input to the knot gate 36. At this time, when the handle 10 of the rotary encoder 1 is operated, the clock signal CLK is transmitted to the input terminal 20.
is inputted to the AND gate 34 from above. The AND gate 34 has the input terminals 23 and 24 set to ``H''.
The clock signal CLK is allowed to pass in order to reach the H level.

The clock signal CL passed through the AND gate 34
K is the tristate gate 25. ...25 to open and close in response to the pulses of the clock signal CLK. The output of the decoder 3 is then transmitted to the tri-state gate 25. . . . is pulsed by the opening/closing of 25 and sent to the present input terminal 26 of the control circuit 6.・
... is input to one of 26.

At this time, the input terminal of the NOT gate 36 is “H2”.
Since the output terminal is at the "L" level, the output terminals of the AND gate 35 and the AND gate 37 become "L" level, and the tristate gates 29 and 31 are cut off. switch 22
remains closed and the switch 21 is opened and the input terminal 23 goes to 'L' level, the output terminal of the AND gate 34 goes to 'L' level, and the tristate gates 25...25 Since the input terminal of the NOT gate 36 is at the "L" level, the output terminal becomes the "H" level, and this output is input to the AND gate 35.Then, the above-mentioned handle of the rotary encoder l 10 is being operated, the clock signal CLK is input from the input terminal 20 to the AND gate 35.The AND gate 35 passes the clock signal CLK because the output terminal of the NOT gate 36 is "H level". This black signal CLK is input to the AND gate 37. Since the input terminal 24 is at the "H" level, the AND gate 37 passes the clock signal CLK, and this clock signal CLK controls the dry state gate 29.31.
+HI, it opens and closes in response to the pulses of the clock signal CLK. At this time, the up/down signal U/D from the rotary encoder 1 is transmitted from the input terminal 19 to the tristate gate 29 and the not gate 30.
is input to. When the amplifier down signal U/D is in the range from B to C in FIG. When the amplifier down signal U/D is in the state from section C to D in FIG. The signal is pulsed and input to the frequency down terminal 33 of the control circuit 6. The control circuit 6 has the program input terminals 28, . . . 28, the preset input terminals 26° . The control circuit 6 has the program input terminal 28. ...When there is an input to one of the terminals 28, the address corresponding to the input terminal is stored in the memory circuit 4, and the memory related to the received program such as the time and frequency value is stored. It is called and displayed on the display circuit 5. The control circuit 6 also has the preset input terminals 26. ...When there is an input to one of the terminals 26, the frequency value stored in the memory circuit 4 having the address corresponding to the input terminal is called up and radio waves of that frequency are received. The frequency determining device 9 is controlled so that the frequency value is displayed on the display circuit 5.

Furthermore, when there is an input to the frequency up terminal 32 or the frequency down terminal 33, the control circuit 6 controls the frequency determining device 9 to set the received frequency value to a predetermined value in accordance with the input terminal. The frequency value is increased or decreased by a numerical value, and the frequency value at each time is displayed on the display circuit 5.

The control circuit 6 also includes the preset input terminal 26. ...Key switch 39 for each of 26
．． ...39 is the tristate gate 25.・・・
- Connected in parallel with each connection from 25.

By operating the key switches 39°...39, the address corresponding to the key switch 39 can be changed to the memory circuit 4 without using the rotary encoder l.
The frequency determining device 9 can be controlled to call up the frequency value stored in the RF signal and receive radio waves of that frequency, and the frequency value can be displayed on the display circuit 5.

With the above configuration, in the channel selection device according to the present invention,
The switches 21 and 22 are used to display the memory related to the received program, to receive radio waves with a pre-stored frequency value, and to increase or decrease the received frequency value by a predetermined value. In these operations, control is performed corresponding to the direction and speed in which the handle 10 of the rotary encoder 1 is operated. Further, the operation for receiving radio waves having a frequency of a pre-stored value is performed using the key switch 39. ...It can also be done using 39.

Next, as shown in FIG. 3, one microcomputer unit is used instead of the one in which the pulse counter 2, the decoder 3, the memory circuit 4, the control circuit 6, and the switching circuit 7 are connected. 40
The same operation as the above-mentioned device can be performed using the Tlt. This microcomputer unit 40 has an input terminal 13 to which the up-down signal U/D is input, an input terminal 14 to which the clock signal CLK is input, an input terminal 23 to which the switch 21 is connected, and the switch 22. It has four input terminals to be connected, an input terminal 24, and two output terminals, an output terminal 41 outputting to the display circuit 5 and an output terminal 42 outputting to the frequency determining device 9.

The operation of this microcomputer unit 40 is as shown in the flowchart in FIG.
When the clock signal CLK is input to the input terminal 14, step 101 and step 102
Next, in step 103, the level of the input terminal 24 is detected. If the input terminal 24 is at the "L" level, then in step 104 the up-down signal U/D input to the input terminal 13 is detected, and the up-down signal U/D becomes "H". If you have the level, step 1
At 05, 1 is added to the address in the memory circuit of the memory that was displayed last time among the memories related to the received program such as time and frequency values stored in the memory circuit in the microcomputer unit 40. The memory at the address is called and displayed on the display circuit 5 in step 107. If the up/down signal U/D is at "L" level, the memory circuit in the microcomputer unit 40 is called in step 106. Among the memories related to received programs such as time and frequency values stored in the memory circuit, 1 is subtracted from the address in the memory circuit of the memory that was displayed last time, and the memory at the resulting address is recalled, and in step 107, the above-mentioned Displayed on the display circuit 5. Then, in steps 101 and 102, the negative edge of the clock signal CLK is detected, and then in step 103, the input terminal 24 is
If the level is "H", then in step 108 the level of the input terminal 23 is detected. If the input terminal 23 is "H" level, then in step 109 the level of the input terminal 13 is detected. The input up-down signal U/D is detected, and the up-down signal U/D is “H”.
” level, in step 110, among the frequency values stored in the memory circuit in the microcomputer unit 40, 1 is added to the address in the memory circuit of the memory circuit used last time. The frequency value stored at the resulting address is called and the frequency value is displayed on the display circuit 5 in step 112. If the up-down signal U/D is at "L" level, step 111
Of the frequency values stored in the memory circuit in the microcomputer unit 40, subtract 1 from the address in the memory circuit that was last used, and then calculate the frequency value stored at the resulting address. The frequency value is displayed on the display circuit 5 in step 112. After detecting the negative edge of the clock signal CLK in steps 101 and 102, if the input terminal 24 is at the "H" level in step 103 and the input terminal 23 is at the "L" level in step 108, then Next, in step 113, the up/down signal U/D input to the input terminal 13 is detected, and if the amplifier down signal U/D is at H" level, the signal is received at that point in step 114. Add a predetermined value to the frequency value of the radio wave,
An output for controlling the frequency determining device 9 to receive radio waves having the frequency of the resulting value is outputted from the output terminal 41, and in step 115, the frequency value is displayed on the display circuit 5, and the up/down If the signal U/D is at the "L" level, in step 116, a predetermined value is subtracted from the frequency value of the radio wave being received at that time, and the frequency is determined so as to receive the radio wave having the frequency of the resulting value. An output for controlling the device 9 is output from the output terminal 41, and the frequency value is displayed on the display circuit 5 in step 117.

〔Effect of the invention〕

As described above, the channel selection device according to the present invention includes a pulse generation means, a pulse counter that counts the pulses generated by the pulse generation means, and an output of the pulse counter that converts the output of the pulse counter into an output that specifies channel selection information. By comprising a decoder and a control circuit that reads and operates the specified channel selection information from a memory circuit that stores a plurality of channel selection channel information +a according to the designation by the output of the decoder, the pulse generated by the pulse generation means is Since it has a function of reading and operating the selected channel information from the memory circuit according to the above, by manually operating the pulse generating means, it is possible to check the memory contents of the memory circuit and write information such as tα to the memory circuit. Operation is quick and easy. That is, compared to the conventional method of using a so-called memory scan display or operating all the key switches to individually call up the contents of the memory circuit, the pulse generation method using a rotary encoder, etc. Being able to perform operations such as confirming the stored contents of the memory circuit and storing data in the memory circuit by operating the means has extremely good operability and contributes to speeding up the above-mentioned operations.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram showing the configuration of a tuning device according to the present invention, FIG. 2 is a waveform diagram showing the output of a rotary encoder included in the tuning device according to the present invention, and FIG. 3 is a wiring diagram showing the configuration of a tuning device according to the present invention. FIG. 4 is a plan view of a microcomputer unit in another embodiment of the channel selection device according to the present invention, and FIG. 4 is a flow chart showing the operation of the microcomputer unit in another embodiment of the channel selection device according to the present invention. 1...Rotary encoder 2...Pulse counter 3...Decoder 4...Memory circuit 6...Control circuit

Claims (1)

[Scope of Claims] Pulse generation means; a pulse counter that counts pulses generated by the pulse generation means; a decoder that converts the output of the pulse counter into an output that specifies selected channel information; and an output of the decoder. a control circuit for reading out and operating the specified channel selection channel information from a memory circuit that stores a plurality of the channel selection channel information according to a specification by the pulse generation means; A channel selection device characterized by having a function of reading and operating station channel information.