JPS63213411A - Snubber circuit - Google Patents

Snubber circuit

Info

Publication number
JPS63213411A
JPS63213411A JP63006015A JP601588A JPS63213411A JP S63213411 A JPS63213411 A JP S63213411A JP 63006015 A JP63006015 A JP 63006015A JP 601588 A JP601588 A JP 601588A JP S63213411 A JPS63213411 A JP S63213411A
Authority
JP
Japan
Prior art keywords
capacitor
transformer
snubber circuit
diode
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63006015A
Other languages
Japanese (ja)
Other versions
JPH0435971B2 (en
Inventor
関 長隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63006015A priority Critical patent/JPS63213411A/en
Publication of JPS63213411A publication Critical patent/JPS63213411A/en
Publication of JPH0435971B2 publication Critical patent/JPH0435971B2/ja
Granted legal-status Critical Current

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  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
  • Protection Of Static Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野ン 不発明は電力変換装置において、半導体素子に加わる過
電圧やdv/dt fir:緩和する為の法論回路(こ
れをスナバ回路という)に関するものである。
[Detailed description of the invention] [Purpose of the invention (Industrial field of application) The purpose of the invention is to provide a circuit (called a snubber circuit) for mitigating overvoltage and dv/dt irradiation applied to semiconductor elements in power converters. ).

(従来の技術) 半導体素子を使用する電力変換装置においては、半導体
素子に加わる過電圧や立ち上シ(以下dv/dt )の
早い電圧で半導体素子が破壊しないように、必らずスナ
バ回路を設ける。第1図は従来から使用されているスナ
バ1路1で、その回路を適用した第2図でその動作の説
明を行なう。第2図はダートターンオアサイリスタ(以
下GTOと記す)を用いたインバータである。
(Prior art) In a power conversion device that uses semiconductor elements, a snubber circuit is always provided to prevent the semiconductor elements from being destroyed by overvoltage applied to the semiconductor elements or voltage with a rapid start-up voltage (hereinafter referred to as dv/dt). . FIG. 1 shows a conventionally used snubber circuit 1, and its operation will be explained with reference to FIG. 2 to which this circuit is applied. FIG. 2 shows an inverter using a dirt turn or thyristor (hereinafter referred to as GTO).

図中1がスナバ回路でコンデンサ11、ダイオード12
及び抵抗13から成る。21と22がGTO、j 3と
24がGTOと逆並列に接続されたダイオードである。
In the figure, 1 is the snubber circuit, which has a capacitor 11 and a diode 12.
and a resistor 13. 21 and 22 are GTOs, and j3 and 24 are diodes connected in antiparallel with the GTO.

25が負荷、26と27はそれぞれE/2の直流電源で
ある。第2図の基本的な動作は、GTO2Jと22が交
互にオンとオフを繰り返すことでそれによって負荷25
に交流が印加される。GTOJ Jがオン、GTO22
がオフしていて負荷25に電流工が流れているときに、
GTOJJをオフした瞬間の波形を第3図に示す。GT
Oはそのダートカソード間に逆方向に電流1gt−流す
と、ターンオフしアノードカソード間に電圧V、が図示
のように加わる。
25 is a load, and 26 and 27 are each an E/2 DC power source. The basic operation in Figure 2 is that GTO 2J and 22 alternately turn on and off, thereby causing the load 25
An alternating current is applied to the GTOJ J is on, GTO22
is off and current is flowing through load 25,
Figure 3 shows the waveform at the moment GTOJJ is turned off. GT
When a current of 1 gt is passed in the opposite direction between the dirt cathode of O, it is turned off and a voltage V is applied between the anode and cathode as shown.

(発明が解決しようとする昧題ン 第3図のVDはGTO,? 1とスナバ1のコンデンサ
11とダイオード12の作る閉回路のインダクタンスt
とターンオフ直前のアノード電流、ナなわち負荷電流■
の大きさで決−174も工も大きい程マDは高くなる。
(The problem to be solved by the invention is that VD in FIG. 3 is GTO,
and the anode current just before turn-off, i.e. the load current■
Determined by the size of -174 The larger the size, the higher the maD.

又マ、は電源26、GTO21と負荷25の閉回路及び
電源27とダイオード22及び負荷25の閉回路の浮遊
インダクタンスLsと浮ai抗Rs及びコンデンサ11
のキャノJ?シタンスC1負荷電流■に依存し、t8と
Iは大きい程又Cは小さb程v、は小さくなる。GTO
を使用するうえてマD=’Pも共に小さ、い方が望まし
く、と9わけVpが高いとそれだけ高耐圧のGTOを使
用しなければならなくなる。しかし、マ、を低下させる
為に、コンデンサ11のCを大きくすると、GTO21
がオンオフの一周期に−C(v  −E J2+’−C
12のエネ2P         2 ルギの大半が抵抗13に消費される。ここでEは電源2
6と22の電圧の和である。例を挙げると周波数fを1
000 Hz * C=21’F r vp =400
 V *E=200 VとするとSOWとなる。
Also, Ma is the floating inductance Ls of the closed circuit of the power supply 26, GTO 21 and the load 25, the closed circuit of the power supply 27, the diode 22 and the load 25, the floating ai resistance Rs, and the capacitor 11.
Cano J? The capacitance C1 depends on the load current ■, and the larger t8 and I are, or the smaller C is, the smaller v is. G.T.O.
In addition, it is desirable that both D='P and D='P be small, and if Vp is high, a GTO with a high withstand voltage must be used. However, if C of capacitor 11 is increased in order to lower M, GTO21
-C(v -E J2+'-C
Most of the energy 2P 2 of 12 is consumed by the resistor 13. Here E is power supply 2
It is the sum of the voltages of 6 and 22. For example, if the frequency f is 1
000 Hz * C=21'F r vp =400
When V*E=200 V, it becomes SOW.

これは装置の効率低下をもたら1−と共に、抵抗の外形
が大きくなり発熱を伴なうので装置の小形化の妨げとな
っている。
This causes a decrease in the efficiency of the device, and the external shape of the resistor becomes large, causing heat generation, which hinders miniaturization of the device.

本発明の目的はコンデンサのエネルギの一部を再利用す
ることによって装置の効率向上と小形化を図ることがで
きるスナバ回路を提供することにある。
An object of the present invention is to provide a snubber circuit that can improve the efficiency and downsize the device by reusing a portion of the energy of the capacitor.

[発明の構成コ (課題を解決するための手段) 本発明は上記目的を達成するために、コンデンサとこの
コンデンサの充電方向に接続されるダイオードからなり
、電力変換装置を構成する正負直流母線間に直列接続さ
れる一対の半導体素子のそれぞれに並列接続されるスナ
バ回路において、前記スナバ回路のそれぞれのダイオー
ドに並列に変成器を設け、前記コンデンサの放電時前記
変成器の2次巻線を介して前記コンデンサのエネルギを
電源へ回生するようにしたものである。
[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above object, the present invention provides a power converter comprising a capacitor and a diode connected in the charging direction of the capacitor, between positive and negative DC buses constituting a power converter. In a snubber circuit connected in parallel to each of a pair of semiconductor elements connected in series, a transformer is provided in parallel to each diode of the snubber circuit, and when the capacitor is discharged, The energy of the capacitor is regenerated to the power source.

(作用) 本発明は、スナバ回路のコンデンサのエネルギを再利用
することにより、装置の効率を数チ向上させうろことが
でき、また発熱部が減少したことによシ高密度の実装が
可能となり、装置の小形化が可能となる。
(Function) The present invention improves the efficiency of the device by several orders of magnitude by reusing the energy of the capacitor in the snubber circuit, and also enables high-density packaging by reducing the number of heat generating parts. , it becomes possible to downsize the device.

(実施例) 第4図(、) (b)が本発明のスナバ回路の構成図で
、それを適用した第5図の回路でその動作を説明する。
(Embodiment) FIG. 4(,)(b) is a block diagram of the snubber circuit of the present invention, and its operation will be explained using the circuit of FIG. 5 to which the snubber circuit is applied.

第5図は本発明の一実施例を示す構成図で。FIG. 5 is a configuration diagram showing one embodiment of the present invention.

第2図と同一部に同一符号を付して、その説明を省略す
る。
The same parts as in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

第5図において、11aと11bはコンデンサ、12g
と12bはダイオード、14aと14bは変圧器、15
mと15bはリアクトル又は抵抗(以下インピーダンス
素子と記す)、16aと16bはダイオードである。
In Figure 5, 11a and 11b are capacitors, 12g
and 12b are diodes, 14a and 14b are transformers, 15
m and 15b are reactors or resistors (hereinafter referred to as impedance elements), and 16a and 16b are diodes.

GTO21がオン、GTO22がオフしている状態では
、コンデンサ11*O@、荷は0、コンデンサJlbは
Eに充電されている。負荷電流ILは電源26→GTO
21→負荷25のループで流れている。この状態でGT
O21のダニトに負の信号を加えGTO21′t−オフ
すると共に、GTO22のダートに正の信号t−mえて
GTO22をオンする。これによシU点の電位は0点を
基準として−E/2となる。
When GTO21 is on and GTO22 is off, capacitor 11*O@, the load is 0, and capacitor Jlb is charged to E. Load current IL is from power supply 26 to GTO
It flows in a loop of 21→load 25. GT in this state
A negative signal is applied to the dunit of the O21 to turn off the GTO21't-, and a positive signal tm is applied to the dirt of the GTO22 to turn on the GTO22. As a result, the potential at the U point becomes -E/2 with respect to the 0 point.

負荷25が純抵抗であれば、GTO22を介して負荷電
流ILが流れ、又誘導性負荷であれば負荷電流ILは瞬
時には変化しないので、ダイオード24を介して電源2
2よシ負荷電流ILが流れるループが形成される。コン
デンサllaはGTO21のオフの直後、第3図に示す
ようにVpに光電されるが、2点とU点の電位差はEで
あるため、マ、−Hの電圧がダイオード12&に逆電圧
として印加され、ダイオード12mはオフとなる。この
後コンデンサl1mの電圧がEになるまで、変圧器14
&の1次巻線と2次巻線の夫々を進してコンデンサエネ
ルギが電源26.27に回生される様子を説明する。
If the load 25 is a pure resistance, the load current IL flows through the GTO 22, and if it is an inductive load, the load current IL does not change instantaneously, so the load current IL flows through the power supply 2 through the diode 24.
A loop is formed in which the load current IL flows. Immediately after the GTO21 is turned off, the capacitor lla is photovolted to Vp as shown in Fig. 3, but since the potential difference between the two points and the U point is E, the voltage of M and -H is applied to the diode 12& as a reverse voltage. The diode 12m is turned off. After this, until the voltage of capacitor l1m becomes E, transformer 14
The manner in which the capacitor energy is regenerated to the power supply 26 and 27 by advancing each of the primary winding and the secondary winding of & will be explained.

ダイオード12&と並列に図示極性に1次巻線が接続さ
れた変圧器24aの2次巻線には、n (vp −E 
)の電圧が誘起される。ここでnは変圧器14aの2次
巻線と1次巻憩の比である。この電圧がEよシ高い場合
はダイオード16hがオンとなシ、変圧器J4JLの2
次巻線にt流が流れる。インピーダンス素子25aはこ
の電流を制限する。この期間中のコンデンサllaのエ
ネルギは変圧器14aの1次巻線と2次巻線を介して電
源26.27に回生されるが、変圧器14aの1次巻線
の電圧が[/n以下になるとダイオード16thがオフ
して2次巻線を介しての電源26.27への回生はとま
る。厳密に述べると、インピーダンス素子15aあるい
は変圧器14aの侍りインダクタンスの作用でE/nよ
シ低い値で回生がとまる。
The secondary winding of the transformer 24a, whose primary winding is connected in parallel with the diode 12& with the polarity shown, has n (vp −E
) is induced. Here, n is the ratio of the secondary winding to the primary winding of the transformer 14a. If this voltage is higher than E, diode 16h is turned on and transformer J4JL's 2
A t current flows through the next winding. Impedance element 25a limits this current. During this period, the energy in the capacitor lla is regenerated to the power supply 26.27 via the primary and secondary windings of the transformer 14a, but the voltage of the primary winding of the transformer 14a is below [/n When this happens, the diode 16th turns off and regeneration to the power source 26, 27 via the secondary winding stops. Strictly speaking, regeneration stops at a value lower than E/n due to the effect of the impedance element 15a or the impedance inductance of the transformer 14a.

これ以降コンデンサ電圧がEVC4するまでのエネルギ
の差分は一旦変圧器14hの励磁エネルギとして貯えら
れた後、変圧器14hとダイオードJ、2aの閉回路で
消費される。
After this, the energy difference until the capacitor voltage reaches EVC4 is temporarily stored as excitation energy of the transformer 14h, and then consumed in the closed circuit of the transformer 14h and the diodes J and 2a.

次にGTO22がオンする際、コンデンサllbのエネ
ルギが電源26.27に回生されろ過8について述べる
。コンデンサllbがEに充電されている状態でGTO
22がオンすると、変圧器14bの1次巻線には・印を
付した側が正となる極性で電圧Eが印加される変圧器1
4bの2次巻線にはngが誘起され、ダイオード16b
がオンとなる。
Next, when the GTO 22 is turned on, the energy of the capacitor llb is regenerated to the power supply 26, 27, and the filtration 8 will be described. GTO with capacitor llb charged to E
22 is turned on, the voltage E is applied to the primary winding of the transformer 14b with the polarity where the marked side is positive.
ng is induced in the secondary winding of 4b, and the diode 16b
turns on.

インピーダンス素子15bの両端には(n−1)Eの電
圧が加わる。インピーダンス素子15bのインピーダン
スを2とすると(n−1)E/Zの電流が変圧器2次巻
線に流れる。かくしてコンデンサ11bのエネルギは変
圧器14bを介して電源に回虫されるが、変圧器Job
の2次電圧がEよシ低くなると、ダイオード16bがオ
フして回生ぐ止まる。インピーダンス素子15bをリア
クトルとすると、リアクトルの働きでたとえ変圧器14
bの2次電圧がEよシ低くても電流′fc流し続けよう
トスるが、いずれOとなる。このときコンデンサ11b
tlC残った電荷はコンデンサllb→変圧器14 b
4GTO22のループで放電し、0になった後、変圧器
14bに貯えられた励磁エネルギ分は、ダイオード12
bと変圧器14b内で消費される。
A voltage of (n-1)E is applied to both ends of the impedance element 15b. If the impedance of the impedance element 15b is 2, a current of (n-1)E/Z flows into the transformer secondary winding. Thus, the energy in the capacitor 11b is transferred to the power supply via the transformer 14b, but the transformer Job
When the secondary voltage becomes lower than E, the diode 16b turns off and regeneration stops. If the impedance element 15b is a reactor, the function of the reactor will cause the transformer 14 to
Even if the secondary voltage of b is lower than E, the current 'fc will continue to flow, but it will eventually become O. At this time, capacitor 11b
tlC The remaining charge is transferred from capacitor llb to transformer 14 b
After being discharged in the loop of 4GTO22 and becoming 0, the excitation energy stored in the transformer 14b is transferred to the diode 12.
b and is consumed within the transformer 14b.

GTO22がオフ、 GTO21がオンとなる過程でも
全く相似の動作により、夫々のコンデンサllaとll
bのエネルギは大部分電源に戻すことが出来る。実験に
よる回生率は55ないし70チであるが、定数の選択を
適切に選べば更に回虫率を上げることは可能である。
Even in the process where GTO22 turns off and GTO21 turns on, the respective capacitors lla and ll
Most of the energy in b can be returned to the power supply. The regeneration rate according to experiments is between 55 and 70, but it is possible to further increase the roundworm rate if the constants are selected appropriately.

[発明の効果コ 本発明によって得られる効果t−マとめると次のように
なる。
[Effects of the Invention] The effects obtained by the present invention can be summarized as follows.

(イ)スナバ回路のコンデンサのエネルギを再利用する
ことによシ装置の効率を数チ向上させうろこと ←)発熱部が減少したことにより高密度の実装が可能と
なり、装置の小形化が可能となったことである。
(a) By reusing the energy of the capacitor in the snubber circuit, the efficiency of the device can be improved by several orders of magnitude. ←) By reducing the number of heat generating parts, high-density packaging is possible, making it possible to downsize the device. This is what happened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のスナバ回路、第2図は第1図の回路を通
用した回路、第3図は第2因のGTOのアノード電圧と
オフr−1電流との関係を示す波形図、第4図(a) 
(b)が本発明のスナバ回路のそれぞれ異なる構成図、
85図は本発明のスナバ回路の一実施例を示す図である
。 1・・・スナバ回路、11.Ila、llb・・・コン
デンサ、12.12m、12b・・・ダイオード、JJ
−−−抵抗、14m、14b・・・変圧器、15a。 15b・・・リアクトル又は抵抗、21.22・・・G
TO123,24・・・ダイオード、25・・・負荷、
26゜27・・・電源。 出願人代理人 弁理士 鈴 江 武彦 第2図 第3図      第′図 第5図
Figure 1 is a conventional snubber circuit, Figure 2 is a circuit using the circuit in Figure 1, Figure 3 is a waveform diagram showing the relationship between the GTO anode voltage and off-r-1 current, which is the second cause. Figure 4 (a)
(b) is a different configuration diagram of the snubber circuit of the present invention,
FIG. 85 is a diagram showing an embodiment of the snubber circuit of the present invention. 1... Snubber circuit, 11. Ila, llb...Capacitor, 12.12m, 12b...Diode, JJ
---Resistance, 14m, 14b...Transformer, 15a. 15b...Reactor or resistance, 21.22...G
TO123, 24...Diode, 25...Load,
26°27...Power supply. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 'Figure 5

Claims (1)

【特許請求の範囲】[Claims] コンデンサとこのコンデンサの充電方向に接続されるダ
イオードからなり、電力変換装置を構成する正負直流母
線間に直列接続される一対の半導体素子のそれぞれに並
列接続されるスナバ回路において、前記スナバ回路のそ
れぞれのダイオードに並列に変成器を設け、前記コンデ
ンサの放電時前記変成器の2次巻線を介して前記コンデ
ンサのエネルギを電源へ回生するようにしたことを特徴
とするスナバ回路。
In a snubber circuit, which is composed of a capacitor and a diode connected in the charging direction of the capacitor, and is connected in parallel to each of a pair of semiconductor elements connected in series between positive and negative DC buses constituting a power converter, each of the snubber circuits A snubber circuit characterized in that a transformer is provided in parallel to the diode, and when the capacitor is discharged, energy of the capacitor is regenerated to a power source via a secondary winding of the transformer.
JP63006015A 1988-01-14 1988-01-14 Snubber circuit Granted JPS63213411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63006015A JPS63213411A (en) 1988-01-14 1988-01-14 Snubber circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63006015A JPS63213411A (en) 1988-01-14 1988-01-14 Snubber circuit

Publications (2)

Publication Number Publication Date
JPS63213411A true JPS63213411A (en) 1988-09-06
JPH0435971B2 JPH0435971B2 (en) 1992-06-12

Family

ID=11626877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63006015A Granted JPS63213411A (en) 1988-01-14 1988-01-14 Snubber circuit

Country Status (1)

Country Link
JP (1) JPS63213411A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119574A (en) * 1988-10-26 1990-05-07 Kyushu Univ Switching power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119574A (en) * 1988-10-26 1990-05-07 Kyushu Univ Switching power supply

Also Published As

Publication number Publication date
JPH0435971B2 (en) 1992-06-12

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