JPS63213359A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63213359A JPS63213359A JP4536587A JP4536587A JPS63213359A JP S63213359 A JPS63213359 A JP S63213359A JP 4536587 A JP4536587 A JP 4536587A JP 4536587 A JP4536587 A JP 4536587A JP S63213359 A JPS63213359 A JP S63213359A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- point metal
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000002844 melting Methods 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 230000008018 melting Effects 0.000 claims abstract description 31
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 18
- 229910000510 noble metal Inorganic materials 0.000 claims description 10
- 239000003870 refractory metal Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 description 16
- 239000010937 tungsten Substances 0.000 description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 3
- 229910021339 platinum silicide Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten halide Chemical class 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置における多層配線の微細化、平坦化
および高品質化を図る半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device that achieves miniaturization, planarization, and high quality of multilayer wiring in a semiconductor device.
第２図（ａ）〜（ｅ）は九従来の半導体装置の製造方法
を工程１１１１Ｋ示す断面図である。主表面の一部に反
対導電型の拡散層２１を有する半導体基板２０の表面に
絶縁膜２２を全面的に形成し拡散層２１の一部を露出す
るように絶縁膜２２を選択除去しコンタクトホール２３
を開孔する。しかる後、導体膜２４を全面に形成し、フ
ォトリングラフィ等によシ所定のパターニングを施し第
１の配線層とする（第２図（ａ））。FIGS. 2(a) to 2(e) are cross-sectional views showing step 1111K of a conventional semiconductor device manufacturing method. An insulating film 22 is formed entirely on the surface of a semiconductor substrate 20 having a diffusion layer 21 of the opposite conductivity type on a part of the main surface, and the insulating film 22 is selectively removed so as to expose a part of the diffusion layer 21 to form a contact hole. 23
Drill a hole. Thereafter, a conductor film 24 is formed over the entire surface and subjected to predetermined patterning by photolithography or the like to form a first wiring layer (FIG. 2(a)).
その第１の配線層および絶縁膜２２の全表面に絶縁膜２
５を形成し、導体膜２４の一部を露出するるように絶縁
膜２５を選択除去してスルーホール２６を開孔する（第
２図伽）〕。An insulating film 2 is formed on the entire surface of the first wiring layer and the insulating film 22.
5 is formed, and the insulating film 25 is selectively removed so as to expose a part of the conductive film 24, thereby forming a through hole 26 (FIG. 2).
さらに、導体膜２７を全面に形成後、フォトリソグラフ
ィ等によシ導体膜２７に所定のパターニングを施し、第
２の配線層とする（第２図（Ｃ））。Further, after forming the conductor film 27 on the entire surface, the conductor film 27 is patterned in a predetermined manner by photolithography or the like to form a second wiring layer (FIG. 2(C)).
しかしながら上述した従来の半導体装置では、コンタク
トホール部において、直接拡散層上に導体膜を形成して
いるのでアロイスパイクを起す可能性があった。また、
コンタクトホール部、スルーホール部において導体膜に
段差ができ、配線時に段差による段切れを発生する可能
性もあった。However, in the conventional semiconductor device described above, since the conductor film is formed directly on the diffusion layer in the contact hole portion, alloy spikes may occur. Also,
Steps were formed in the conductor film at the contact hole portion and through hole portion, and there was a possibility that the step would cause breakage during wiring.
このような段差をなくすため各ホールに導体膜を充填す
るとしても、先づ、導体膜をコンタクトホール、スルー
ホールに各ホールを埋める程厚く形成し、次に導体膜を
平坦化するためのエツデバック工程を行なわなければな
らないので製造工程が増加し、生産性が低下するという
欠点があった。Even if each hole is filled with a conductive film to eliminate such a step, the conductive film is first formed thick enough to fill each hole in the contact hole and through hole, and then an etched back layer is applied to flatten the conductive film. This method has the disadvantage that the number of manufacturing steps increases and productivity decreases.
本発明は、コンタクトホールよシ露出した拡散層上にバ
リアーメタルとして貴金属化合膜を形成した後、この上
に高融点金属膜を選択形成してコンタクトホールを充填
し、さらにその上に導体膜と高融点金属膜を形成し所定
のパターニングを施し第１の配線層とした後、絶縁膜を
全面に被覆し、高融点金属膜が露出するようスルーホー
ルを形成し、この高融点金属膜上の露出部に高融点金属
膜を選択成長させてスルーホールを充填するものである
。In the present invention, after a noble metal compound film is formed as a barrier metal on the diffusion layer exposed through the contact hole, a high melting point metal film is selectively formed on this to fill the contact hole, and then a conductive film is formed on top of the noble metal compound film. After forming a high melting point metal film and performing predetermined patterning to form the first wiring layer, the entire surface is covered with an insulating film, a through hole is formed to expose the high melting point metal film, and a through hole is formed to expose the high melting point metal film. A high melting point metal film is selectively grown on the exposed portion to fill the through hole.
本発明はコンタクトホールにおける導体膜のアロイスパ
イクの発生を抑え、コンタクトホールおよびスルーホー
ルにおける導体膜の段切れを々くすことができる。The present invention can suppress the occurrence of alloy spikes in the conductor film in contact holes, and can reduce the number of breaks in the conductor film in contact holes and through holes.
〔実施例〕 次に、本発明について図面を参照して詳細に説明する。〔Example〕 Next, the present invention will be explained in detail with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明に係る半導体装置の製造
方法の一実施例を製造工程順に示す断面図である。FIGS. 1(a) to 1(f) are cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of manufacturing steps.
ｎ型シリコン基板１は、その主表面の一部にｐ型拡散層
２ 、２ａ ｔ−有し、ｐ型拡散層２内にはさらに、ｎ
型拡散層３が形成されている。先ず、ｎ型シリコン基板
１の全表面にシリコン酸化膜４（第１の絶縁膜）を形成
する。次に、ｐ重拡散層２ａおよびｎ型拡散層３の一部
を露出するようシリコン酸化膜４を選択除去し、コーン
タクトホール５を開孔する。このコンタクトホール開孔
後、シリコン酸化膜４の表面にスパッタリング等によシ
白金を全面的に付着させ、約５００℃の熱処理によシコ
ンタクトホール５の開孔部の白金のみを選択的に白金シ
リサイド６（貴金属化合膜）と成し、それ以外の白金は
王水等によυ除去する（第１図（ａ））。The n-type silicon substrate 1 has p-type diffusion layers 2 and 2a on a part of its main surface, and the p-type diffusion layer 2 further includes an n-type diffusion layer.
A type diffusion layer 3 is formed. First, a silicon oxide film 4 (first insulating film) is formed on the entire surface of an n-type silicon substrate 1. Next, the silicon oxide film 4 is selectively removed so as to expose a portion of the p-heavy diffusion layer 2a and the n-type diffusion layer 3, and a cone tact hole 5 is opened. After this contact hole is opened, platinum is deposited on the entire surface of the silicon oxide film 4 by sputtering or the like, and then only the platinum in the opening of the contact hole 5 is selectively coated with platinum by heat treatment at about 500°C. Silicide 6 (noble metal compound film) is formed, and other platinum is removed with aqua regia or the like (FIG. 1(a)).
次に、タングステンのハロゲン化物を用いたＣＶＤ （
Ｃｈｅｍｌｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏ
ｎ）方法により、白金シリサイド６の表面のみにタング
ステン膜Ｔ（第１の高融点金属膜）を形成し、コンタク
トホール５を充填して絶縁膜４の表面を平坦化する（第
１図（ｂ））。Next, CVD using tungsten halide (
Chemlcal Vapor Depositio
n) method, a tungsten film T (first high melting point metal film) is formed only on the surface of the platinum silicide 6, and the contact hole 5 is filled to flatten the surface of the insulating film 4 (see FIG. 1(b)). )).
その後、絶縁膜４および高融点金属膜７の表面に、アル
ミニウム膜８（第１の導体膜）を蒸着させ、さらに、こ
のアルミニウム膜８上にタングステン膜９（第２の高融
点金属膜）を形成する。次に、フォトリングラフイー等
によシアルミニウム膜８およびタングステン膜９に所定
のバターニングを施し第１の配線層とする（第１図（Ｃ
））。Thereafter, an aluminum film 8 (first conductor film) is deposited on the surfaces of the insulating film 4 and the high melting point metal film 7, and a tungsten film 9 (second high melting point metal film) is further deposited on the aluminum film 8. Form. Next, the sialuminium film 8 and the tungsten film 9 are patterned in a predetermined manner by photolithography or the like to form a first wiring layer (see Fig. 1(C).
)).
そして、プラズマＣＶＤ法等により第１の配線層上に、
シリコン窒化膜１０（第２の絶縁膜〕を厚めに形成した
後、エッチバック法等にょシ凹凸を削シ取って表面を平
坦にし、次いで、タングステン膜９の一部を露出するよ
うシリコン酸化膜１０を、選択除去し、スルーホール１
１全開孔する（第１図（ｄ））。Then, on the first wiring layer by plasma CVD method or the like,
After forming a silicon nitride film 10 (second insulating film) to be thick, the surface is flattened by removing any unevenness using an etch-back method, and then a silicon oxide film is formed so as to expose a part of the tungsten film 9. 10, selectively remove through hole 1
1. Open the entire hole (Fig. 1(d)).
この露出したタングステン膜９部分に、タングステンの
ハロゲン化物を用いたＣＶＤ法等によシ選択成長させて
タングステン膜１２ （［３０ｉ％Ｍ点膜〕を形成し、
スルーホール１１を充填する（第１図（ｅ））。A tungsten film 12 ([30i% M point film]) is formed on the exposed tungsten film 9 by selective growth using a CVD method using a tungsten halide.
The through hole 11 is filled (FIG. 1(e)).
次に、シリコン窒化膜１０およびタングステン膜１２の
全表面にわたってアルミニウム膜１３（第２の導体膜）
を形成し、フォトリングラフィ等によシアルミニウム膜
１３に所定のバターニングを施し、第２の配線層とする
（第１図（ｆ））。Next, an aluminum film 13 (second conductor film) is formed over the entire surface of the silicon nitride film 10 and the tungsten film 12.
A predetermined patterning is applied to the sia aluminum film 13 by photolithography or the like to form a second wiring layer (FIG. 1(f)).
本実施例では、コンタクトホール５のバリアーメタルと
して白金シリサイドを用いたが、パラジウム等の貴金属
化合物を代用してもよい。In this embodiment, platinum silicide is used as the barrier metal of the contact hole 5, but a noble metal compound such as palladium may be used instead.
マタ、コンタクトホール５とスルーホール１１を充填す
る高融点金属としてはタングステン膜６．１２を用いた
が、他の高融点金属でも可能であり、下地の金属とこの
上に形成する充填用金属は違う元素の高融点金属を使用
してもよい。ただし、スルーホールにおける第２の高融
点金属膜とその上に形成する第３の高融点金属膜とは選
択成長させる関係上、同一元素である方がよい。Tungsten film 6.12 was used as the high melting point metal to fill the contact hole 5 and through hole 11, but other high melting point metals can also be used. Refractory metals of different elements may be used. However, it is preferable that the second high melting point metal film in the through hole and the third high melting point metal film formed thereon be of the same element because of selective growth.
次に、本発明の他の実施例として、３／ｉ配線の半導体
装置について説明する。Next, as another embodiment of the present invention, a semiconductor device with 3/i wiring will be described.
まず第１図（ｆ）に示すようにアルミニウム膜１３を全
面に形成した後にその表面にタングステン膜を形成し、
所定のバターニングを施し第２の配線層を形成した後、
その表面にシリコン窒化膜を第１図（ｄ）と同様に平坦
に形成する。次に、タングステン膜の一部を露出するよ
うにシリコン窒化膜上にスルーホールを開孔し、さらに
、このスルーホールを充填するよう露出したタングステ
ン膜上にタングステン膜を選択成長させる。その後、シ
リコン窒化膜とタングステン膜上にアルミニウム膜を形
成する。最後に、このアルミニウム膜に所定のバターニ
ングを施し、第３の配線層を形成する。First, as shown in FIG. 1(f), an aluminum film 13 is formed on the entire surface, and then a tungsten film is formed on the surface.
After performing predetermined patterning and forming the second wiring layer,
A silicon nitride film is formed flat on the surface as shown in FIG. 1(d). Next, a through hole is formed on the silicon nitride film to expose a part of the tungsten film, and a tungsten film is selectively grown on the exposed tungsten film to fill the through hole. After that, an aluminum film is formed on the silicon nitride film and the tungsten film. Finally, this aluminum film is subjected to predetermined patterning to form a third wiring layer.
このような工程を順次繰夛返すことにより、３層以上の
多層配線を形成することが可能となる。By sequentially repeating these steps, it becomes possible to form a multilayer wiring having three or more layers.
本発明を適用する半導体装置としては、バイポーラ型ト
ランジスタおよび電界効果型トランジスタが考えられる
。また、基板の材料としてはシリコンのｉｔか■−■族
化合物牛導体も使用できる。Semiconductor devices to which the present invention is applied include bipolar transistors and field effect transistors. Further, as the material of the substrate, silicon IT or ■-■ group compound conductors can be used.
以上説明したように本発明によれば、半導体基板上のス
ルーホール部に貴金属化合膜を選択成長することによシ
、貴金属化合膜がバリアーメタルとして働くので、アロ
イスパイクを低減することが可能である。As explained above, according to the present invention, alloy spikes can be reduced by selectively growing a noble metal compound film on the through-hole portion of a semiconductor substrate, so that the noble metal compound film acts as a barrier metal. be.
又、コンタクトホール、スルーホールに高融点金属を選
択成長することによシホールが充填されるので、各ホー
ル上に形成する配線層の段差がなくなシ、配線の段切れ
が防止できる。さらに、ホールの充填は選択成長法であ
るので工程が１工程で済むので生産性が向上する。Further, since contact holes and through holes are filled with holes by selectively growing a high melting point metal, there is no level difference in the wiring layer formed over each hole, and breakage of the wiring can be prevented. Furthermore, since the holes are filled by a selective growth method, only one step is required, which improves productivity.
第１図（ａ）〜０）は本発明に係る半導体装置の製造方
法の一実施例を工程順に示す断面図、第２図（ａ）〜（
ｃ）は従来の半導体装置の製造方法を工程順に示す断面
図である。
１φ・・・ｎ型シリコン基板、２，２ａ ・・−・ｐ
型拡散層、３・・・・ｎ型拡散層、４・・・・シリコン
酸化膜、５−・・・コンタクトホール、６・・・・白金
シリサイド、７，９．１２−・拳・タングステン膜、８
．１３・・・・アルミニウム膜、１０・１１０・シリコ
ン窒化膜、１１・・φ・スルーホール。FIGS. 1(a) to 0) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS. 2(a) to 0)
c) is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps; 1φ...n-type silicon substrate, 2, 2a...-p
Type diffusion layer, 3...n type diffusion layer, 4...silicon oxide film, 5-...contact hole, 6...platinum silicide, 7,9.12--fist/tungsten film , 8
．． 13...aluminum film, 10, 110, silicon nitride film, 11...φ through hole.
Claims (3)
膜を被着させ、この第１の絶縁膜の所定箇所を除去して
前記拡散層の一部を露出しコンタクトホールを開孔する
工程と、このコンタクトホールから露出した前記拡散層
上に貴金属化合膜を形成する工程と、この貴金属化合膜
上にのみ第１の高融点金属膜を選択成長させ前記コンタ
クトホールを充填する工程と、前記第１の絶縁膜および
第１の高融点金属膜上に第１の導体膜を被着後、この第
１の導体膜上に第２の高融点金属膜を形成し、前記第１
の導体膜と第２の高融点金属膜とを所定パターンとなる
ように選択除去して第１の配線層を形成する工程と、前
記第１の配線層と第１の絶縁膜上に第２の絶縁膜を表面
が平坦化するよう形成し、この第２の絶縁膜の所定箇所
を除去して前記第２の高融点金属膜の一部を露出しスル
ーホールを開孔する工程と、前記第２の高融点金属膜の
露出部に第３の高融点金属膜を選択成長させ、前記スル
ーホールを充填する工程と、前記第２の絶縁膜と第３の
高融点金属膜上に第２の導体膜を形成し、この第２の導
体膜を所定パターンとなるように選択除去して第２の配
線層を形成する工程とを含むことを特徴とする半導体装
置の製造方法。(1) A first insulating film is deposited on the main surface of a semiconductor substrate having a diffusion layer, a predetermined portion of the first insulating film is removed to expose a part of the diffusion layer, and a contact hole is opened. a step of forming a noble metal compound film on the diffusion layer exposed from the contact hole; and a step of selectively growing a first high melting point metal film only on the noble metal compound film to fill the contact hole. , after depositing a first conductive film on the first insulating film and the first high melting point metal film, a second high melting point metal film is formed on the first conductive film, and the second high melting point metal film is formed on the first conductive film;
forming a first wiring layer by selectively removing the conductor film and the second high melting point metal film in a predetermined pattern; and forming a second wiring layer on the first wiring layer and the first insulating film. forming an insulating film with a flat surface, removing a predetermined portion of the second insulating film to expose a part of the second high-melting point metal film and opening a through hole; selectively growing a third high melting point metal film on the exposed portion of the second high melting point metal film and filling the through hole; 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a conductor film; and selectively removing the second conductor film in a predetermined pattern to form a second wiring layer.
特許請求の範囲第１項記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the second and third refractory metal films are of the same element.
膜を被着させ、この第１の絶縁膜の所定箇所を除去して
前記拡散層の一部を露出しコンタクトホールを開孔する
工程と、このコンタクトホールから露出した前記拡散層
上に貴金属化合膜を形成する工程と、この貴金属化合膜
上にのみ第１の高融点金属膜を選択成長させ前記コンタ
クトホールを充填する工程と、前記第１の絶縁膜および
第１の高融点金属膜上に第１の導体膜を形成後、この第
１の導体膜上に第２の高融点金属膜を形成し、前記第１
の導体膜と第２の高融点金属膜とを所定パターンとなる
ように選択除去して第１の配線層を形成する工程と、前
記第１の配線層と第１の絶縁膜上に第２の絶縁膜を表面
が平坦化するよう形成し、この第２の絶縁膜の所定箇所
を除去して前記第２の高融点金属膜の一部を露出し第１
のスルーホールを開孔する工程と、前記第２の高融点金
属膜の露出部に第３の高融点金属膜を選択成長させ、前
記第１のスルーホールを充填する工程と、前記第２の絶
縁膜と第３の高融点金属膜上に第２の導体膜を形成後、
この第２の導体膜上に第４の高融点金属膜を被着し、前
記第２の導体膜および第４の高融点金属膜を所定パター
ンとなるよう選択除去し第２の配線層を形成する工程と
、第２の配線層上に第３の絶縁膜を表面が平坦化するよ
うに形成し、この第３の絶縁膜の所定箇所を除去して前
記第４の高融点金属膜の一部を露出して第２のスルーホ
ールを開孔する工程と、この第４の高融点金属膜の露出
部に第５の高融点金属膜を選択成長させ第２のスルーホ
ールを充填する工程とを含むことを特徴とする半導体装
置の製造方法。(3) A first insulating film is deposited on the main surface of a semiconductor substrate having a diffusion layer, a predetermined portion of the first insulating film is removed to expose a part of the diffusion layer, and a contact hole is opened. a step of forming a noble metal compound film on the diffusion layer exposed from the contact hole; and a step of selectively growing a first high melting point metal film only on the noble metal compound film to fill the contact hole. , after forming a first conductor film on the first insulating film and the first high-melting point metal film, forming a second high-melting point metal film on the first conductor film;
forming a first wiring layer by selectively removing the conductor film and the second high melting point metal film in a predetermined pattern; and forming a second wiring layer on the first wiring layer and the first insulating film. An insulating film is formed to have a flat surface, and a predetermined portion of the second insulating film is removed to expose a part of the second high melting point metal film.
a step of opening a through hole in the second refractory metal film; a step of selectively growing a third refractory metal film on the exposed portion of the second refractory metal film to fill the first through hole; After forming the second conductive film on the insulating film and the third high melting point metal film,
A fourth high melting point metal film is deposited on the second conductor film, and the second conductor film and the fourth high melting point metal film are selectively removed to form a predetermined pattern to form a second wiring layer. A third insulating film is formed on the second wiring layer so that the surface is flattened, and a predetermined portion of the third insulating film is removed to form one of the fourth high-melting point metal films. a step of opening a second through hole by exposing the fourth refractory metal film, and a step of selectively growing a fifth refractory metal film on the exposed portion of the fourth refractory metal film to fill the second through hole. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4536587A JPS63213359A (en) | 1987-03-02 | 1987-03-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4536587A JPS63213359A (en) | 1987-03-02 | 1987-03-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63213359A true JPS63213359A (en) | 1988-09-06 |
Family
ID=12717244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4536587A Pending JPS63213359A (en) | 1987-03-02 | 1987-03-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63213359A (en) |
-
1987
- 1987-03-02 JP JP4536587A patent/JPS63213359A/en active Pending
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