JPS63211768A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an insulating film having high breakdown strength for a leaking current even if the thickness of the film is made thin without increase in cost and decrease in reliability, by thermally oxidizing a second unsingle crystal silicon film, forming a silicon oxide film, and forming a conductor layer on the silicon oxide film. CONSTITUTION:Silicon oxide films 13 and 13 are formed as gate insulating films on the surface of a silicon substrate 11. Impurity ions are implanted in the surface of a channel region. Thereafter, a first polycrystalline silicon film 14 is formed on the entire surface of the substrate by an LPCVD method. Then phosphorus is implanted in the polycrystalline silicon film 14 at a concentration of about 3-5X10<12> cm<-3> by treatment in a POCl3 atmosphere. Then a resist pattern 15 is formed on the polycrystalline silicon film 14. With the resist pattern 15 as a mask, the polycrystalline silicon film 14 undergoes selective anisotropic etching, and a hole is formed. Then, the resist pattern 15 is removed, and a second polycrystalline silicon film 16 including phosphorus is formed on the surface of the polycrystalline silicon film 14 by an LPCVD method. Thus the surface of the substrate is covered with the polycrystalline silicon film 16. Then the entire silicon oxide film 16 is oxidized, and a polysilicon oxide film 17 is formed.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to an EFROM-? It is used in the manufacture of DRAM and the like.

(Prior Art) Generally, the technology of forming a silicon oxide film on non-single crystal silicon, for example, polycrystalline silicon, for example, EPROM (
Erasable Programmable Rea
dOnlyM@mory) to achieve a good electrical insulation film between the floating dirt and control dirt, or DRAM (Dynamic Ra
It is used to form a surface coating film for capacitor electrodes of ndom Ace (ssM/mory). Conventionally, a silicon oxide film with a thickness of several tens of nanometers formed by thermal oxidation has been used as such an insulating film, but as devices become faster and have larger capacities, There is a demand for a thinner film and less leakage current.

By the way, a silicon oxide film (hereinafter referred to as a polysilicon oxide film) formed on a polycrystalline silicon film by a thermal oxidation method
It is known that when the film thickness becomes approximately 30 nm or less, the leakage breakdown voltage (dielectric breakdown voltage) decreases. Regarding this, please refer to the Institute of Electrical Communication Engineers, Reliability Study Group Material R84.
-68, ``High Reliability Between Polysilicon Layers, Thin Film Insulating Film Formation Technology'' (March 1983).

This document states that it is not preferable to use a polysilicon oxide film as a thin insulating film of 40 nm or less in terms of leakage voltage, and that "oxide film/ It is stated that a three-layer structure film called "nitride film/oxide film" is preferable.

However, the three-layer structure film has the drawback that the number of manufacturing steps is increased compared to a single-layer film of polysilicon oxide film, resulting in higher costs. Another problem is that the silicon nitride film has many traps, and the accumulation and release of charges in these traps reduces the reliability of the device.

(Problems to be Solved by the Invention) As described above, in the conventional manufacturing method of semiconductor devices, when the insulating film is made thinner, the leakage withstand voltage decreases. There are drawbacks such as increased cost and decreased device reliability due to increased complexity.

This invention was made in view of the above circumstances,
The purpose is to provide a method for manufacturing a semiconductor device that can form an insulating film that has a high leakage breakdown voltage even when the film is thinned, without causing an increase in cost or a decrease in reliability.

[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in this invention, in order to achieve the above object, first a first non-single crystal silicon film is formed, and then the non-single crystal silicon film is formed. After doping the silicon film with impurities/performing mother turning,
A second non-single crystal silicon film is formed on the first non-single crystal silicon film, and the second non-single crystal silicon film is entirely oxidized to form a thin insulating film.

By doing this, damage layers, locally-containing areas containing a large amount of impurities, and surface irregularities generated on the surface of the first non-single crystal silicon film from formation to processing can be removed from the second non-single crystal silicon film. Since a thin insulating film is formed by coating with a crystalline silicon film and oxidizing this second non-single crystal silicon, the leakage breakdown voltage can be improved if the film thickness is the same as in the conventional case.

(Example) Hereinafter, an example of the present invention will be described in detail by taking the manufacture of an EFROM memory cell as an example.

Figure 1 (a) to (,) and Figure 2 (a), (b)
The manufacturing steps are sequentially shown. First, as shown in FIG. 1(a), a field insulating film 12 for element isolation of memory cells is formed on a P-type (100) silicon substrate 11.

Next, a silicon oxide film 13.13 with a thickness of 30 nm is formed as a dirt insulating film on the surface of the silicon substrate 1 in the element region separated by the field insulating film 12, and a threshold voltage control film 13.13 is formed directly on the surface of the channel region. Perform ion implantation of impurities for use.

After that, the entire surface of the substrate was coated with a thickness of 300 nm using the LPCVD method.
The first polycrystalline silicon film 14 is formed to a certain extent. At this time, no impurities are added to the reaction gas. Next, 900℃
The polycrystalline silicon film 14 is treated in a pot atmosphere for about 30 minutes to introduce phosphorus into the polycrystalline silicon film 14 at a concentration of about 3 to 5×10 cm. Next, a part of the polycrystalline silicon film 14 on the field insulating film 12 is removed, and a normal photolithography process is performed to form a floating tart of the memory cell. That is, a resist pattern 15 is formed on the polycrystalline silicon film 14, and the first polycrystalline silicon film 14 is selectively anisotropically etched using the resist z4' turn 15 as a mask to form an opening. (See Figure 1(b)). At this time, the field insulating film 12 is also etched by several tens of nanometers.

Next, after removing the resist pattern 15 and cleaning the surface of the polycrystalline silicon film 140, 3 to 5×10 phosphorus is removed.
The second polycrystalline silicon film 16 containing about cW1 is LP
It is formed to a thickness of about 12 nm using the CVD method.

As a result, the entire surface of the substrate is covered with the second polycrystalline silicon film 16, as shown in FIG.

Since this polycrystalline silicon film 16 is doped with phosphorus in the deposition process, it is possible to dope phosphorus uniformly into the polycrystalline silicon, compared to the polycrystalline silicon film 14 formed by diffusion using POCt. be.

Next, the second silicon oxide film 16 is completely oxidized in an O2 atmosphere diluted to 10% to form a polysilicon oxide film 17 as shown in FIG. 1(d).

At this time, the oxidation temperature is set to 1000° C. or higher to prevent the shape of the oxide film at the corners and between the polycrystalline silicon duplexes from deteriorating due to stress during oxidation.

In this way, a film thickness of 25 mm is formed on the polycrystalline silicon film 14.
A polysilicon oxide film 17 is formed.

After that, as shown in FIG. 1(,), a third polycrystalline silicon film 18 with a thickness of about 350 nm is formed on the entire surface of the substrate by the LPCVD method, and this polycrystalline silicon film 18 is formed by diffusion using POC3. 18 is doped with phosphorus.

Next, the polycrystalline silicon film 18 is patterned by anisotropic etching to form word lines of the EPROM. The first polycrystalline silicon film 14 is also anisotropically etched in the same pattern. Figure 1 in this state (,)
A cross-sectional view taken along the line A-A' is shown in FIG. 2 (, ).

Next, as shown in FIG. 2(b), an NFI diffusion layer 19A that becomes the source and drain of the memory cell transistor.

After forming 19B, the entire surface of the substrate is oxidized to form floating dirt 14' and word line 18' with silicon oxide film 20.
Cover with

Thereafter, a silicon oxide film and a PSG film for surface protection are deposited over the entire surface of the substrate, contact holes are selectively opened, and AA wiring is formed to complete an EPROM memory cell.

According to such a manufacturing method, the second polycrystalline silicon film 16 formed on the surface of the first polycrystalline silicon film 14
The surface is stable without any damage layer caused by processing, and since it uses doped polysilicon that is doped with impurities during deposition, abnormal processing at grain boundaries of polycrystalline silicon is avoided. It is possible to prevent the formation of a high phosphorus concentration portion due to contamination, and it is possible to maintain a low phosphorus concentration in the first polycrystalline silicon film as a whole. Therefore, even if the polysilicon oxide film 17 formed by thermally oxidizing the polycrystalline silicon film 16 is made thinner, a high leakage breakdown voltage can be obtained. Therefore, a polysilicon oxide film with a thickness of 25 mm can be used as the insulating film between the floating gate and the control gate. The above-mentioned manufacturing process is simpler than the conventional three-layer structure film, and the cost can be lowered compared to the three-layer structure film.Since no nitride film is used, there are no problems such as traps, and it is highly reliable. is obtained.

In order to confirm the effects of this invention, a 10m long capacitor was formed using the manufacturing process described above, and the leakage voltage was measured, and it was found that the leakage voltage was as high as 5.5 MY/cm (measured value of 50 pieces). Obtained. Also, 0 to 4 MY/-
So-called B-mode failure (for example, due to the presence of impurities)
There are extremely few defective defects such as a partial decrease in the breakdown voltage of the oxide film, a decrease in the breakdown voltage due to the partially thin oxide film, etc.) and A-mode defects (short circuits).
(less than 1 out of 50), even a polysilicon oxide film with a film thickness of 25 nm can be used for mega-pit class memories.

[Effects of the Invention] As explained above, according to the present invention, a method for manufacturing a semiconductor device is provided that can form an insulating film that has a high leakage breakdown voltage even when the film is thinned, without causing an increase in cost or a decrease in reliability. It will be done.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, respectively. 14...First polycrystalline silicon film (first non-single crystal silicon film), 16...Second polycrystalline silicon film (second
(non-monocrystalline silicon film), 17... polysilicon oxide film (oxide film), 18... third polycrystalline silicon film (inscription layer). Applicant's agent Patent attorney Suzue Takehiko A' 1st cause 18゛

Claims (2)

[Claims] (1) A step of forming a first non-single-crystal silicon film, a step of forming a second non-single-crystal silicon film containing impurities on the first non-single-crystal silicon film, and a step of forming the second non-single-crystal silicon film containing impurities. 1. A method of manufacturing a semiconductor device, comprising the steps of thermally oxidizing a non-single crystal silicon film to form a silicon oxide film, and forming a conductive layer on the silicon oxide film. (2) The semiconductor device according to claim 1, wherein the impurity concentration in the second non-single crystal silicon film is lower than the impurity concentration in the first non-single crystal silicon film. Production method.