JPS63209307A - Voltage controlled piezoelectric oscillation circuit - Google Patents
Voltage controlled piezoelectric oscillation circuitInfo
- Publication number
- JPS63209307A JPS63209307A JP62044311A JP4431187A JPS63209307A JP S63209307 A JPS63209307 A JP S63209307A JP 62044311 A JP62044311 A JP 62044311A JP 4431187 A JP4431187 A JP 4431187A JP S63209307 A JPS63209307 A JP S63209307A
- Authority
- JP
- Japan
- Prior art keywords
- applied voltage
- circuit
- voltage
- digital
- externally applied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 16
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract 2
- 230000003068 static effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電圧制御型圧電発振回路に関し、特に可変容
量素子の静電容量を外部印加電圧の大きさに応じて制御
することにより圧電発振回路の発振周波数を変化させる
様にした電圧制御型圧電発振回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a voltage-controlled piezoelectric oscillator circuit, and particularly to a piezoelectric oscillator circuit that generates piezoelectric oscillation by controlling the capacitance of a variable capacitance element according to the magnitude of an externally applied voltage. This invention relates to a voltage-controlled piezoelectric oscillator circuit that changes the oscillation frequency of the circuit.
従来のこの種の電圧制御型圧電発振回路は、第4図に回
路構成を示す如く、圧電発振回路の発振周波数を制御す
る為の外部印加電圧が抵抗器R3を介して可変容量素子
2に印加される構成となっており、外部印加電圧値に応
じて可変容量素子2の静電容量を変化させて、圧電発振
回路の発振周波数を制御している。In a conventional voltage-controlled piezoelectric oscillator circuit of this type, as shown in the circuit configuration in FIG. The oscillation frequency of the piezoelectric oscillation circuit is controlled by changing the capacitance of the variable capacitance element 2 according to the externally applied voltage value.
上述した従来の電圧制御型圧電発振回路は、外部印加電
圧値に対する発振周波数の変化特性が第3図に示す様な
可変容量素子2に固有の印加電圧−静電容量特性によっ
て決定される為、第5図に示す様な非直線部分のある外
部印加電圧−発振周波数特性しか得られず、例えば外部
印加電圧に比例した発振周波数変化を必要とする用途に
は不適であるという欠点がある。In the conventional voltage-controlled piezoelectric oscillator circuit described above, the change characteristics of the oscillation frequency with respect to the externally applied voltage value are determined by the applied voltage-capacitance characteristics specific to the variable capacitance element 2 as shown in FIG. This method has the disadvantage that only an externally applied voltage--oscillation frequency characteristic with a non-linear portion as shown in FIG. 5 can be obtained, making it unsuitable for applications requiring, for example, a change in oscillation frequency proportional to the externally applied voltage.
本発明の電圧制御型圧電発振回路は、外部からの印加電
圧値に応じて静電容量が変化する可変容量素子と圧電共
振子とを含む電圧制御型圧電発振回路において、前記印
加電圧値をディジタルコード化するディジタル・アナロ
グ変換器と、該アナログ・ディジタル変換器の出力ディ
ジタルコードにより指定されたアドレスに対応した電圧
補償ディジタルコードを記憶するメモリ回路と、該メモ
リ回路の出力ディジタルコードをアナログ信号化するデ
ィジタル・アナログ変換器とを備え、該ディジタル・ア
ナログ変換器の出力信号を前記可変容量素子に印加して
前記静電容量を変化させるよう構成しである。The voltage-controlled piezoelectric oscillator circuit of the present invention includes a variable capacitance element and a piezoelectric resonator whose capacitance changes according to an externally applied voltage value. A digital-to-analog converter for encoding, a memory circuit for storing a voltage compensation digital code corresponding to an address specified by the output digital code of the analog-to-digital converter, and a memory circuit for converting the output digital code of the memory circuit into an analog signal. and a digital-to-analog converter, and is configured to apply an output signal of the digital-to-analog converter to the variable capacitance element to change the capacitance.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.
同図において、外部印加電圧はアナログ・ディジタル変
換器3により一旦ディジタルコードに変換される。アナ
ログ・ディジタル変換器3の出力ディジタルコードは、
メモリ回路4に供給される。In the figure, an externally applied voltage is once converted into a digital code by an analog/digital converter 3. The output digital code of analog-to-digital converter 3 is
The signal is supplied to the memory circuit 4.
メモリ回路4には、外部印加電圧値による発振周波数の
変化を制御するために、電圧値を示すアドレス信号であ
るディジタルコードに対応した電圧制御ディジタルコー
ドをあらかじめ記憶させておく。外部電圧値が変化する
とアドレス信号も変化し、これに応じてメモリ回路4か
ら電圧制御ディジタルコードが読み出される。この読み
出された電圧制御ディジタルコードは、ディジタル・ア
ナログ変換器5に供給されてアナログ信号に変換された
あと、抵抗器R3を介して可変容量素子2に供給され、
可変容量素子2の静電容量値を制御する。この容量値制
御によって、圧電共振子1、トランジスタQ、抵抗器R
1〜R7、およびコンデンサC□〜C4から成る圧電発
振回路の発振周波数が制御される。In order to control changes in oscillation frequency due to externally applied voltage values, the memory circuit 4 stores in advance a voltage control digital code corresponding to a digital code that is an address signal indicating a voltage value. When the external voltage value changes, the address signal also changes, and the voltage control digital code is read out from the memory circuit 4 accordingly. This read voltage control digital code is supplied to the digital-to-analog converter 5 and converted into an analog signal, and then supplied to the variable capacitance element 2 via the resistor R3.
The capacitance value of the variable capacitance element 2 is controlled. Through this capacitance value control, piezoelectric resonator 1, transistor Q, resistor R
The oscillation frequency of the piezoelectric oscillation circuit made up of capacitors C□ to C4 is controlled.
本実施例では、メモリ回路4に記憶させる電圧制御ディ
ジタルコードの設定値を変えることにより、所望の外部
印加電圧−発振周波数特性を得ることができ、第2図に
例示するような直線特性を容易に実現できる。In this embodiment, by changing the set value of the voltage control digital code stored in the memory circuit 4, a desired externally applied voltage-oscillation frequency characteristic can be obtained, and a linear characteristic as illustrated in FIG. 2 can be easily obtained. can be realized.
以上説明したように本発明は、外部印加電圧を一旦ディ
ジタルコード化した後、再びアナログ信号に変換する構
成としている為、アナログ・ディジタル変換率及びディ
ジタル・アナログ変換率の設定値により外部印加電圧値
に対する発振周波数特性を任意に設定することができ、
例えば第2図に示すような直線性の良い外部印化電圧−
発振周波数特性を得ることができるという効果がある。As explained above, the present invention has a configuration in which the externally applied voltage is once converted into a digital code and then converted back into an analog signal. The oscillation frequency characteristics can be set arbitrarily,
For example, an externally applied voltage with good linearity as shown in Figure 2.
This has the effect that oscillation frequency characteristics can be obtained.
第1図は本発明の一実施例を示す回路図、第2図は本発
明による外部印化電圧−発振周波数特性を例示する特性
図、第3図は可変容量素子のもつ印加電圧−静電容量特
性例を示す特性図、第4図は従来の回路構成図、第5図
は従来回路構成による外部印加電圧−発振周波数特性を
例示する特性図である。
1・・・圧電共振子、2・・・可変容量素子、R1−R
7・・・抵抗器、01〜C4・・・コンデンサ、Q・・
・トランジスタ、3・・・アナログ・ディジタル変換器
、4・・・メモリ回路、5・・・ディジタル・アナログ
変換器。
一〒’6− ’FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram illustrating externally applied voltage-oscillation frequency characteristics according to the present invention, and FIG. 3 is an applied voltage-electrostatic voltage characteristic of a variable capacitance element. FIG. 4 is a characteristic diagram showing an example of capacitance characteristics, FIG. 4 is a conventional circuit configuration diagram, and FIG. 5 is a characteristic diagram illustrating an externally applied voltage-oscillation frequency characteristic according to the conventional circuit configuration. 1... Piezoelectric resonator, 2... Variable capacitance element, R1-R
7...Resistor, 01-C4...Capacitor, Q...
- Transistor, 3... Analog-digital converter, 4... Memory circuit, 5... Digital-analog converter. 1〒'6-'
Claims (1)
容量素子と圧電共振子とを含む電圧制御型圧電発振回路
において、前記印加電圧値をディジタルコード化するア
ナログ・ディジタル変換器と、該アナログ・ディジタル
変換器の出力ディジタルコードにより指定されたアドレ
スに対応した電圧補償ディジタルコードを記憶するメモ
リ回路と、該メモリ回路の出力ディジタルコードをアナ
ログ信号化するディジタル・アナログ変換器とを備え、
該ディジタル・アナログ変換器の出力信号を前記可変容
量素子に印加して前記静電容量を変化させる電圧制御型
圧電発振回路。In a voltage-controlled piezoelectric oscillator circuit including a variable capacitance element and a piezoelectric resonator that change capacitance according to an externally applied voltage value, an analog-to-digital converter that converts the applied voltage value into a digital code; comprising a memory circuit that stores a voltage compensation digital code corresponding to an address specified by the output digital code of the analog-to-digital converter, and a digital-to-analog converter that converts the output digital code of the memory circuit into an analog signal,
A voltage-controlled piezoelectric oscillation circuit that applies an output signal of the digital-to-analog converter to the variable capacitance element to change the capacitance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62044311A JPS63209307A (en) | 1987-02-26 | 1987-02-26 | Voltage controlled piezoelectric oscillation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62044311A JPS63209307A (en) | 1987-02-26 | 1987-02-26 | Voltage controlled piezoelectric oscillation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63209307A true JPS63209307A (en) | 1988-08-30 |
Family
ID=12687943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62044311A Pending JPS63209307A (en) | 1987-02-26 | 1987-02-26 | Voltage controlled piezoelectric oscillation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63209307A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02128432U (en) * | 1989-03-29 | 1990-10-23 | ||
JPH0314318A (en) * | 1989-06-13 | 1991-01-23 | Japan Radio Co Ltd | Linearlizer circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57132406A (en) * | 1981-02-09 | 1982-08-16 | Nippon Telegr & Teleph Corp <Ntt> | Digital control type piezoelectric oscillating circuit |
-
1987
- 1987-02-26 JP JP62044311A patent/JPS63209307A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57132406A (en) * | 1981-02-09 | 1982-08-16 | Nippon Telegr & Teleph Corp <Ntt> | Digital control type piezoelectric oscillating circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02128432U (en) * | 1989-03-29 | 1990-10-23 | ||
JPH0314318A (en) * | 1989-06-13 | 1991-01-23 | Japan Radio Co Ltd | Linearlizer circuit |
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