JPS63207283A - Stripe effect circuit - Google Patents

Stripe effect circuit

Info

Publication number
JPS63207283A
JPS63207283A JP3949987A JP3949987A JPS63207283A JP S63207283 A JPS63207283 A JP S63207283A JP 3949987 A JP3949987 A JP 3949987A JP 3949987 A JP3949987 A JP 3949987A JP S63207283 A JPS63207283 A JP S63207283A
Authority
JP
Japan
Prior art keywords
image
horizontal
latches
data
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3949987A
Other languages
Japanese (ja)
Inventor
Toshiharu Yamashita
山下 敏治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3949987A priority Critical patent/JPS63207283A/en
Publication of JPS63207283A publication Critical patent/JPS63207283A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To interchange band-shaped pictures by providing at least one counter for memory address, at least two latches where data is held, and at least two comparators which compare the value of the counter for memory address with the contents of latches. CONSTITUTION:Data on a data bus B from a CPU is inputted to latches 7-10 to assign them as I/Os or the like of the CPU, and a strobe signal (STRB) is given by an 1/O write instruction or the like of the CPU to hold data H1-H4 in latches 7-10 independently of one another. Gate circuits 11-13 output a horizontal direction key signal S. If the key signal S outputs an image by logical '1' and masks the image by logical '0', a vertical band-shaped image is obtained. Values of data H1-H4 are changed to change bands of an image area. With respect to the vertical direction of the image, a horizontal band- shaped image is obtained by the same method. Further, a lattice-shaped image is obtained by AND between horizontal-direction and vertical-direction key signals.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テレビジョンにおけるディジタルビデオ効実
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital video effects device in television.

〔従来の技術〕[Conventional technology]

従来、この種のキー信号発生回路は画面の縁を境界とし
その内部で一様に出力されるようになっていた。
Conventionally, this type of key signal generating circuit has been designed to output uniformly within the edge of the screen as its boundary.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のキー信号発生回路では、画面の中は絵が
連続的に出ていることになり、縦方向。
In the conventional key signal generation circuit described above, the picture appears continuously on the screen, vertically.

横方向の帯又は長方形により画面を交換するような効果
を得ることができない。
It is not possible to obtain the effect of replacing the screen with horizontal bands or rectangles.

本発明の目的は帯状に画面の入替を行うことができるス
トライプ効果回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a stripe effect circuit that can replace screens in a strip-like manner.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のストライプ効果回路は水平方向、垂直方向の少
なくとも一方のメモリアドレス用の少なくとも1個のカ
ウンタと、データを保持する少なくとも2個のラッチと
、前記メモリアドレスのカウンタの値と前記ラッチの内
容とを比較する少なくとも2個のコンパレータとを有す
ることを特徴とするものである。
The stripe effect circuit of the present invention includes at least one counter for a memory address in at least one of a horizontal direction and a vertical direction, at least two latches for holding data, and the value of the counter of the memory address and the contents of the latch. and at least two comparators for comparing the two.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すものであり、本実施例
は水平方向のキー信号発生回路を対象とするものである
6第1図において、1は水平方向のメモリアドレス用カ
ウンタで、複数のビットのデータを保有する。2〜6は
複数のビットからなる2つの入力A、Bを比較するコン
パレータであり、入力A、Hの大小関係により、A>B
、A<Bの信号を出力する。7〜10はラッチで、図示
しないcPUからのデータバスBを入力とし、CPUの
Ilo等として割り付け、CPUのI10ライト命令等
によりストローブ信号(STRB)を与え各ラッチ7〜
10に独立にデータ旧〜H4を保持させる。11〜13
はゲート回路で、水平方向のキー信号Sを出力する。
FIG. 1 shows an embodiment of the present invention, and this embodiment is intended for a horizontal key signal generation circuit.6 In FIG. 1, 1 is a horizontal memory address counter. , holds multiple bits of data. 2 to 6 are comparators that compare two inputs A and B consisting of multiple bits, and due to the magnitude relationship of inputs A and H, A>B
, outputs a signal where A<B. Numerals 7 to 10 are latches, which input data bus B from the cPU (not shown), are allocated as Ilo, etc. of the CPU, and are given a strobe signal (STRB) by the CPU's I10 write command, etc. to each latch 7 to 10.
10 to independently hold data old to H4. 11-13
is a gate circuit which outputs a horizontal key signal S.

水平方向のメモリアドレスカウンタ1は、水平の映像期
間の始めから終わりにかけて変化する。
The horizontal memory address counter 1 changes from the beginning to the end of the horizontal video period.

例えば、0から3FF(16進数、H)まで変化する。For example, it changes from 0 to 3FF (hexadecimal number, H).

3 FFHを水平アドレスの最大値HM A Xと呼ぶ
ことにし、 0<Hl<H2<H3<H4<HMAXとすれば、コン
パレータ2のA<B出力、コンパレータ3のA>B出力
、コンパレータ4のA<B出力、コンパレータ5のA>
B出力及びコンパレータ6のA<B出力は第2図に示す
ようになる。
3 Let FFH be called the maximum horizontal address value HMA A<B output, A of comparator 5>
The B output and the A<B output of the comparator 6 are as shown in FIG.

従って、コンパレータ3と4の出力のANDの出力11
と、コンパレータ5と6のANDの出力12は第2図に
示すようになる。コンパレータ2のA<B出力と、出力
11.12のOR出力13は第2図のように得られ、水
平キー信号Sが得られる。このキー信号Sは論理′1′
の部分で映像を出力し、′″0″′の部分で映像をマス
クすることにすれば第3図に示すような映像が得られる
。ここで白い部分Wが映像の出ている領域で、斜線部B
が映像がマスクされている領域である。旧〜H4の値を
変化させることにより映像の領域の帯を変えることがで
きる。映像の垂直方向でも同様な方法により第4図のよ
うな映像が得られる。さらに水平、垂直方向のキー信号
のANDをとることにより第5図のような映像も得られ
る。
Therefore, the output 11 of the AND of the outputs of comparators 3 and 4
The output 12 of the AND of the comparators 5 and 6 is as shown in FIG. The A<B output of the comparator 2 and the OR output 13 of the outputs 11 and 12 are obtained as shown in FIG. 2, and a horizontal key signal S is obtained. This key signal S is logic '1'
If the image is output at the portion ``0'' and the image is masked at the portion ``0'', an image as shown in FIG. 3 will be obtained. Here, the white part W is the area where the image appears, and the shaded part B
is the area where the image is masked. By changing the values of old to H4, the band of the video area can be changed. An image as shown in FIG. 4 can be obtained by a similar method in the vertical direction of the image. Further, by ANDing the horizontal and vertical key signals, an image as shown in FIG. 5 can be obtained.

尚、実施例では水平方向のメモリアドレスカウンタのみ
を用いたが、垂直方向のメモリアドレスカウンタをもつ
垂直方向のキー信号発生回路に適用してもよく、さらに
は水平及び垂直方向のメモリアドレスカウンタをもつキ
ー信号発生回路に適用してもよい。
Although only a horizontal memory address counter is used in the embodiment, it may be applied to a vertical key signal generation circuit having a vertical memory address counter, or even a horizontal and vertical memory address counter. The present invention may also be applied to a key signal generation circuit having a key signal generation circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は帯状のキー信号を発生させ
るため、映像の場面転換などに用いることにより帯状に
画面を入れ替えることができる効果を有するものである
As explained above, since the present invention generates a band-shaped key signal, it has the effect of being able to change the screen in a band-like manner by using it for changing the scene of a video.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す構成図、第2図は第1
図の各部の波形と最終出力である水平方向のキーの出力
を示す図、第3図は第1図の回路により得られた映像の
例を示す図、第4図は第1図の回路と同様な方法を垂直
方向のキーに応用した場合の映像の例を示す図、第5図
は第3図及び第4図に示した水平及び垂直方向のキー信
号のORをとることにより得られるキー信号により得ら
れた映像の例を示す図である。 1・・・水平方向のメモリアドレスカウンタ、2〜6・
・・2人力のコンパレータ、7〜lO・・・ラッチ、1
1〜13・・・ゲート回路
FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
Figure 3 shows an example of the image obtained by the circuit in Figure 1. Figure 4 shows the circuit in Figure 1 and the output of the horizontal key which is the final output. A diagram showing an example of an image when a similar method is applied to a vertical key. Figure 5 is a key obtained by ORing the horizontal and vertical key signals shown in Figures 3 and 4. FIG. 3 is a diagram showing an example of a video obtained from a signal. 1...Horizontal memory address counter, 2 to 6.
・2-man power comparator, 7~lO...latch, 1
1 to 13...gate circuit

Claims (1)

【特許請求の範囲】[Claims] (1)ビデオのキー信号の発生回路において、水平方向
、垂直方向の少なくとも一方のメモリアドレス用の少な
くとも1個のカウンタと、データを保持する少なくとも
2個のラッチと、前記メモリアドレスのカウンタの値と
前記ラッチの内容を比較する少なくとも2個のコンパレ
ータとを有することを特徴とするストライプ効果回路。
(1) A video key signal generation circuit includes at least one counter for a memory address in at least one of the horizontal and vertical directions, at least two latches that hold data, and the value of the counter at the memory address. and at least two comparators for comparing the contents of the latches.
JP3949987A 1987-02-23 1987-02-23 Stripe effect circuit Pending JPS63207283A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3949987A JPS63207283A (en) 1987-02-23 1987-02-23 Stripe effect circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3949987A JPS63207283A (en) 1987-02-23 1987-02-23 Stripe effect circuit

Publications (1)

Publication Number Publication Date
JPS63207283A true JPS63207283A (en) 1988-08-26

Family

ID=12554739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3949987A Pending JPS63207283A (en) 1987-02-23 1987-02-23 Stripe effect circuit

Country Status (1)

Country Link
JP (1) JPS63207283A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205891A (en) * 1989-02-03 1990-08-15 Mitsubishi Electric Corp Picture display control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205891A (en) * 1989-02-03 1990-08-15 Mitsubishi Electric Corp Picture display control circuit

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