JPS63207125A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS63207125A
JPS63207125A JP3925287A JP3925287A JPS63207125A JP S63207125 A JPS63207125 A JP S63207125A JP 3925287 A JP3925287 A JP 3925287A JP 3925287 A JP3925287 A JP 3925287A JP S63207125 A JPS63207125 A JP S63207125A
Authority
JP
Japan
Prior art keywords
wafer
silicon
temperature
polycrystalline silicon
additive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3925287A
Other languages
Japanese (ja)
Inventor
Atsushi Nomura
淳 野村
Hiroshi Tetsuda
鉄田 博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3925287A priority Critical patent/JPS63207125A/en
Publication of JPS63207125A publication Critical patent/JPS63207125A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To prevent the end of a silicon wafer from slipping by heat-treating with a lamp the wafer in a state that an undoped polycrystalline silicon is selectively deposited on the front or rear surface of a semiconductor substrate. CONSTITUTION:An undoped polycrystalline silicon 12 is deposited on the rear surface of a silicon wafer 11. Then, the silicon 12 is coated with a resist, patterned, and the silicon 12 is etched with the resist pattern 13 as a mark, thereby allowing the silicon 12 to remain only on a region several mm at the end of the rear surface of the wafer 11. Further, after the pattern 13 is removed, an annealing light 14 is irradiated to the wafer 11 to be heat treated with a lamp in a state that the silicon 12 remains on the end of the rear surface of the wafer 11. Thus, the temperature of the end rises due to the deposition of the silicon 12, and the temperature of the wafer 11 wholly becomes uniform. In this manner, it can prevent the end of the wafer 11 from slipping.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体素子の製造方法に係り、特にランプに
よる短時間高温熱処理方法(RTA : RapidT
hermal Anneal ) K関するもノテある
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing semiconductor devices, and particularly to a short-time high-temperature heat treatment method (RTA: RapidT) using a lamp.
There are also notes regarding K.

(従来の技術) 半導体素子の製造工程において、イオン注入層のアニー
ル、PSGフローなどの高温の熱処理は、従来、電気炉
を用いて行われてきた。しかし、最近、短時間の熱処理
方法として、タングステン八日rンランプやアークラン
プなどを用いたRTA(Rapid Thermal 
Anneal )法が開発され実用化されようとしてい
る。
(Prior Art) In the manufacturing process of semiconductor devices, high-temperature heat treatments such as annealing of ion-implanted layers and PSG flow have conventionally been performed using an electric furnace. However, recently, as a short-time heat treatment method, RTA (Rapid Thermal Treatment) using a tungsten lamp or an arc lamp has been developed.
Anneal) method has been developed and is about to be put into practical use.

RTA装置の概略断面図を第5図に示す。この第5図は
半導体ウェハの両面加熱型の装置を示したものであるが
、他にランプが片側だけ゛にある装置もある。
A schematic cross-sectional view of the RTA device is shown in FIG. Although FIG. 5 shows a device for heating semiconductor wafers on both sides, there are other devices that have lamps on only one side.

第5図において、1は半導体ウェハ、2は石英チューブ
、3はタングステンハロダンランプ、4はミラー、5は
パイロメータである。
In FIG. 5, 1 is a semiconductor wafer, 2 is a quartz tube, 3 is a tungsten-halodan lamp, 4 is a mirror, and 5 is a pyrometer.

この装置において、ランプ3より放射された光は、一部
は、石英チューブ2を通して半導体ウェハ1に照射され
、他はウェハlの反対側に照射され、ミラー4で反射さ
れた後、石英チューブ2を通して半導体ウェハlに照射
される。半導体ウェハlでは、照射された光はウェハ1
に一部が吸収される。他はウェハlで反射され、もしく
はウニ ゛ハ1を透過し、再びミラー4へ戻り、多重反
射が繰り返えされる。その結果、ウェハlの温度が短時
間で上昇し、熱処理が行われることになる。上昇したウ
ェハ1の温度はパイロメータ5もしくは図示しない熱電
対を直接半導体ウェハ1に接触させることにより測定さ
れ、測定された温度をランプ3の入力にフィードバック
することにより、熱処理温度が制御される。
In this device, part of the light emitted from the lamp 3 is irradiated onto the semiconductor wafer 1 through the quartz tube 2, and the other part is irradiated onto the opposite side of the wafer l, and after being reflected by the mirror 4, the light is emitted from the quartz tube 2. The semiconductor wafer l is irradiated through the beam. On semiconductor wafer l, the irradiated light is on wafer 1.
Some of it is absorbed into. The remaining light is reflected by the wafer 1 or transmitted through the wafer 1, returns to the mirror 4, and multiple reflections are repeated. As a result, the temperature of the wafer I rises in a short time, and heat treatment is performed. The increased temperature of the wafer 1 is measured by bringing a pyrometer 5 or a thermocouple (not shown) into direct contact with the semiconductor wafer 1, and the heat treatment temperature is controlled by feeding back the measured temperature to the input of the lamp 3.

(発明が解決しようとする問題点) しかしながら、上記のRTA装置では、熱処理が秒の単
位のオーダーであることから、ウェハ1内での温度の均
一性を得ることが難しい。特に、熱処理を行うウェハ1
の端部においては、第6図に示すごとく光の入射(実線
矢印で示す)が殆ど無いため、相対的に光の放射−址(
点線矢印で示す)が多くなり、ウェハl端部の温度はウ
ェハ1中心に比較し低温となる。さらに、ウェハlを支
持する図示しない石英ビンが端部に接触する場合、熱伝
導のため更に低温となり、その結果ウェハ1端部にスリ
ップ(結晶欠陥)が発生する。
(Problems to be Solved by the Invention) However, in the RTA apparatus described above, it is difficult to obtain temperature uniformity within the wafer 1 because the heat treatment is on the order of seconds. In particular, wafer 1 to be subjected to heat treatment.
As shown in Figure 6, there is almost no light incident (indicated by the solid arrow) at the end of the
(indicated by a dotted line arrow) increases, and the temperature at the end of the wafer 1 becomes lower than that at the center of the wafer 1. Further, when a quartz bottle (not shown) that supports the wafer 1 comes into contact with the end, the temperature becomes even lower due to heat conduction, and as a result, slips (crystal defects) occur at the end of the wafer 1.

この温度の不均一性を改良するため、第5図のミラー4
の反射率をウェハ1端部に対応子る部分で大きくするこ
とにより、ウェハ1の端部での光の入射量を増す方法、
またはウェハ1支持部をヒーター入シの石英リング状に
する方法などがあった。しかし、いずれの方法もウェハ
径の変更に対してミラー4′またはリング状ヒーターを
交換することが必要となる。また、ウェハ1の大口径化
に対して、このような方法では光分にスリップの発生を
防止することができなかった。
In order to improve this temperature non-uniformity, mirror 4 in FIG.
A method of increasing the amount of light incident on the edge of the wafer 1 by increasing the reflectance of the area corresponding to the edge of the wafer 1,
Alternatively, there is a method in which the wafer 1 support part is shaped like a quartz ring with a heater. However, in either method, it is necessary to replace the mirror 4' or the ring-shaped heater when changing the wafer diameter. Further, as the diameter of the wafer 1 increases, this method cannot prevent slippage in the light beam.

この発明は上記の点に鑑みなされたもので、その目的は
、ランプ熱処理工程に2いて半導体ウェハの全体から、
或いはスリップを発生をウェハ端部のみに限定してウェ
ハの有効領域からスリップの発生を防止することのでき
る半導体素子の製造方法を提供することにある。
This invention was made in view of the above points, and its purpose is to remove the entire semiconductor wafer from the entire semiconductor wafer during the lamp heat treatment process.
Another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent slip from occurring in the effective area of the wafer by limiting the occurrence of slip to only the edge of the wafer.

(問題点を解決するための手段) この発明では、半導体基板の表面または裏面に選択的に
無添加多結晶シリコンを堆積させた状態でランプによる
熱処理を実施する。
(Means for Solving the Problems) In the present invention, heat treatment using a lamp is carried out in a state where additive-free polycrystalline silicon is selectively deposited on the front or back surface of a semiconductor substrate.

(作用) 半導体ウェハ(半導体基板)の例えば底面上に無添加多
結晶シリコンを堆積させ、このウェハにランプ熱処理(
RTA )を行うと、RTA中のウェハの温度は、多結
晶シリコンを堆積させていないウェハと比較し異なった
値を示す。第4図はシリコンウェハに形成した3i02
上に無添加多結晶シリコンを1100n または500
nm堆積(デポジション〕させた後RTAを行った時の
シリコンウェハの温度をウェハ裏面よりパイロメータで
測定した結果を示す。縦軸は、多結晶シリコンを堆積さ
せていないウェハの温度との差を示し、横軸は、各設定
RTA@度である。この時、無添加多結晶シリコンを堆
積させたシリコンウェハでは、20℃〜40℃程度(5
00nmの場合)堆積させていないウェハよりも温度が
高くなる。したがって、上記この発明のように無添加多
結晶シリコンを選択的に堆積させることにより、シリコ
ンウェハの温度制御が可能となる。いま、無添加多結晶
シリコンを、シリコンウェハの端部に堆積させれば、こ
の端部の温度を上げることができ、その結果、ウェハの
温度を全体均一にすることができ、ウェハの全体からス
リップの発生を防止できる。−万、シリコンウェハに、
端部を除いて無添加多結晶シリコンを堆積させれば、端
部とその他で急激な@夏着がつくようになり、その結果
、スリップの発生は端部のみに限定され、ウェハの有効
領域からはスリップの発生は見られなくなる。
(Function) Additive-free polycrystalline silicon is deposited, for example, on the bottom surface of a semiconductor wafer (semiconductor substrate), and this wafer is subjected to lamp heat treatment (
When performing RTA), the temperature of the wafer during RTA exhibits a different value compared to a wafer without polycrystalline silicon deposited. Figure 4 shows 3i02 formed on a silicon wafer.
Additive-free polycrystalline silicon on top of 1100n or 500n
The results show the temperature of a silicon wafer measured from the backside of the wafer using a pyrometer when RTA was performed after nm deposition.The vertical axis shows the difference in temperature from the temperature of a wafer on which polycrystalline silicon was not deposited. The horizontal axis is each setting RTA@degree. At this time, for a silicon wafer on which additive-free polycrystalline silicon is deposited, the temperature is about 20°C to 40°C (5
00 nm) The temperature is higher than that of a wafer without deposition. Therefore, by selectively depositing additive-free polycrystalline silicon as in the present invention, it becomes possible to control the temperature of the silicon wafer. Now, if additive-free polycrystalline silicon is deposited on the edge of a silicon wafer, the temperature of this edge can be raised, and as a result, the temperature of the entire wafer can be made uniform, and the temperature of the entire wafer can be increased. It is possible to prevent the occurrence of slips. -10,000 silicon wafers,
If additive-free polycrystalline silicon is deposited except for the edges, a sudden drop will occur at the edges and other parts, and as a result, the occurrence of slip will be limited to the edges, and the effective area of the wafer will be From then on, no slips were observed.

(実施例) 以下この発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図はこの発明の第1の実施例を示す工程断面図であ
る。この図の(a)において、11はシリコンウェハで
あり、このシリコンウェハ11の裏面に無添加多結晶シ
リコン12を1100n〜500nm堆積させる。
FIG. 1 is a process sectional view showing a first embodiment of the present invention. In (a) of this figure, 11 is a silicon wafer, and doped-free polycrystalline silicon 12 is deposited on the back surface of this silicon wafer 11 to a thickness of 1100 nm to 500 nm.

その後、無添加多結晶シリコン12上にレジストを塗布
し、ノ9ターン化し、そのレジストパターン13をマス
クとして無添加多結晶シリコン12をエツチングするこ
とにより、この多結晶シリコン12を第1図(b)に示
すようにシリコンウェハ11の裏面端部数minの領域
にのみ残す。
Thereafter, a resist is applied onto the additive-free polycrystalline silicon 12, and the additive-free polycrystalline silicon 12 is etched using the resist pattern 13 as a mask. ), it is left only in an area of a few minutes at the end of the back surface of the silicon wafer 11.

その後、レジスト・9ターフ13を除去した後、ウェハ
11の裏面端部に無添加多結晶シリコン12が残ってい
る状態で第1図(C)に示すようにアニール光14にシ
リコンウェハ11に当て、ランプ熱処理(RTA)を実
施する。
Thereafter, after removing the resist 9 turf 13, the silicon wafer 11 is exposed to an annealing light 14 as shown in FIG. , perform lamp heat treatment (RTA).

すると、このRTAにおいて、従来、シリコンウェハ1
1の端部がその他に比べて低温になるところが、この実
施例においては無添加多結晶シリコン12の堆積により
第3図(a)に示すように端部の温度が上がり、その結
果、シリコンウェハ11の温度が全体的に均一になるの
で、ウェハ11の端部にスリップが発生することが無く
なる。
Then, in this RTA, conventionally, silicon wafer 1
In this example, the temperature at the end of the silicon wafer increases as shown in FIG. 3(a) due to the deposition of additive-free polycrystalline silicon 12. Since the temperature of the wafer 11 becomes uniform throughout, slips do not occur at the edges of the wafer 11.

第2図はこの発明の第2の実施例を示す。この第2の実
施例では、シリコンウェハ11の表面に無添加多結晶シ
リコン12をloonm〜500nm堆積させた後、パ
ターン13aをマスクとして無添加多結晶シリコン12
をエツチングすることにより、この無添加多結晶シリコ
ン12を第2図(a)に示すように、シリコンウェハ1
1の裏面端部数m諺の領域t−除きシリコンウェハ11
の裏面に残す。
FIG. 2 shows a second embodiment of the invention. In this second embodiment, after depositing additive-free polycrystalline silicon 12 to a thickness of 100 nm to 500 nm on the surface of a silicon wafer 11, the additive-free polycrystalline silicon 12 is deposited using the pattern 13a as a mask.
By etching this additive-free polycrystalline silicon 12, as shown in FIG. 2(a), a silicon wafer 1 is formed.
Silicon wafer 11 except for the proverbial area t, which is the number m of the backside edge of 1
Leave it on the back side.

そして、前記レジスト・(ターン13aを除去後、前述
のように無添加多結晶シリコン12が残存した状態で7
ニール光14を当ててシリコンウェハ11のRTAを実
施する。すると、この第2の実施例では、シリコンウェ
ハ11の端部を除く領域の温度が第3図(b)に示すよ
うに上昇し、その結果、ウェハ11の端部とその他で急
蔽な温度差がつくので、スリップの発生は端部のみに限
られるようになり、その結果としてシリコンウェハ11
の有効領域からスリップが発生するのが防止される。
After removing the resist turn 13a, 7
RTA of the silicon wafer 11 is performed by applying the Neil light 14. Then, in this second embodiment, the temperature of the region other than the edge of the silicon wafer 11 rises as shown in FIG. As a result, the occurrence of slip is limited to only the edges, and as a result, the silicon wafer 11
This prevents slippage from occurring from the effective area of the

(発明の効果) 以上詳述したように、この発明の方法によれば、半導体
基板の表面または裏面に選択的に無添加多結晶シリコン
を堆積させた状態でランプによる熱処理を実施すること
により、該ランプ熱処理工程中の半導体基板の面内温度
グロファイルを制御可能としたので、通常ランプ熱処理
中に形成されるスリップの発生を半導体基板の全体から
、あるいはスリップの発生を基板端部に限定させて基板
の有効領域から除去することが可能となる。また、この
方法は、大口径の半導体基板でも良好な結果を得ること
ができるものであり、しかも基板の径の変更に対しても
部品の交換などを必蒙とせずに容易に対処できる。
(Effects of the Invention) As detailed above, according to the method of the present invention, by performing heat treatment using a lamp while additive-free polycrystalline silicon is selectively deposited on the front or back surface of a semiconductor substrate, Since it is possible to control the in-plane temperature profile of the semiconductor substrate during the lamp heat treatment process, it is possible to prevent the occurrence of slip that is normally formed during lamp heat treatment from the entire semiconductor substrate, or to limit the occurrence of slip to the edges of the substrate. This makes it possible to remove it from the effective area of the substrate. Further, this method can obtain good results even with large-diameter semiconductor substrates, and can easily cope with changes in the diameter of the substrate without requiring replacement of parts.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は仁の発明の半導体素子の製造方法の第1の実施
例を示す工程断面図、第2図はこの発明の第2の実施例
を示す工程断面図、第3図はこの発明の第1および第2
の″A施雄側おけるRTA中のウェハ径方向の温度特性
図、第4図は無添加多結晶シリコン堆積基板と非堆積基
板のRTA時の温度差を示す特性図、第5図はRTA装
置の概略断面図、第6図は従来のRTA中の半導体ウェ
ハの光の入放射を示す図である。 11・・・シリコンウェハ、12・・・無添加多結晶シ
リコン、14・・・7 ニール光。 /4−−゛アニール尤 第 2vA
FIG. 1 is a process sectional view showing a first embodiment of the semiconductor device manufacturing method of Jin's invention, FIG. 2 is a process sectional view showing a second embodiment of the invention, and FIG. 1st and 2nd
Figure 4 is a characteristic diagram showing the temperature difference during RTA between a non-additive polycrystalline silicon deposited substrate and a non-deposited substrate, and Figure 5 is a temperature characteristic diagram in the radial direction of the wafer during RTA on the "A side". 6 is a diagram showing the incidence and emission of light from a semiconductor wafer during conventional RTA. 11...Silicon wafer, 12...Additive-free polycrystalline silicon, 14...7 Neil Light. /4--゛Anneal first 2vA

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の表面または裏面に選択的に無添加多
結晶シリコンを堆積させた状態でランプによる熱処理を
実施することを特徴とする半導体素子の製造方法。
(1) A method for manufacturing a semiconductor device, which comprises performing heat treatment using a lamp after selectively depositing additive-free polycrystalline silicon on the front or back surface of a semiconductor substrate.
(2)半導体基板の裏面端部数mmの領域のみに無添加
多結晶シリコンを堆積させることを特徴とする特許請求
の範囲第1項記載の半導体素子の製造方法。
(2) A method for manufacturing a semiconductor device according to claim 1, characterized in that additive-free polycrystalline silicon is deposited only in a region several millimeters from the end of the back surface of the semiconductor substrate.
(3)半導体基板の裏面端部数mmの領域を除き、無添
加多結晶シリコンを堆積させたことを特徴とする特許請
求の範囲第1項記載の半導体素子の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein additive-free polycrystalline silicon is deposited except for a region several millimeters away from the end of the back surface of the semiconductor substrate.
JP3925287A 1987-02-24 1987-02-24 Manufacture of semiconductor element Pending JPS63207125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3925287A JPS63207125A (en) 1987-02-24 1987-02-24 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3925287A JPS63207125A (en) 1987-02-24 1987-02-24 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS63207125A true JPS63207125A (en) 1988-08-26

Family

ID=12547946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3925287A Pending JPS63207125A (en) 1987-02-24 1987-02-24 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS63207125A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179837A (en) * 2004-12-24 2006-07-06 Fujitsu Ltd Manufacturing method for semiconductor device, wafer and manufacturing method for it
JP2008277696A (en) * 2007-05-07 2008-11-13 Toshiba Corp Method of manufacturing semiconductor device
US7459354B2 (en) 2001-01-29 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device including top gate thin film transistor and method for manufacturing an active matrix device including top gate thin film transistor
JP2012069774A (en) * 2010-09-24 2012-04-05 Covalent Materials Corp Silicon wafer heat treatment method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459354B2 (en) 2001-01-29 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device including top gate thin film transistor and method for manufacturing an active matrix device including top gate thin film transistor
JP2006179837A (en) * 2004-12-24 2006-07-06 Fujitsu Ltd Manufacturing method for semiconductor device, wafer and manufacturing method for it
US7859088B2 (en) 2004-12-24 2010-12-28 Fujitsu Semiconductor Limited Semiconductor device manufacturing method, wafer, and wafer manufacturing method
JP2008277696A (en) * 2007-05-07 2008-11-13 Toshiba Corp Method of manufacturing semiconductor device
US7759259B2 (en) 2007-05-07 2010-07-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2012069774A (en) * 2010-09-24 2012-04-05 Covalent Materials Corp Silicon wafer heat treatment method

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