JPS63205968A - Semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a miniaturized thin-wire-like channel structure by a method wherein a thin-wire-like high-concentration impurity doped region is formed in a layer having a weak electron affinity and another layer having a strong electron affinity is formed on the region. CONSTITUTION:An FET is constituted by a source electrode 7, a drain electrode 8 and a gate electrode 4. An undoped AlGaAs layer 2 grown by a molecular beam epitaxial method, a p-type GaAs layer 3 and an n-type impurity doped region 5 are formed on a semiinsulating GaAs substrate 1; the region 5 acts as a channel-inducing region. The region 5 is doped selectively; the spread of a region 6 in the transverse direction is prescribed by the spread of a potential generated by a space charge in the region 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a semiconductor device that maximizes the operating speed by utilizing the high-speed propagation effect of electrons in a compound semiconductor such as GaAs. It is related to.

More specifically, we have improved the so-called HEMT (High Electron Mobility Transistor) structure and applied this cross-sectional structure to one-dimensional FETs and quantum interference transistors (QTTs).
The present invention relates to a semiconductor device suitable for application to transistors).

[Conventional technology]

Conventionally, many attempts have been made to construct high-speed semiconductor devices by utilizing the high-speed propagation effect of electrons in semiconductors.

In particular, by confining electrons, which serve as carriers, in one dimension, it is possible to realize a device with characteristics that greatly exceed those of conventional devices. For example, a one-dimensional FET has been proposed that utilizes high electron mobility by confining the movement of electrons within one dimension and reducing the influence of scattering. (H. Sakaki, Japanese Journal of Applied Physics 19.735 (1980). H. Sakaki, Professional Sweating 1981 International Symposium on Gallium Arsenide and Related Compounds, 1981, Oiso Institute Physics Conference Series 63°251 (198
2nd year) (H, 5akaki, Jpn, J, App
l, Phy,.

19, 735 (1980), H, 5akaki,
Proc., 1981 Int.

Symp, on GaAs & Re1ated C
compound, 1981.0iso.

In5t, Phys, Conf, Ser,, 6
3.251 (1982)) The planar structure of such an element is shown in FIG. 67 is a source electrode, 68 is a drain electrode, 66 is a thin channel, and 64 is a gate electrode. Various cross-sectional structures have been proposed, which will be discussed later.

In addition, if a channel structure in which the channel through which electrons pass is once branched, divided into two channels, and then recombined into one channel can be realized, a phase difference in the electrons will occur between the two divided channels, and interference will occur at the combined part. It has been proposed to obtain transistor action using the change in conductance caused by this. (Nith Dutta, M. R. Melok, N. Pandyopadhyay, and M. N. Lundstrom, Applied Physics Letters 48, 487 (1986) (S, [1
atta.

M., R. Melloch, S. Bandyopa.
dhyay, and M, S.

Lundstrom, Appl, Phys, Le
TT, 48.487 (1986)) Such a transistor is called a quantum interference transistor (QIT). Its planar structure is shown in FIG. 6(b). 6
7 is a source electrode, 68 is a drain electrode, and 64 is a gate electrode formed only on one of the two paths. 66 is a channel divided into two at the middle. The operating principle of such a QIT is completely different from that of a one-dimensional FET. That is,
While FET controls the number of electrons, QIT controls the phase of electrons. For this reason, the absolute value of the voltage applied to the gate to be controlled is about several hundred mV for a FET, whereas it is about several mV for a QIT. In this way, there are differences in the operating principle between FET and QIT, but QI
If the electrons in the channel can be more completely confined in one dimension even at T, the interference effect will be more complete and the device characteristics can be improved.

In this way, in order to realize this type of ultra-high-speed device,
It is necessary to realize a potential structure that one-dimensionally confines electrons within the channel region to the de Broglie wavelength of several + nm or less, and a potential structure that allows a thinned channel region with branch points to be configured in an arbitrary shape.

Furthermore, with miniaturization, it is essentially necessary to reduce the influence of surface interfaces, which are important factors that impair electrical characteristics.

[Problem that the invention seeks to solve]

Conventionally, many structures have been proposed for realizing this type of device, but as will be explained below, no solution has been found that satisfies the above requirements, and no device has been realized.

The biggest reason for this is a problem based on the cross-sectional structure under the gate electrode, indicated by aa' in FIGS. 6(a) and 6(b). The problems of the conventional example will be explained in detail below.

The cross-sectional structure of the first example according to the conventional method is shown in FIG. 6(c).

In the figure, 61 is a semi-insulating GaAs substrate, 62 is a non-doped GaAs layer, and 63 is an n-type fiJL GaA
s layer, 64 is a gate electrode, and 65 is an induced carrier gas.

This structure can be constructed, for example, using a semi-insulating G
On the aAs substrate 61, a non-doped GaAs layer 62
, an n-type AnGaAs layer 63 is sequentially formed by molecular beam epitaxial (MBE) crystal growth method, a gate electrode 64 is further deposited, processed to desired dimensions, and then mesa-etched. . n-type A
When the fl Ga As layer 63 is appropriately doped with impurities, the non-doped Ga As layer 62 is
A carrier gas 6 is provided at the interface with the n-type A-vertical GaAs layer 63.
5 is induced and acts as a channel region. ``This effect is a well-known fact in so-called HEMT devices.

In this structure, the potential structure for confining electrons consists of a non-doped GaAs layer 62 in the vertical direction and an n-type A
ft defined by the difference in electron affinity of the GaAs layer 63 and the space charge in the non-doped GaAs layer 62, and the width W of the channel in the lateral direction, that is, the width W of the channel, is determined by the shape of the non-doped GaAs layer 62 by mesa etching, that is, the non-doped GaAs layer 62. The GaAs layer 62 is defined by the difference in electronic states (energy levels) in vacuum.

However, this structure has a problem with the method of defining the lateral potential structure by mesa etching.

In this structure, in order to narrow the lateral spread of the carrier gas region 65 and enhance the one-dimensional confinement effect, it is necessary to rely on etching techniques such as miniaturization of the mask in the etching process and the use of side etching. However, there were great difficulties in realizing a fine structure of several tens of nanometers or less.

Furthermore, it is widely known that it is difficult to stabilize the surface or interface of a compound semiconductor, and trap levels are generated on the surface, causing deterioration of electrical properties such as a drift phenomenon in the current value.

Therefore, even if a fine structure can be realized by making full use of etching technology, since the horizontal direction of a single structure is the surface, it is necessary to stabilize it. However, there is a problem in that no effective means for surface stabilization has been found at present.

A second example using the conventional method is shown in FIG. 7. J71 is a semi-insulating GaAs substrate, and 72.75 is a non-doped Al1G substrate.
73 is a non-doped GaAs layer, 77 is a mixed crystal region, 76 is a formed channel region, and 74 is a gate electrode which also serves as an impurity doping mask.

This structure can be constructed using, for example, a semi-insulating G
On the aAs substrate 71, non-doped AnGaAs
layer 72, non-doped GaAs layer 73, non-doped An
After forming the GaAs layer 75 sequentially by the MBE crystal growth method, an S layer is formed using an appropriate mask and gate electrode 74.
The AflGaAs mixed crystal region 77 is obtained by thermally diffusing the AflGaAs mixed crystal region 77 by heat treatment. Alternatively, a similar structure can be obtained by implanting ions of Ga, Si, etc. into the region 77 using ion implantation technology and performing heat treatment.

In the potential structure that confines electrons in this example, the vertical direction is a non-doped An Ga As layer 72.7
5 and the non-doped GaAs layer 73, and the lateral direction is defined by the difference in electron affinity between the mixed crystal region 77 and the GaAs layer 76.

In this structure, the channel region is entirely surrounded by a heterostructure, and the channel region is not exposed to the outside during the manufacturing process, so it is stable against the surface caused by mesa etching, which was pointed out in the first conventional example. The problem of difficulty has been solved.

However, like the first conventional example, in order to narrow the lateral extent of the channel region 76 in this structure, it is necessary to miniaturize the mask in the thermal diffusion process or ion implantation process, and There were great difficulties in realizing the miniaturized structure.

In addition, in this structure, in order to determine the dimensions of the channel region 76 by the mixed crystal formation process based on the diffusion phenomenon caused by heat treatment, in other words, as shown in the impurity concentration distribution of the ion-implanted region in FIG. Since the concentration of the crystal region is low and the characteristics are gentle, it is difficult to obtain a sharp boundary between the channel region and the mixed crystal region, and a fine structure with a lateral extent of several tens of r+m or less is realized. The problem was that it was inherently difficult to do so.

A third example using the conventional method is shown in FIG.

81 is a semi-insulating GaAs substrate, 82.85 is a non-doped All GaAs ffJ, and 87 is an n-type MG.
a As layer, 83 is non-doped GaAsJ5.86
84 is a formed channel region, and 84 is a gate electrode.

This structure can be constructed, for example, using a semi-insulating G
On the aAs substrate 81, a non-doped AnGaAs layer 82,
Non-doped GaAs layer 83, non-doped AQ Ga
After the As layer 85 is sequentially formed by the MBE crystal growth method.

This is obtained by performing mesa processing, further growing an n-type All Ga As layer 87, and depositing a gate electrode 84. If the n-type ML GaAs layer 87 is appropriately doped with impurities, non-doped GaAs
A carrier gas is induced in the layer 83 at the interface with the n-type AnGaAs layer 87 and acts as a channel region 86 .

In the potential structure in this example, the vertical direction is composed of non-doped An Ga A s82.85 and non-doped G
It is defined by the difference in electron affinity between the a As layer 83, and in the lateral direction, the n-type All Ga As layer 87 and the non-doped G
a Difference in electron affinity of A s layer 83 and non-doped G
It is defined by the space charge of a A s ljJ 83.

In this structure, the potential that has the confinement effect depends only on the control accuracy of the laminated film thickness, so in principle it is possible to realize a fine structure of several tens of nanometers or less, and it is possible to Particularly regarding confinement in the lateral direction (indicated by W in the figure), it is superior to the above two examples.

However, since this structure utilizes the mesa-processed etched portion, the etching and n-type AQGaAs layer 8
There was a problem in that it required 7 regrowth steps and required advanced manufacturing technology.

Furthermore, since the end face of the non-doped GaAs layer 83, which will become the channel region, is exposed to the etching atmosphere, atmosphere, etc. during the process to form the etched part, it is necessary to perform a surface stabilization treatment on the end face part.

However, as mentioned in the first conventional example, it is widely known that it is difficult to stabilize the surface or interface of compound semiconductors, and trap levels occur on the surface, causing drift phenomena in the current value, etc. There is a phenomenon of deterioration of the electrical properties of the surface, and currently no effective means have been found to stabilize the surface.

There was a serious problem.

Furthermore, since this structure utilizes a channel region induced on the end face, it is theoretically impossible to branch the channel region 86 into two or more channels for application to QIT, for example, and the branching point is When trying to construct a potential structure in an arbitrary shape using the thinned channel region, there are problems in that the structure is complicated and the manufacturing technology is required to be more sophisticated.

As described above, in the conventional structure, the biggest problem to be solved is that the width W of the channel cannot be formed so narrow that it can be regarded as one-dimensional when viewed at the electronic level.

The object of the present invention was to solve problems when the lateral dimension of a potential structure that confines electrons is made finer to about 1100 nm or less. The object of the present invention is to provide a fine linear channel structure that solves the difficulties of forming a fine structure, the difficulty of surface stabilization treatment, and the difficulty of forming one branch point.

[Means for solving problems]

The present invention provides a thin line-shaped region doped with a high concentration of impurities in a substrate or a growth layer on the substrate that has a low electron affinity, and a layer with a higher electron affinity is provided on top of the thin line-like region, and the impurity doped region is function as a channel induction region,
A so-called HE that induces a channel region consisting of a carrier accumulation layer or a carrier inversion layer on the lower surface of the layer above it.
We propose a one-dimensional FET or QIT having an MT structure (more precisely, an inverted HEMT structure) as a cross-sectional structure.

Furthermore, in one embodiment, in order to narrow the width of the channel and realize a -dimensional channel, microfabrication technology using a focused ion beam or the like is used, and the impurity doping concentration distribution is changed so that the central part has a high concentration. Taking advantage of the characteristics of
It is possible to induce a narrower channel corresponding to this central portion.

[Effect]

In this way, in the film thickness direction of the grown film (direction perpendicular to the main surface of the substrate), an extremely fine structure (equivalent to +Yarnel height) can be realized using known high-precision film thickness control technology. At the same time, the lateral, ie, channel width direction can also be made extremely fine without being adversely affected by surface traps, and as a result, a one-dimensional channel can be realized. Therefore, if applied to FETs or QITs, it is possible to realize high-speed devices that make maximum use of the high-speed propagation effect of electrons.

In addition, in the conventional technology, only a channel width equal to the maximum width of the channel induction region could be realized, but according to one embodiment of the present invention, the convex shape of the impurity concentration distribution of the channel induction region is used to realize a physical This has the effect of realizing a channel width narrower than the maximum width. Therefore, it is possible to realize a channel width that is less than the physical processing limit of the channel inducing region, and therefore it is possible to realize a one-dimensional channel more easily.

〔Example〕

Embodiment 1 FIGS. 1(a) to 1(c) are diagrams showing a first embodiment of the present invention. In each figure, the same or corresponding reference numerals indicate the same or similar members.

However, Fig. 1(c) shows only the cross-sectional structure, and Fig. 1(c) shows only the cross-sectional structure.
One-dimensional FET shown in a) or Q shown in FIG. 1(b)
A cross section along aa' of IT is shown.

As mentioned earlier, one-dimensional FET and QIT are elements with completely different structures and operating principles, but they have in common that if a one-dimensional channel can be formed, the performance will be further improved, and from this point of view, For example, the cross-sectional structure directly under the gate is important; in other words, if only this structure is specified, it can be easily applied to both. Therefore, in the following examples, the explanation will be limited to the cross-sectional structure.

Note that FIG. 1(a) shows the FET and (
In the plan view of b), 7 and 8 are source electrodes, respectively.
and drain electrode 1, for example, n-type Ge, n-type In
This is a so-called non-alloy ohmic electrode formed of a material such as GaAs. , 4 are, for example, Ti/Au or W
This is a gate electrode obtained by depositing Si to a thickness of about 0.3 mm. This structure allows the flow of electrons in the channel region 6 to be controlled by signals applied to the respective gate electrodes 4, resulting in FET or QIT operation.

As will be described in detail in the following explanation, in the structure according to the present invention, the width of the channel region 6 can be reduced to 1100 nm or less, so electrons are confined one-dimensionally and the mobility of electrons is increased. The transconductance of is also increased.

In the cross-sectional view of FIG. 1(c), 1 is semi-insulating GaAs.
2 is a semi-insulating GaAs substrate] and non-doped A grown by molecular beam epitaxial method (MBE method).
In the nGaAs layer, the composition ratio of 晟 is arbitrary, but
About 0.2 to 0.5 is desirable. 3 is a non-doped or p-type GaAs layer grown by the MBE method on the non-doped Afl Ga As layer 2; 5 is a non-doped or p-type GaAs layer grown prior to the growth of the non-doped or p-type GaAs layer 3;

This is an n-type impurity doped region selectively doped with an n-type impurity such as Si at a concentration of 10''/cm' or more, and acts as a channel inducing region.

In order to selectively dope the n-type impurity doped region 5 with impurities, for example, in addition to the usual ion implantation method using a mask, thermal diffusion method, etc., a more desirable manufacturing method is to use a vacuum. Using a focused ion beam device and a molecular beam epitaxial device that are combined so that they can be transported without breaking, after the non-doped M Ga As layer 2 is grown, the focused ion beam device is transported to the focused ion beam device without breaking the vacuum, and the focused ion beam is transferred to the focused ion beam device without breaking the vacuum. There is a method in which ions are implanted into the region 5 using an ion beam generated by a beam device, and then the undoped or p-type GaAsJli3 is regrown by transferring the region to the molecular beam epitaxial device again without breaking the vacuum.

Reference numeral 6 denotes a channel region which is non-doped or induced in the p-type GaAs layer 3 by the n-type impurity doped region 5, and corresponds to 6 in FIGS. 1(a) and 1(b).

Since the electron affinity of the non-doped or p-type GaAs layer 3 is greater than that of the non-doped AnGaAs layer 2, the impurity concentration of the n-type impurity doped region 5 is 101 G/am-
3 or more, the electrons supplied to the n-type impurity doped region 5 by doping are AfJ, GaAs layer 5
From there to the GaAs layer 3, a channel region 6 consisting of a carrier accumulation layer or a carrier inversion layer is formed. This mechanism is well known for HEMT and reverse HEMT devices. In HEMT, by using a high purity layer for the P-type GaAs layer 3, the mean free path caused by impurity scattering of electrons traveling in the channel region 6 increases, and the electrical characteristics are significantly improved. This is a known fact. That is, if it is explained based on the plan view of FIGS. 1(,) and 1(b), the source electrode 7 and the drain electrode 8 are formed of a material such as n-type Ge or n-type InGaAs.
Since it is a non-alloy ohmic electrode, the electrode does not extend deep into the substrate. Therefore, when looking at the cross-sectional structure diagram of FIG. 1(C), the current between the source and drain is shown in the channel region 6.
and does not flow into the channel inducing region 5.

A major feature of this structure is that the n-type impurity doped region 5 is selectively doped, so that the channel region 6 expands in the lateral direction (W in FIGS. 1(a) and 1(b)).
is defined by the potential spread caused by the space charge in the n-type impurity doped region 5. Furthermore, in its formation process and final structure,
One of the major effects brought about by this structure is that the surface of the crystal is not exposed to the atmosphere, etching atmosphere, etc., so that no surface stabilization treatment is required. Further, by modulating the mask pattern or the scanning method of the focused ion beam, a channel region of any shape including branches can be formed. Furthermore, the dimensions of the selectively formed region are determined by the mask dimensions during ion implantation or the focusing width of the focused ion beam, but it is known that current technology can miniaturize the region to about 0.1-. 0.1
Channel regions up to the layer size can be formed by this method.

In order to obtain the effects of the present invention, the width of the channel region should be 0.
It is necessary that the wavelength be 57 m or less, but in order to further improve the characteristics, it is necessary to
That is, it is desirable that the thickness be several tens of nanometers or less.

Example 2 FIG. 2 is a sectional view showing a second embodiment of the invention.

Identical parts are given the same reference numerals as in the first embodiment (FIG. 1(C)). The difference from the first embodiment is that layer 3 in FIG. 1 is composed of two layers 23a and 23b. That is, 21 is a semi-insulating GaAs substrate, 22 is a non-doped AnGaAs layer, 23a is a non-doped or p-type GaAs layer, and 23b is a non-doped AfL GaAs sM having a lower electron affinity than 23a.

24 is a gate electrode, 25 is an n-type impurity doped region, 26
is the channel region. Here, the layer 23a has a thickness of 10
nm or less, and a double heterostructure is formed by growing on the 23a layer, for example, an An Ga As layer with a smaller electron affinity than the 23a layer, by the MBE method, and the 23 layer is made into a multilayer, so-called Channel region 2 as a quantum well
By realizing a structure in which the film thickness dimension d of 6 can be limited to a small value, a channel that is even more nearly one-dimensional can be realized by confining the channel more effectively.

Note that it is also possible to arbitrarily combine the concept of this embodiment with other embodiments of the present invention.

Example 3 FIG. 3 is a sectional view showing a third embodiment of the present invention.

The same parts are given the same reference numerals as in the first embodiment (FIG. 1(c)). The difference from the first embodiment is that 39 layers are provided between the 32nd and 33rd layers. layer 39
is a so-called spacer layer interposed between the 32nd layer and the 33rd layer, and is a non-doped AnGaAs layer. That is, 31 is a semi-insulating GaAs substrate, 32 is a non-doped MGaAs layer, 33 is a non-doped or P-type GaAs layer, and 39 is a non-doped MGAs layer.
34 is a gate electrode, 35 is an n-type impurity doped region, and 36 is a channel region. Non-doped All Ga As in which impurity layer doped region 35 exists
layer 32, a non-doped AnGaAs layer 39 thereon, and a non-doped or p-type GaAs layer 39 thereon.
The relationship between the electron affinities of the layer 33 is small, small, and large, and this intermediate layer 39 acts as a spacer layer,
'It is well known that the electron transport characteristics in HEMT operation can be improved, so the explanation will be omitted.

Note that it is also possible to arbitrarily combine the concept of this embodiment with other embodiments of the present invention.

Embodiment 4 FIGS. 4(a) and 4(b) are diagrams showing a fourth embodiment of the present invention, and the same parts as those of the first embodiment (FIG. 1(C)
) with the corresponding sign.

The difference from the first embodiment is that impurity-doped channel inducing regions 45b and 45b are formed with their central portions overlapping each other. That is, 41 is a semi-insulating GaAs substrate, 42 is a non-doped AI GaAs layer, and 7I3
44 is a gate electrode, 45a and 45b are n-type impurity doped regions (channel induction regions), and 46 is a channel region.

The structure having 45a and 45b can be obtained, for example, by performing ion implantation using a focused ion beam generator and scanning the ion beam twice at a small distance from each other.

Because of this structure, the impurity concentration in the overlapping part of 45a and 45b is higher than in other parts of the region 45d and 45b, and the impurity concentration in the entire channel induction region is as shown in FIG. As shown in b), it has a convex concentration distribution. In this structure, by appropriately selecting the concentrations of 45a and 45b, it is possible to cause only the overlapping portion, that is, the maximum point of the convex concentration distribution, to act as an effective channel inducing region. 46 is the channel region thus produced.

For example, according to recent focused ion beam generators, it is possible to adjust the minute distance between 45a and 45b to 0.057/I11 or less.
A channel region with a thickness of 1ρ or less can be formed.

Example 5 FIG. 5 is a sectional view showing a fifth embodiment of the present invention.

In the figure, 51 is a semi-insulating GaAs substrate, 100 is a non-doped GaAs layer, and 52 is a non-doped Afl Ga
As layer, 53 is non-doped or p-type GaAs layer, 54
10 is a gate electrode, 55 is an n-type impurity doped region (channel induction region), 56a, 56b, and 56c are channel regions induced by the n-type impurity doped region, respectively;
2 is an ohmic electrode, 101 is an n-type impurity doped region (
conductive area).

The feature of this structure is that the control potential applied to the ohmic electrode 102 is transmitted to the channel induction region 55 via the conductive region 101, and the channel region is changed from the actual channel induction region 55 by the bias potential of the channel induction region 55. It combines the effect of being able to change the size to any desired size.

In order to achieve this purpose, the ohmic electrode 102 is an impurity doped region 1 provided on the GaAs layer 100.
01 bias electrode.

On the other hand, the gate electrode 54 is an electrode for controlling electrons traveling from the source to the drain in the channel region formed in this way, and is used in the FET shown in FIG. 1(a).
, and corresponds to 4 in the QIT shown in FIG. 1(b). A control signal applied to the gate electrode 54 controls the number of electrons flowing in the channel region in a FET and the phase in a QIT, so that each transistor operates as a transistor.

Note that in this structure, after the GaAs layer 100 is provided on the substrate 51, a conductive region 101 is formed in this GaAs layer 100.
However, the same effect can be obtained even if the GaAs layer 100 is omitted, the conductive region 101 is formed directly in the substrate 51, and the ohmic electrode 102 is formed on the substrate 51.

According to this structure, by applying various potentials to the ohmic electrode 102, the cross-sectional dimension of the channel region can be changed. That is, when a positive bias potential is applied to the electrode 102, the channel region becomes 5 as shown at 56c.
It spreads out compared to 6b, and when a negative bias is applied, it becomes 56a.
becomes narrower as shown in .

Therefore, the bias potential of the electrode 102 has the function of changing the channel region. In particular, by applying a negative bias, a channel region narrower than the physical width of the impurity doped region 55 can be realized, with a width of 0.1 μm or less. A channel region can now be formed.

The embodiments of the present invention have been described above. In the above embodiments, GaAs, All G
Although the aA s layer is used, a heterostructure with the same electron affinity size relationship as this combination, such as InP/I
It is clear that similar effects can be obtained by using nGaAs, InGaAs/InAnAs, and the like.

〔Effect of the invention〕

As explained above, in the present invention, a part of the cross-sectional structure has a so-called HEMT (or reverse HEMT) structure, and the channel inducing region can be selectively doped in one dimension, and the channel This is because the lateral extent of the region is defined by the extent of the potential induced by the channel-induced region.

(1) A channel region up to several tens of nm thick can be formed.

(2) The surface of the crystal is not exposed to the atmosphere, etching atmosphere, etc. during the formation process and final structure, and surface stabilization treatment is not required.

(3) By modulating the mask pattern or the scanning method of the focused ion beam, a channel region of any shape including branches can be formed.

Therefore, by applying the semiconductor structure of the present invention to a one-dimensional FET, QIT, etc., it becomes possible to realize an ultrahigh-speed device.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a one-dimensional FET according to the present invention, FIG. 1(b) is a plan view of a QIT according to the present invention, and FIG.
) is a sectional view near the gate electrode of the first embodiment of the present invention,
Fig. 2 is a sectional view showing a second embodiment of the invention, Fig. 3 is a sectional view showing a third embodiment of the invention, and Fig. 4(a) is a sectional view showing a fourth embodiment of the invention. The cross-sectional view shown in FIG. 4(b) is the fourth
Figure 6(a) is a diagram showing the impurity concentration distribution of the channel induction region, Figure 5 is a cross-sectional view showing the fifth embodiment of the present invention, Figure 6(a) is a plan view of a conventional one-dimensional FET, FIG. 6(b) is a plan view of a conventional QIT, FIG. 6(c) is a cross-sectional view near the gate electrode of the first conventional example, and FIGS. 7(a) and (b) are a plan view of a conventional QIT. FIG. 8 is a sectional view showing a third conventional example. 1.21.31.41.51.61.71.81...
Semi-insulating GaAs substrate 2.22.32.42.52...Non-doped AnGaAs layer 3.23a, 3
3.43%53...Non-doped or p-type GaAs layer4.24.34
．． 44.54.64.74.84...Gate electrode 5, 25.35.45a, 45b, 55...N-type impurity doped region (channel induction region) 6.6a, 6b, 2
6.36.46.56a, 56b, 56c, 66.66
a, 66b, 76.86...Channel region 7.67...Source electrode 8.68...Drain region 23b, 82.85-...Non-doped An Ga A
s layer 39...Non-doped A vertical GaAs layer (spacer M) 62.73.83.10!1-, non-doped GaA
s layer 63.85-n type An Ga As s layer 65...
・Induced carrier gas 72.75-...Non-doped AQ Ga As layer 7
7... Mixed crystal region 101... N-type impurity doped region (conductive region) 102
...Diagram of Ohmic Electrode Diagram 4 (Ku) (b) Distance (F-value) Procedural Amendment Form) May 6, 1988 Commissioner of the Japan Patent Office Kuro 1) Akio Tono 1, Incident Indication: Patent Application No. 38732 of 1988 2, Title of invention: Semiconductor device 3, Relationship with the case of the person making the amendment: Name of patent applicant (422) Nippon Telegraph and Telephone Corporation 5,
Date of amendment order: April 28, 1986 6. Subject of amendment: Drawing

Claims (1)

[Claims] 1. A first semiconductor layer (2) formed on a semiconductor substrate (1)
), a second semiconductor layer (3) formed on the first semiconductor layer and having a higher electron affinity than the first semiconductor layer; a heavily doped region (5) having a predetermined depth and formed in a thin line shape, and a channel region (5) induced to be formed in the second semiconductor layer in contact with the highly doped region (5);
6), a first electrode (4) formed on the channel region at a predetermined position where lines of electric force extend to the channel region, and the first electrode (4) placed between both ends of the channel region or above. a second electrode (7) and a third electrode (8) provided on the channel region;
A semiconductor device characterized in that a current flowing through the channel region between the electrode and the first electrode is controlled by an electric signal applied to the first electrode. 2. A third semiconductor layer having a lower electron affinity than the second semiconductor layer is formed on the second semiconductor layer in contact with the second semiconductor layer. A semiconductor device according to scope 1. 3. The planar shape of the high concentration impurity doped region is such that both ends are in the form of a single thin line, and the middle portion is branched into two paths, and accordingly, the channel region is also connected to the high concentration impurity doped region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is induced to have the same shape as . 4. The impurity concentration of the above-mentioned high concentration impurity doped region is 10^
3. The semiconductor device according to claim 1 or 3, characterized in that it is 1^6/cm^3 or more. 5. The impurity concentration distribution in the cross section in the width direction of the high concentration impurity doped region is convex, and the channel region is induced only in the high concentration portion corresponding to the center of the convex concentration distribution. A semiconductor device according to claim 1 or 3.