JPS63204348A - System for controlling data input/output of information processing system - Google Patents

Abstract

PURPOSE:To reduce overhead due to an input/output interruption processing at a CPU, etc., by storing a data directly on a memory part without generating input/output interruption to a central processing part until when data length arrives at designated data length at the time of generating the input of the data from a terminal equipment. CONSTITUTION:A READ and a START commands are issued from the CPU 10 to a terminal equipment control part (IOC) 40 in advance, and when data input from the terminal equipment 50 is generated, the IOC stores the data from the terminal equipment in a memory 20 directly without issuing the interruption to the CPU. In such a way, no input/output interruption to the CPU, start up of the terminal equipment from the CPU, and input/output interruption of storage completion from the terminal equipment to a main memory are generated, and it is possible to reduce the overhead due to those processing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data input/output control method for an information processing system, and more specifically, to a method for transferring data between terminal devices connected to the information processing system. The present invention relates to a data input/output control method in a terminal device control unit in the information processing system when the information processing system is used.

[Conventional technology]

Figure 2 shows the general configuration of an information processing system, with a central processing unit (CPU) 10 and a main memory unit (MEM) 2.
0C and a channel section (CH) 30 are connected to each other, a terminal device control section (IOC) 40 is connected to the channel section 30, and a plurality of terminal devices [5
0 is connected. The conventional operation when a data input processing request is issued from the terminal device 50 will be described below.

Terminal device! Data input processing requests from 50 are sent to Engineering 0C4.
0 is the terminal device v! Data from t50 & operation to transfer to MEM20 via CH30 (READ operation) or M
Data from EM20 to terminal device 5.0 via CH30
If no operation (WRITE operation) to transfer the data to is being executed, it is accepted by l0C40 and reported as an input/output interrupt to CPU l0 via CH30. CPUl
When 0 receives an input/output interrupt from l0C40, it determines the contents of the interrupt and starts the terminal device 50 that generated the 1 interrupt via CH30 and l0C40 by instructing a READ operation.l0C40 is CPjUlo. Upon activation from , it receives input data from the terminal device 50, stores it in the MEM 20 via C:H30, and then generates an input/output interrupt to the CPU10 again to report the completion of the operation. CPU10 ends the input/output operation from the terminal device 50 due to the second input/output interrupt.

[Problem that the invention seeks to solve]

In the above conventional technology, in the case of data input processing from a terminal device, input/output interrupts from the terminal device control unit to the CPU occur twice, resulting in a long data transfer time between the information processing system and the terminal device. There is a problem. In particular, if short data is frequently input from the terminal device, input/output interrupts from the terminal device control unit to the CPU and activation of the terminal device from the CPU will occur frequently.
The overhead of programs running on the CPU will increase terminal response time. Also.

A data input processing request from a terminal device causes the terminal device control unit to perform a READ operation with another terminal device.

Or when it occurs while executing a WRITE operation.

The data input processing request from the terminal device is accepted after the completion of the operation being executed, and the terminal response time is extended due to the waiting time until the terminal device control unit accepts the processing.

On the other hand, in information processing systems, the simultaneous operation (full-duplex operation) function of data READ and WRITE operations supported by terminal devices is effectively utilized to shorten terminal response time.

For this purpose, a method has been adopted in which two logical addresses are assigned to one terminal device. In other words, the address (n) for performing the READ operation on the terminal device, and the WRIT
An address (m) for performing the E operation is assigned, and the device is provided as two virtual devices to the application software.

When the application software executes a READ operation, it executes a command to address n to read data, and when it executes a WRITE operation, it executes a command to address m to input and output data. Since the terminal device control unit controls the terminal device on an address-by-address basis, these two operations are executed simultaneously. As a result, the full-duplex operation of the terminal device is effectively utilized and READ
By simultaneously executing /WRITE processing, terminal response time can be shortened.

However, in this method, one terminal device is actually accessed logically as two terminal devices.

Abnormal processing when a failure occurs in a terminal device, recovery processing for data, etc. become complicated. For example, READ operation at address n and WRITE operation at address m
If a failure occurs in the WRITE operation and the command operation terminates abnormally while operations are being executed simultaneously, the READ operation of another device at address n will also terminate abnormally at the same time, and recovery processing for the two devices at addresses m and n will be completed. is required. Therefore, a special error recovery program logically related to the two terminal devices is required in the application software.

It is an object of the present invention to maintain compatibility with input/output control in conventional information processing systems by assigning only one address to a terminal device, and to prevent input/output from occurring on the terminal without causing input/output interruption to the CPU. Data input from the device is stored directly in memory, reducing the overhead caused by input/output interrupt processing in the CPU, etc., and making effective use of the full-duplex operation function supported by the terminal device. The object of the present invention is to shorten terminal response time by making it possible to simultaneously execute data input operations to an information processing system and data output operations from the information processing system to a terminal device.

[Means and effects for solving the problems] The present invention is based on C
READ 5TART from PU to IOC in advance
When a command is issued and data input processing from a terminal device occurs, the IOC does not issue an input/output interrupt to the CPU.

The data from the terminal device is directly stored in the memory.

As a result, input/output interrupts to the CPU, activation of the terminal device from the CPU, and input/output interrupts for completion of storing data from the terminal device to the main memory do not occur, and the overhead associated with these processes is reduced. Furthermore, READ
By issuing the 5TART command in advance and taking advantage of the full duplex operation function supported by the terminal device, the WRITE command issued later allows data output from the memory to the terminal device and Data input operations from the device to the memory are performed simultaneously, and the response time of the terminal device can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of one embodiment of a terminal equipment control section according to the present invention, and the overall configuration of the information processing system is as shown in FIG. 2.

In FIG. 1, a terminal device control unit (IOC) 40 includes a channel interface unit 101, an internal state management unit 102, a parameter holding unit 103, a WRITE operation control unit 104, a READ operation control unit 105, and a terminal device signal line control unit. 106, a data buffer 107, and a signal line driver/receiver circuit 108.

The channel interface section 101 has a channel section (CH
) 30, the main memory unit (MEM) 20 and l0C
Execution of information transfer between 40 and CPU 101 and 10C1
Transfers information associated with startup and termination processing between 04 and 04.

The state management unit 102 inside the IOC starts the operation related to the terminal device 50 specified by the activation of the CPU10, and
A command is fetched from the MEM20 via the H30, analyzed and executed.

It also manages the internal state of the IOC, reports the detection of abnormal conditions, and executes the READ operation as background processing if execution of the READ operation is specified in advance.

Is the parameter holding unit 103 instructed to hold control information necessary for terminal device control (main memory address, transfer data length, data transfer speed of the terminal device, etc.) and to perform a READ operation as background processing? Holds the state of “no”.

The WRITE' operation control unit 104 receives the data read out from the MEM 20 by the channel interface unit 101 into the WRITE data buffer 107-1, and has a control function to sequentially extract data from this buffer and transfer it to the terminal device 50. The driver circuit 10B manages the amount of data transferred to the terminal bag w, 50, adds parity information, converts byte data to bit data, etc.
Send to -1. Furthermore, by managing the WRITE buffer 107-1, errors such as data underruns are detected.

The READ operation control unit 105 receives information asynchronously transferred from the terminal device 50, and performs confirmation of the normality of the received data, such as converting bit data to byte data and detecting parity errors.

Holds 10 low data buffers for READ.

It also manages the READ data buffer 107-2, detects errors such as data overruns, and requests the state management unit 102 to store data in the MEM 20.

The terminal device signal line control unit 106 controls the signal lines necessary between the present IOC 40 and the terminal device 50, and instructs the WRITE operation control unit 104 and the READ operation control unit 105 to permit or prohibit execution of data transfer operations. It performs instructions, detects the state of the terminal device 50, etc.

The data buffer 107 includes a WRITE buffer 107-1 that holds data read from the MEM 20, and a READ buffer 107-1 that holds data received from the terminal bag [50].
buffer 107-2.

The signal line driver/receiver circuit 108 is a WRITE
A driver circuit 108-1 necessary for data transfer from the operation control unit 104 to the terminal bag [50], a receiver circuit 108-2 for receiving data sent from the terminal device [50]
, and a driver/receiver circuit 108-3 for the signal line between the terminal device signal line control unit 106 and the terminal bag $150.

FIG. 3 is an example of a channel program issued by an information processing system to control a terminal device. In Figure 3, we first use the REA to start background processing.
This shows an example of a channel program that issues a D-type command, executes two WRITE operations, and then stops the READ operation being executed as background processing.

Below, using the channel command in Figure 3 as an example, the IO command in Figure 1 is
The flow of processing in C will be explained.

(1) Upon receiving the activation from CPUl0 via CH30, the state management unit 102 starts executing the channel program. First, the SET PARAMETER command at the beginning of the channel program is fetched from the MEM 20. The SET PARAMETER command is a command by which the program transfers the operating environment of the terminal device to the terminal device control unit. The state management unit 102 performs SET PA
When a RAMETER command is detected, multiple control parameters (data transfer rate of the terminal device, data length, buffer control method during data transfer, etc., maximum execution time of the SET PARAMETER command, etc.) are fetched from the MEM 20 based on the command. , parameter holding unit 1
03. Terminal device control by subsequent commands is performed by the parameter holding unit 103 of the corresponding terminal device address.
Execute according to the contents.

(2) When the SET PARAMETER command ends, the state management unit 202 updates the next LIN in the chain.
E0PEN:i? Take out :/ from MEM20,
Execute. The LINE 0PEN command is a command that establishes an interface between the IOC and the terminal device. When the state management unit 102 detects the LINE 0PEN command, it instructs the terminal device signal line control unit 106 to transfer data between the 10C40 and the terminal device [500] necessary to start the data transfer operation between the specified terminal device and the IOC. 0 of signal line
After setting N10FF, one I0C40 sets the data transferred from the terminal device 50 as valid data,
The READ operation control unit 205 stores the READ data in the low data buffer 10 .

(3) When you finish the LINE 0PEN command.

The state management unit 102 selects the next chained READ
5Fetch the TART command from MEM2Q and execute it. The READ 5TART command is a command that instructs the state management unit 102 to perform an operation of storing input data transferred from the terminal device in the MEM address specified by the command as a background process such as a WRITE operation.

Upon receiving the READ 5TART command, the state management unit 102 uses this command to set the parameter holding unit 10 indicating that the READ 5TART command is being executed.
3 is set to ON, the MEM address for storing the data transferred from the terminal device [50] and the data length to be transferred to the MEM 20 are held in the parameter holding unit 103, and the R
It instructs the EAD operation control unit 105 to perform a READ operation. The READ operation control unit 105 controls R of the state management unit 102.
According to the EAD 5TART command, one or more bytes of valid data are input from the terminal device and buffer 1 is filled.
07-2, the state management section 102 is requested to send the data, and the data is directly stored in the MEM 20 via the channel interface section 101. This operation occurs when the transfer data length held in the parameter holding unit 103 becomes 0, when the execution time of the READ 5TART command passes the time specified by the SET PARAMETER command, or when another READ command or 5 Execute independently of other processes until a TOP READ command is detected.

(4) The state management unit 102 controls the READ operation control unit 105
When a READ operation is instructed for the command, the next chained WRITE command is retrieved from the MEM20, and
Execute. The WRITE command is a command to transfer the contents of the main memory to the terminal device, and the state management unit 102
WRIT the data address and transfer data length on EM20
E operation control unit 104 and WRITE operation control unit 1
Start the WRITE operation in 04. The WRITE operation control unit 104 is activated by the state management unit 102, and the MEM
Data is sequentially read from 20 and transferred to the terminal device 50 via the WRITE buffer 107-1. When the transfer of the specified data is completed, the WRITE operation control unit 1
04 reports the completion of data transfer to the state management unit 102. The state management unit 102 is the WRITE operation control unit 104
The operation of one command is completed by waiting for the completion report from.

(5) When the first WRITE command is finished, the state management unit 102 retrieves the next chained WRITE command from the MEM 20 and executes the process (4) again on the address of the MEM 20.

(6) When the second WRITE command is finished.

The state management unit 102 selects the next 5 TOPs that are chained.
The READ command is taken out from the MEM 20 and executed. 5TOP READ command.

This command terminates the operation of the previously issued READ 5TART command. With this command, the state management unit 102 turns off the flag in the parameter holding unit 103 indicating that the READ 5TART command is being executed. R for the operation control unit 105
Instructs to end the EAD operation. As a result, from now on, data transferred from the terminal device [50] will be transferred to the data buffer 1.
It is held in the READ buffer 107-2 of ME
In response to the READ 5TART command completion report from the READ operation control unit 105 that is not transferred to the MEM 20, the state management unit 102 stores the data length that was successfully transferred by the READ 5TART command in the specified area in the MEM 20, and ends the process. .

(7) When the 5TOP READ command ends, the state management unit 102 selects the next LINE in the chain.
The CLO5E command is taken out from the MEM 20 and executed. The LINE CLO3E command is a command that disconnects the interface between the IOC and the terminal device. The state management unit 102 uses the LINECLO8E command to
It clears the data held in the parameter holding unit 103 and also instructs the terminal device signal line control unit 106 to turn off the signal line between the terminal device 50 and the 10C 40. From now on, data transferred from the terminal device [50] will not be received.

(8) In response to the LINE CLO8E command, the state management unit 102 performs termination processing of the channel program, and
Reports the completion status to Ul0.

〔Effect of the invention〕

As explained above, according to the present invention, when data is frequently input from a terminal device, the READ
By issuing the 5TART command to the terminal control unit, the input data from the terminal device is stored in a predetermined memory without input/output interruption, and the CPU checks the information in the memory to control the terminal device. It is possible to obtain data from. As a result, input/output interrupts such as input/output interrupts to the CPU, startup of the terminal device from the CPU, and completion of storing data from the terminal device to memory do not occur, and the overhead associated with these processes is reduced.
Terminal device response time can be shortened.

Furthermore, by issuing a WRITE command to store data from the terminal device to a predetermined memory within the information system, data output operations from the memory to the terminal device by the WRITE command issued later, and data storage from the terminal device Data input operations to the information processing system are performed simultaneously, and the response time of the terminal device can be shortened.

In addition, the 5TOPREAD command may be issued when the content of the data input from the terminal device makes it unnecessary to input any more data, or when the application program starts processing that does not require data input. As a result, input of unnecessary data from the terminal device is prohibited, and overhead associated with input processing in the terminal device control unit and CPU can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a terminal device control unit according to the present invention, FIG. 2 is a block diagram of the entire information processing system targeted by the present invention, and FIG. FIG. 3 is a diagram showing an example of a channel program for explaining the operation. 10...Central processing unit (CPU). 20...Main memory section (MEM). 20... Channel (CH), 40... Terminal device control unit (IOC). 50...Terminal device. 101...Channel interface section. 102... IOC internal state management section, 103... Parameter holding section, 104... WRITE operation control section, 105... READ operation control section, 106... Terminal device signal line control section. 107...Data buffer, 108...Signal line driver/receiver circuit. Figure 1 Figure 2 Figure 7 Sui Xiong Vyay! System ・ (1 ST: T PA shaku △ METER tsu (2) LIJE OF 已 N tsu (7) LINJE CLOBE c nozu la meter tuff F toss) ]C [MEKey dosis, data count]C [M day size completed)'°Response, data count]O

Claims (2)

[Claims] (1) In an information processing system having a central processing unit, a memory unit, and a terminal device control unit that controls a terminal device, the central processing unit transmits input data from the terminal device to the memory unit. By specifying in advance the data length to be stored and the data length to be stored, the terminal device control unit stores data up to the specified data length to the central processing unit when data is input from the terminal device. storing the data directly in the memory unit without generating an input/output interrupt, and generating an input/output interrupt to the central processing unit when data exceeding the specified data length is input from the terminal device. A data input/output control method for an information processing system characterized by: (2) When the terminal device control unit receives an instruction to stop storage from the central processing unit while the data from the terminal device is being stored in the memory unit, the terminal device control unit stores the data input from the terminal device in the memory unit. The data length stored in the memory unit up to the point in time when the stop instruction is received is reported to the central processing unit, and if data input occurs from the terminal device after that, the input/output to the central processing unit is completed. A data input/output control method for an information processing system according to claim 1, characterized in that an interrupt is generated.