JPS63203030A - Bit synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To detect whether or not a recovered clock and an input data are synchronized by returning a count to a prescribed value when a code change point signal is not within a range for a prescribed time and generating a synchronizing detection signal when the count value reaches the prescribed value. CONSTITUTION:When a code change point signal 1200 is not in the timing within + or -1/8T, the signal is given to an AND circuit 52, goes to a signal 90 and given to a clear terminal CL of a shift register 61 of a counter circuit 6. Thus, when the recovered clock 400 is not synchronized with a reception data 100, the signal 900 is outputted from the AND gate 52 to clear a register 61. That is, an output signal from an output terminal QH of the 8-th stage of the register 61 is used as the bit synchronizing detection signal 200, then the signal 200 is zero when the recovered clock 400 is not synchronized with the reception data. So long as the signal 1200 is within + or -1/8T and the recovered clock 400 is synchronized with the reception data 100, the synchronizing detection signal 200 being an output of the register 61 remains logical 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a bit synchronization detection circuit for digital mobile communications.

(Prior Art) A digital PLL (phase locked loop circuit) is often used in a clock recovery circuit of a demodulator for conventional digital data transmission in the mobile communication field. However, in a digital PLL, there is a trade-off between the phase pull-in characteristic and the amount of jitter of the reproduced clock, and if the phase pull-in time is designed to be short, the amount of jitter increases. Conversely, if the amount of jitter is designed to be small, the phase pull-in time becomes longer.

If the amount of jitter is large, the error rate of the received data will be large, so the design is usually made to reduce the amount of jitter, and the drawback of the long phase acquisition time is countered by increasing the number of bits of the bit synchronization signal that is added before the data. Was. However, when data is transmitted in bursts, with this method the ratio of the bit synchronization signal to the transmitted data becomes large.
This has the drawback of deteriorating data transmission efficiency.

(Problems to be Solved by the Invention) In the clock recovery circuit of the conventional digital data transmission demodulator described above, in order to pull in the phase while keeping the amount of jitter small, the number of bits of the bit synchronization signal is increased to completely Since the phase can be pulled in, the bit synchronization signal occupies a large proportion of the transmitted data, which has the disadvantage of deteriorating data transmission efficiency. In order to improve this drawback, it is sufficient to have a digital PLL that can pull in the phase at high speed and has a small amount of jitter. This can be achieved by pulling the phase and then switching the digital PLL to a characteristic with a small amount of jitter. The problem is how to obtain the timing signal for this characteristic switching, but the present invention
The above problem can be solved by using a bit synchronization detection circuit that can detect whether the regenerated clock is synchronized with the received data, and thus the number of bits of the bit synchronization signal can be reduced, increasing data transmission efficiency. be able to.

``Configuration of the Invention (Means for Solving Problems) The bit synchronization detection circuit of the present invention includes a reproduced clock generating means for generating a reproduced clock from input data, and a predetermined time range centered around the rising edge of the reproduced clock. timing signal generation means for generating a designated timing signal; sign change point generation means for generating a sign change point signal indicating a sign change point of input data; and when the sign change point signal is within the predetermined time range. is counted, and if the sign change point signal is not within the predetermined time range, the count value is returned to the initial value, and when the count value reaches a preset value, the input data and the reproduced clock are synchronized. and synchronization detection means for generating a synchronization detection signal indicating that the synchronization has occurred.

(Function) In the bit synchronization detection circuit of the present invention, the reproduced clock generating means generates a reproduced clock from input data and supplies it to the timing signal generating means. The timing signal generating means generates a timing signal specifying a predetermined time range around the rising edge of the reproduced clock, and supplies this to the synchronization detecting means. On the other hand, the sign change point generation means generates a sign change point signal indicating the sign change point of the input data, and supplies this to the synchronization detection means. The synchronization detection means counts when the sign change point signal is within the predetermined time range, returns the count value to the predetermined value when the sign change point signal is not within the predetermined time range, and determines whether the count value is When the set value is reached, a synchronization detection signal is generated indicating that the input data and the reproduced clock are synchronized. With this synchronization detection signal, it is possible to detect whether or not the reproduced clock and input data are synchronized.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the bit synchronization detection circuit of the present invention. 1 is received data 1 that has already been waveform shaped
00 input terminal, 2 is a clock regeneration circuit that regenerates a clock from the received data 100, 3 is a timing generation circuit that sets a timing of a certain width based on the output of the clock regeneration circuit, 4 is a sign change of the received data 100 A sign change point detection circuit for detecting a point, 5 a selection circuit for selecting a signal that advances the count from the output of the sign change point detection circuit 4 based on the output of the timing generation circuit 3 and a signal that returns the count value to a predetermined value, and 6 a selection circuit. A counter circuit 7 counts up the output of the circuit and is reset by this output, and 7 is an output terminal of a bit synchronization detection signal 200.

FIG. 2 is a block diagram showing a detailed example of FIG. 1. However, since the clock regeneration circuit 2 has a large circuit scale,
Illustrations are omitted. The timing generation circuit 3 includes a binary down counter 31 with a preset input that divides the basic clock 300 by 16, flip-flops 32 and 33 that catch the rising edge of the recovered clock 400, and an AND circuit 35.
and an 8-bit shift register 34 which outputs separately loaded data 500 using the output signal 1ioo of the down counter 31 as a clock. The sign change point detection circuit 4 includes flip-flops 41 and 42 and an AND circuit 4 that detect rising and falling edges of the received data 100.
3. /14 and the detection signal 600 output from the AND circuits 43 and 44.

It consists of an OR circuit 45 that takes the OR of 700 and outputs the result.

The selection circuit 5 receives the sign change point detection signal 1200 from the sign change point detection circuit 4 and the data 5 from the timing generation circuit 3.
00, an AND circuit 52 that ANDs the sign change point detection signal 1200 from the circuit 4 and an inverted signal of the data 500, and an inverter 53 that inverts the data 500. counter 6
is the signal 8 that advances the counter output from the selection circuit 5.
00 and is reset by a signal 900 output from the circuit 5 which resets the counter.

Next, the operation of this embodiment will be explained. First, the basic clock (frequency 153.6 K1, which is 128 times the data transmission speed) as shown in Figure 3 (A>) is used to operate the circuit.
-12) 300 is the clock terminal O of the down counter 31, flip-flop 32, 33, 41, 42
It is input to K. The clock 300 input to the binary down counter 31 is divided by 16 to produce a signal 1100 as shown in FIG.
The signal is then input to the clock input terminal CK of the 8-bit shift register 34. Therefore, 8-bit shift register 3
A 1-bit long waveform is outputted from the output terminal Q8 of 4 in 8 clocks. On the other hand, a recovered clock 400 of <1200 Hz outputted from the clock recovery circuit 2 as shown in FIG. 3(B) is inputted to the input terminal of the D flip-flop 32. Here, D flip-flops 32 and 3
Since the output timings of 3 are shifted from each other by one cycle of the clock 300, when the output signal from the output terminal Q of the flip-flop 32 and the output signal from the output terminal 0 of the flip-flop 33 are ANDed by the AND circuit 35, As shown in FIG. 3(C), a pulse 1000 having a width of one period of the basic clock 300 synchronized with the rising edge of the reproduced clock 400 is obtained. This pulse is down counter 3
1 preset terminal PR and the load terminal LD of the shift register 34, the down counter 31 is preset by this pulse 1000, and at the same time, the shift register 34 inputs a 1 bit length pattern by this pulse 1000 to the input terminal D1. ~Load from D8. However, the timing to count the sign change point is ±178T.
When set to , the pattern to be loaded is 10000.
Set it to 001. Note that the king has a data length of 1 bit.

Therefore, the output signal 500 outputted from the output terminal Q8 of the shift register 34 is 1 in a portion within ±178T around the rising edge of the recovered clock, and 0 in other portions, as shown in FIG. 3(E). . In addition, the reproduction clock 4
00 has jitter, but according to the above configuration, the output signal from the shift register 34 can be a signal that becomes high level at a timing of approximately ±178T around the rising edge of the reproduced clock.

On the other hand, the received data 100 is input to the input terminal of the D flip-flop 41, but the D flip-flops 41 and 4
The output timings of the two output signals are shifted from each other by one cycle of the basic clock 300. Therefore, by ANDing the output signal of the output terminal Q of the flip-flop 41 and the output signal of the output terminal O of the flip-flop 42, a pulse 600 with a width of one period of the basic clock synchronized with the rising edge of the received data 100 is generated. is obtained. Similarly, flip-flop 41
When the output signal of the output terminal Q of the 7 lip-flop 42 is ANDed, the received data 100
A pulse 700 having a width of one cycle of the basic clock synchronized with the falling edge of is created. These pulses 600°7
00 is ORed by the OR circuit 45 and outputted to the selection circuit 5 as the output signal 1200 of the sign change point detection circuit 4. The data 500 output from the shift register 34 and the sign change point detection signal 1200 output from the OR circuit 45 are input to the AND circuit 51 of the sorting circuit 5, and the signal 800 which is the result of ANDing these signals is input to the counter. It is output to circuit 6. Similarly, the data 5 output from the shift register 34 is input to the AND circuit 52 of the selection circuit 5.
The inverted signal of 00 and the sign change point detection signal 1200 output from the OR circuit 45 are input, and a signal 900 that is the result of ANDing these signals is output to the counter circuit 6. Therefore, the sign change point detection signal 1200 is ±178
If the timing is within T, this signal 1200
passes through the AND circuit 51 and is input to one input terminal of the AND circuit 62 of the counter circuit 6. When the sign change point signal 1200 does not enter the timing within ±178T, this signal 1200 passes through the AND circuit 52 and becomes the signal 900, which is sent to the shift register 6 of the counter circuit 6.
It is input to the clear terminal CL of No. 1. As a result, when the reproduced clock 400 is not synchronized with the received data 100, the AND gate 52 outputs a signal 900 to clear the shift register 61. Here, the output terminal Q outputs the output of the flip 70 knob in the eighth stage of the shift register 61.
Assuming that the output signal from H is a bit synchronization detection signal 200, this signal 200 becomes zero when the reproduced clock 400 is not synchronized with the received data 100. Further, since this signal 200 is applied to the other input terminal of the AND circuit 62 via the inverter 63, "1" is normally applied to the other input terminal of the AND circuit 62.

When the rising edge of the recovered clock 400 is within ±1/8T of the sign change point of the received data, a signal 800 is input from the AND gate 51 to one input terminal of the AND circuit 62; The signal passes through and is input to the clock terminal CK of the shift register 61. Therefore, the contents of the shift register 61 are advanced by one stage to the output side by inputting the signal 800.

In this state, the shift register 61 receives 8 signals in succession.
times, and the first stage input of the shift register 61 is
Then, when the contents of the shift register 61 advance by eight stages, the output signal of the output terminal QH becomes 1. Similarly, since the output of the inverter 63 becomes zero, the AND circuit 62 is cut off and subsequent clock input to the shift register 61 is prohibited. After that, the reproduction clock is 4 within ±178T.
00 is synchronized with the received data 100, the bit synchronization detection signal 200, which is the output of the shift register 61, remains 1. When the synchronization deviates from within ±178T, the AND circuit 52 outputs a signal 900, the shift register 61 is cleared, and the bit synchronization detection signal 200 becomes O. From then on, the signal 200 remains O until the shift register 61 counts 8 steps. It remains as it is.

FIG. 4 is an operation timing chart when the reproduced clock is not synchronized with the received data. As shown in FIG. 4(F), when the signal 900 indicating the sign change point of the received data 100 is output from the AND circuit 52 at the timing A,
As shown in FIG. 4(G), the shift register 61 is reset and the signal 200 becomes O. In addition, Fig. 4 (A), (
B), (C), (D>.

(E) is received data 100. Sign change point detection signal 120
0, a reproduced clock 400, a data 5001 signal 800, respectively.

FIG. 5 is a timing chart when the reproduced clock is synchronized with the received data. As shown in FIG. 5(E), in the synchronized state, when the signal 800 indicating the sign change point of the received data 100 reaches the 8th pulse at the beginning timing, the 5th pulse
As shown in FIG. 5(G), the bit synchronization detection signal 200 output from the shift register 61 becomes 1, and as shown in FIG.
This shows that the received data 100 shown in FIG. 5 and the reproduced clock 400 shown in FIG. 5(C) are synchronized.

According to this embodiment, received data 100 and recovered clock 4
00 can be detected by the bit synchronization detection signal 200, the clock regeneration circuit 2
When the received data 100 and the recovered clock 400 are synchronized by the bit synchronization detection signal 200, the clock regeneration circuit 2 is switched to a longer pull-in characteristic, and the bits of the bit synchronization signal are By reducing the number of bit synchronization signals, the proportion of the bit synchronization signal in the transmission data can be reduced, and transmission and reception efficiency can be improved.

In particular, in data transmission in mobile communications, data may be sent and received using the 5 CPC method, and in this case, burst transmission is often performed. In such a system, a signal suddenly enters the receiver from an unmanned state, and its output rapidly changes from a state where noise is output to a state where received data is output. In such a system, transmission efficiency can be effectively improved by making the bit synchronization signal as short as possible.

In the above embodiment, the case where the timing width is ±178 units has been described, but by changing the configurations of the down counter 31 and the shift register 34, it is possible to set an arbitrary timing width. Further, the set count value of the counter circuit 6 can also be changed to an arbitrary value.

[Effects of the Invention] As described above, the bit synchronization detection circuit of the present invention has the advantage of being able to detect whether or not the recovered clock is synchronized with the received data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the bit synchronization detection circuit of the present invention, Fig. 2 is a block diagram showing a detailed example of Fig. 1, and Fig. 3 is the operation of the circuit shown in Fig. 2. FIG. 4 is an operation timing chart when the reproduced clock is not synchronized with received data, and FIG. 5 is an operation timing chart when the reproduced clock is synchronized with received data. 2... Clock regeneration circuit 3... Timing generation circuit 4... Sign change point detection circuit 5... Selection circuit 6
...Counter circuit agent Patent attorney Nori Chika Ken Shu Kanshu Sanno - 161

Claims (1)

[Claims] Regenerated clock generation means for generating a regenerated clock from input data; timing signal generation means for generating a timing signal specifying a predetermined time range around the rising edge of the regenerated clock; and a sign change point indicating a sign change point of input data. a sign change point generating means for generating a signal; and counting when the sign change point signal is within the predetermined time range, and initializing a count value when the sign change point signal is not within the predetermined time range; and synchronization detection means for generating a synchronization detection signal indicating that the input data and the reproduced clock are synchronized when the count value reaches a preset value. Bit synchronization detection circuit.