JPS63200221A - Automatic control circuit for clock pulse - Google Patents

Abstract

PURPOSE:To reduce the control manhour and to improve the control accuracy by providing a delay circuit and detecting the phase difference between the output of the delay circuit and the output of a programmable counter for selection of the delay value. CONSTITUTION:An external crystal oscillator 1 which produces a reference frequency is connected to an automatic clock pulse control circuit L consisting of an LSI and set into a CPU. Furthermore, the circuit L contains two control circuits A and B of the same constitution and sets a reference frequency at a desired level via an ordinary programmable counter 2 that can set freely an N-ary number with a program input. The phase comparators 3a-3b are provided to compare the phase of the output of the counter 2 with those of the outputs of delay circuits 7a-7b together with a drive circuit selecting decoder 4, the decoders 5a-5c, the up-down counters 6a-6b, etc. Then, a prescribed waveform is obtained by combining a pulse waveform of a frequency set by the counter 2 and the selection outputs A-C outputted from decoders 5a-5b.

Description

[Detailed Description of the Invention] [Summary] In an adjustment circuit that adjusts the timing of a system clock pulse used for synchronous operation of a computer, etc., a delay circuit that can obtain a phase delay amount of n stages, for example, 3 stages, is provided,
The clock pulse generation timing is automatically adjusted by counting amplifying or counting down the counter using the pulses generated by the phase difference.

[Industrial application field]

The present invention relates to an automatic clock pulse adjustment circuit, and more particularly to an adjustment circuit that can automatically adjust the generation timing of system clock pulses for synchronously operating computers and the like.

[Prior art and problems to be solved by the invention] Conventionally, the timing adjustment of clocks used to synchronize the operations of computers, etc. has been carried out by observing the waveform of a clock generation circuit built on a printed circuit board using a tester, oscilloscope, etc. However, it is adjusted at the factory. In this case, the delay adjustment of the output timing of the black/7ri is performed, for example, by changing the length of the cable. In this way, system malfunctions due to clock phase shifts are prevented.

However, such manual adjustment requires a lot of man-hours and is inefficient.

[Means for solving problems]

An object of the present invention is to provide a clock pulse automatic adjustment circuit that solves the above-mentioned problems, and its means include a programmable counter 2 that sets a reference frequency to a desired frequency, and a delay that provides n stages of phase delay. circuit? a, 7b, phase comparators 3a, 3b that detect the phase difference between the output of the programmable counter and the output of the delay circuit, and generate leading or lagging pulses corresponding to the phase difference; An amplifier down counter 6a that counts up or counts down according to the phase advance or phase delay pulse.
, 6b, and decoders 5a, 5 for selecting the delay amount of any one of the delay circuits according to the leading or slowing pulse.
b, and the clock pulse generation timing set by the programmable counter is automatically adjusted.

[For production]

For example, when adjusting the generation timing of system clock pulses, for example, a delay circuit that can provide three stages of phase delay? a and 7b are provided, the phase difference between the output of the programmable counter and the output of the delay circuit is detected, the up/down counter is driven by a leading or slowing pulse corresponding to the phase difference, and the clock pulse is generated by selecting the amount of delay. Adjust timing automatically.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the clock pulse automatic adjustment circuit according to the present invention, and FIGS.
3 is a signal timing chart at each point in the figure.

In FIG. 1, reference numeral 1 indicates an externally attached crystal oscillator that generates a reference frequency. L is a clock pulse automatic adjustment circuit (hereinafter referred to as adjustment circuit) according to the present invention, which is constructed from a large-scale integrated circuit (LSI) and is incorporated inside a computer, for example, inside a central processing unit (CPU). The adjustment circuit is composed of two adjustment circuits A and B, and the internal structure is as follows. That is, 2 is a general programmable counter whose N-ary number can be freely set by inputting a program and sets the reference frequency to a desired frequency, and 3a and 3b are the outputs of the programmable counter 2 and the output of a delay circuit to be described later. A phase comparator that compares the phases of and outputs a pulse (4) based on the phase difference.
is a decoder for selecting one of two adjustment circuits, 5a
and 5b is a decoder for an up/down counter to be described later, which selects one of the delay means;
6a and 6b are up/down counters that count up or count down using clocks based on phase differences; 7a and 7b are delay circuits in which a three-stage delay can be obtained by a combination of delay elements No. 1 to No. 6;

The operation of this circuit in such a configuration will be explained with reference to FIG. The output pulse period of the crystal oscillator 1 is converted into a desired period by a programmable counter 2. Pulse D0 in FIGS. 2(a) to 2(c) is a pulse waveform with a cycle set by the programmable counter 2.

By combining this waveform with the selected outputs A, B, and C output by the decoders 5a and 5b, waveforms as shown in (a) to (c) are obtained. That is, (a) is the case when the selection signal A is output, and the delay gate 1 of one stage of the delay circuit 7a
is selected and the amount of phase delay is Da. (b) shows the case where selection signal B is output, and there are two stages of delay gates 2.
3 is selected and the amount of delay is Db. (C) shows the case where the selection signal C is output, and the three stages of delay gates 4, 5.6 are selected and the amount of delay is Dc. A programmable counter output Do is commonly input to one input of the delay gates 1°2.4.

In (a), the phase of the clock Do is shifted by Da in the leading direction, and the phase comparators 3a and 3b generate a leading pulse of U only in the section where the phase difference occurs. This pulse becomes a count-up clock.

In (b), the phase comparator does not generate a phase difference pulse because the clock Do is synchronized with Do with a phase shift of Db.

In (C), the phase of the clock DO is shifted by Dc in the lag direction, and the phase comparator generates a lag pulse of ■ only in the section where the phase difference occurs.

This pulse becomes a countdown clock.

In this way, a phase-adjusted clock pulse can be obtained from the output terminal OUT1. Furthermore, since the lower stage circuit operates in exactly the same manner, a description thereof will be omitted.

In this case, if the clock B has a period different from the period of the A clock in the upper stage,
It is also possible to obtain a clock.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to automatically adjust the deviation in the timing of clock pulse generation, thereby reducing the number of adjustment steps and improving the adjustment accuracy.

[Brief explanation of the drawing]

FIG. 1 is a clock pulse automatic adjustment circuit according to the present invention, and FIG. 2 is a signal timing chart at each point in the circuit shown in FIG. (Explanation of symbols) 1...Crystal oscillator 2...Programmable counter 3a, 3b...Phase comparator 4...Adjustment circuit selection decoder 5a, 5b...Decoder 6a, 6b...Up/down Counters 7a, 7b...
・Delay circuit One embodiment of the present invention Circuit diagram Fig. 1 V □ V □ Fig. 1 Signal timing chart of the circuit Fig. 2

Claims (1)

[Claims] 1. A programmable counter (2) that sets the reference frequency to a desired frequency, delay means (7a, 7b) that can obtain n stages of phase delay, and a phase difference between the output of the programmable counter and the output of the delay means. A phase comparator (
3a, 3b), an up/down counter (6a, 6b) that counts up or counts down in accordance with the leading or lagging pulse of the phase comparator; An automatic clock pulse adjustment circuit comprising a decoder (5a, 5b) for selecting one of the delay amounts, and automatically adjusting the generation timing of the clock pulse set by the programmable counter.