JPS63199340U

JPS63199340U -

Info

Publication number: JPS63199340U
Application number: JP8763487U
Authority: JP
Priority date: 1987-06-05
Filing date: 1987-06-05
Publication date: 1988-12-22

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による加算回路の
構成を示すブロツク図、第２図は従来の加算回路
の構成を示すブロツク図、第３図は動作を説明す
るためのタイミングチヤートである。１〜９，１１〜１９…入力端子、２０，２１，
２２，２４，３１，３２，３３…ラツチ回路、２
３…アンド回路、２６，２８，３０…４ビツトの
全加算器、４１〜４９…出力端子。なお、図中の
同一符号は同一または相当部分を示す。 FIG. 1 is a block diagram showing the structure of an adder circuit according to an embodiment of the invention, FIG. 2 is a block diagram showing the structure of a conventional adder circuit, and FIG. 3 is a timing chart for explaining the operation. 1-9, 11-19...input terminal, 20, 21,
22, 24, 31, 32, 33...Latch circuit, 2
3...AND circuit, 26, 28, 30...4-bit full adder, 41-49...output terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

補正昭６２．１１．１６実用新案登録請求の範囲を次のように補正する
。Amendment November 16, 1986 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】語長が４ｎ＋１ビツト（ｎ＝１，２，…）の２
つの入力信号を加算し、その出力信号を１／２倍
して出力するように構成した加算回路において、
上記語長が４ｎ＋１ビツトの２つの入力信号の最
下位ビツトから順に第１ビツト、第２ビツト、…
第４ｎ＋１ビツトとして２つの入力信号の第１ビ
ツトを入力するアンド回路と、上記２つの入力信
号の第２ビツトから第４ｎ＋１ビツトを入力する
ｎ個の４ビツトの全加算器とを備え、上記ｎ個の
全加算器それぞれの桁上げ信号を各全加算器の上
位の全加算器の桁上げ入力に供給するとともに、
上記アンド回路の出力信号を上記ｎ個の全加算器
の最下位の全加算器の桁上げ入力に供給して、上
記ｎ個の全加算器の出力信号と最上位の桁上げ信
号とを出力するように構成したことを特徴とする
加算回路。[Scope of claim for utility model registration] 2 with a word length of 4n+1 bits (n=1, 2,...)
In an adder circuit configured to add two input signals and output the output signal after multiplying it by 1/2,
The first bit , the second bit,...
It is provided with an AND circuit that inputs the first bit of the two input signals as the 4n+1 bit, and n 4-bit full adders that input the second bit to the 4n+1 bit of the two input signals, and The carry signal of each full adder is supplied to the carry input of the upper full adder of each full adder, and
The output signal of the AND circuit is supplied to the carry input of the lowest full adder of the n full adders, and the output signal of the n full adders and the highest carry signal are output. An adder circuit characterized in that it is configured to.

Claims

[Scope of utility model registration request]

2 with a word length of 4n+1 bits (n=1, 2,...)
In an adder circuit configured to add two input signals and output the resulting output signal after multiplying it by 1/2,
An AND circuit which inputs the first bit of the two input signals having a word length of 4n+1 bits as the 1st bit, 2nd bit, . . . 4n+1 bit starting from the least significant bit of the two input signals; Input the 2nd to 4n+1 bits n
4-bit full adders, and supplies the carry signal of each of the n full adders to the carry input of the upper full adder of each full adder, and also supplies the output signal of the AND circuit. is supplied to the carry input of the lowest full adder of the n full adders to output the output signal of the n full adders and the highest carry signal. An adder circuit featuring: