JPS63197089A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed-up the reading action of a static type RAM by connecting a complementary common data line with a sense amplifier through the gate of input MOSFET pair and executing a feedback amplification by differential MOSFET pair, etc., connected in a cross. CONSTITUTION:The sense amplifier SA0 is constituted of an N channel MOSFET and a P channel MOSFET in a parallel form. And their gates are provided in serial forms with two pairs of parallel transmission gates MOSFET Q13 and Q36, Q15 and Q37 connected to the non-inversion signal line and inver sion signal line of the complementary common data line and their gates and drains are connected in a cross with each other so as to include the differential MOSFET Q14 and Q16. Thus, the amplifying action of the sense amplifier SA0 is made to get the speed-up and the operating current of the SA0 can be suppressed, so that the speed-up of reading actions of the static type RAM, etc., can be enhanced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, for example, a 0MO3 (complementary MO3) static type RAM.
(Random Access Memory).

(Prior Art) There is a CMOS static RAM whose memory array is composed of static memory cells consisting of N-channel MO3FETs and whose peripheral circuits are composed of OMO3, thereby achieving higher speed and lower power consumption.

As an amplifier circuit, ie, a sense amplifier, for such a CMOS static RAM, current mirror type differential amplifier circuits as shown in FIG. 6 are used singly or in symmetrical combinations.

Regarding such static type RAM and current mirror type differential amplifier circuit, for example, "Nikkei Electronics" published by Nikkei McGraw-Hill, December 30, 1985.
It is described on pages 117 to 145 of .

[Problem that the invention seeks to solve]

In FIG. 6, the sense amplifier SAO of the static RAM has its gate connected to the non-inverted signal line CDO and the inverted signal line CDO of the complementary common data line, respectively.
Contains channel type differential MO3FETs Q32 and Q33. Among these, a P-channel MO3FET is connected between the train of MO3FETQ32 and the circuit power supply voltage Vcc.
A P-channel MO3FET Q52 whose gate and drain are commonly connected is provided between the drain of the MO3FET Q33 and the power supply voltage Vcc of the circuit. These MO3FETQ51 and Q52 are
Furthermore, their gates are connected in common, forming a current mirror configuration and acting as an active load. Differential MO3FE
An N-channel MO3FET Q34, which receives a timing signal φsa at its gate, is provided between the commonly connected sources of TQ32 and Q33 and the ground potential of the circuit.

The MO3FET Q51 also includes a P-channel MO3FE which receives the timing signal φsa at its gate.
TQ50 are provided in parallel configuration. MO3FETQ32
The drain voltage of is inverted by an inverter circuit N8 and outputted as a non-inverted output signal SDO of this sense amplifier SAO.

The complementary common data lines CDO and CDO are static type R.
In the non-selected state of AM, it is short-circuited by, for example, a P-channel MO3FET Q49 for equalization, and is set to a half precharge level of about 1/2 of the power supply voltage Vcc. At this time, since MO3FETQ34 is turned off and MO3FETQ50 is turned on, the sense amplifier SAO is rendered inactive, and the differential MO3FE
The drain voltages of TQ32 and Q33 are power supply voltage VCC and power supply voltage Vcc-VTHP (VTHP is the threshold voltage of MO3FETQ49), respectively.

Static type RAM becomes selected state and MO3FETQ
34 is turned on, the sense amplifier SAO becomes operational, and the drain voltages of the differential MO3FETs Q32 and Q33 are connected to the read signal transmitted from the selected memory cell via the complementary common data line CDO and π1. The level will be as per the following. That is, when storage data of logic "0" is output from the selected memory cell, the level of the inverted signal IJI CDO becomes higher than the level of the non-inverted signal line CDO. Therefore, the conductance of MO3FETQ33 is increased and the conductance of MO3FETQ32 is decreased. I want to, MO3F
The drain voltage of ETQ33 decreases, which causes the MO
The conductance of 3FETQ52 is increased. In addition, as the gate voltage of MO3FETQ52 decreases,
The conductance of MO3FETQ51 is also increased, and M
The drain voltage of O3FETQ32 increases. Therefore, the non-inverted output signal SDO of the sense amplifier SAO becomes a logic low level. On the other hand, when storage data of logic "1" is output from the selected memory cell, the level of the non-inverted signal line CDO becomes higher than the level of the inverted signal line CDO. Therefore, the conductance of MO3FETQ33 is reduced, and conversely, the conductance of MO3FETQ32 is increased. This allows MO3FETQ33
The drain voltage of MO3FETQ52 increases, and the gate of MO3FETQ52 becomes the drain voltage. Also, MO3FETQ52
As the gate voltage of MO3FETQ51 increases, the conductance of MO3FETQ51 also decreases, and the drain voltage of MO3FETQ32 decreases.

Therefore, the non-inverted output signal SD of the sense amplifier SAO
O becomes a logic high level.

As described above, the sense amplifier SAO in FIG. 6 uses the differential MO3FETQ3 according to the read signal from the memory cell.
3, the change in the drain current of M
By transmitting through O3FETQ52 and Q51,
Performs relatively high-speed amplification operation. However, as described above, when storage data of logic "O" is output from the selected memory cell, MO3FETs Q33 and Q52 are simultaneously turned on. For this reason, these MO3FETs
A relatively large operating current flows through Q33 and Q52. This significantly increases power consumption in a static RAM that inputs and outputs stored data in parallel in units of, for example, 16 bits or 32 pins. In addition, when trying to limit the operating current of the sense amplifier to deal with this, MO3FETQ33 and Q5
It is necessary to reduce the conductance of 2 to some extent, which impedes the speeding up of the read operation of the static RAM.

It is an object of the present invention to provide a semiconductor memory device such as a static RAM in which a sense amplifier has higher speed and lower power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a sense amplifier such as a static RAM includes a pair of input MOSFETs whose gates are respectively coupled to a non-inverting signal line and an inverting signal line of a complementary common data line;
These input MOSFET pairs are provided in series, and their gates and drains are cross-coupled with each other to constitute a positive feedback amplifier circuit, and the conductance thereof is changed to be complementary to the input MOSFET pair. Motion M
A pair of OSFETs is provided.

[For production]

According to the above means, by coupling the complementary common data line and the sense amplifier through the gates of the input MOSFET pair, the load on the complementary common data line is reduced, and
By performing feedback amplification using a pair of cross-connected differential MOSFETs, etc., the amplification operation of the sense amplifier can be made faster. In addition, input MOS FET pair and differential MO5FET
By turning on the sense amplifiers in a complementary manner, the operating current of the sense amplifier can be reduced, and its power consumption can be reduced.

[Embodiment 1] FIG. 5 shows a circuit block diagram of an embodiment of a CMOS static type RAM to which the present invention is applied. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known CMO3 integrated circuit manufacturing technique. In the following figures, MOSFETs with arrows added to the channel (bank gate) portions are P-channel type, and are distinguished from N-channel MO3FETs with no arrows added.

The static type RAM of this embodiment has a function of simultaneously inputting and outputting 16-bit storage data in parallel, although this is not particularly limited. Therefore, 16 memory arrays M-ARYO-M-AR are arranged corresponding to these stored data.
YI5 is provided, and column switches cswo to C3W15 are provided corresponding to each of these memory arrays.
, sense amplifier SAO~5A15, light amplifier WAO
~WA15, data output buffer DOBO~DOB 1
5 and data input cover sofas DIBO to DIB15 are provided. FIG. 5 exemplifies the memory array M-ARYO corresponding to the first bit of stored data, the column switch cswo, the sense amplifier SAO, the write amplifier WAO, the data output buffer DOBO, and the data input cover sofa DIBO. is shown.

In FIG. 5, the memory array M-ARYO is m+1
main word lines WO to Wm and n+1 sets of complementary data lines D
It is composed of (m+1)×(n+1) memory cells MC arranged at the intersections of O.r-T to pn-T and their word lines and complementary data lines.

As exemplarily shown in FIG. 5, each memory cell MC has a basic configuration of N-channel type MO3FETs Q1 and O2 whose respective gates and drains are cross-coupled with each other. Although not particularly limited, the above MO3F
High resistances R1 and R2 formed of polysilicon (polycrystalline silicon) layers are provided between the drains of ETQI and O2 and the circuit power supply voltage Vcc, respectively. Further, the sources of MO3FETQI and O2 are commonly connected and further coupled to the ground potential of the circuit. As a result, M
O3FETQI and O2, together with high resistances R1 and R2, constitute a flip-flop that serves as a storage element of a static RAM.

MO3F which is the input/output node of this flip-flop
The drains of ETQI and O2 are respectively coupled to corresponding complementary data lines DO.1- through N-channel type transmission gates MO3FETQ3 and O4. Also,
The gates of these transmission gates MO3FETQ3 and O4 are commonly connected to the corresponding word line WO.

All of the other memory cells MC have the same circuit configuration, and are similarly arranged in a matrix by being coupled to the corresponding complementary data lines and word lines to form the memory array M-ARYO. That is, the input/output nodes of the memory cells MC arranged in the same column are coupled under the corresponding complementary data lines DO•1 to Dn-σ through the corresponding transmission gate MO3FET. In addition, the transmission gate MO3FE of the memory cell MC arranged in the same row
The gates of T are commonly connected to corresponding word lines WO to Wm, respectively.

The load resistance R1 of each memory cell MC is a MOS FET
When O2 is turned on and MO3FETQI is turned off, that is, when the memory cell MC holds the stored data of logic "1", MO3FE"l"O2
The resistance value is set to be high enough to replenish the M product charge of the gate capacitance so that the gate voltage of the gate does not fall below the threshold voltage due to leakage current. Similarly, when MO3FETQI is turned on, the load resistance R2 of each memory cell MC is
FF: Gate capacitance is set to prevent the gate voltage of MO3FETQI from falling below the threshold voltage due to leakage current when TQ2 is in the off state, that is, when the memory cell MC holds stored data of logic "0". The resistance value is high enough to replenish the accumulated charge. These load resistors R1 and R2 are made of polysilicon layers instead of
P-channel MO with relatively small conductance
It may also use 3FET.

Complementary data line DO/DO= of memory array M-ARYO
Between Dn-Dn and the circuit power supply voltage Vcc, there is an N-channel load M, as exemplarily shown in FIG.
OS FET pairs Q5, Q6 to Q7, O8 are provided.

Word lines WO to Wm are coupled to an X address decoder XDCH. This X address decoder XDCH has
Complementary internal address signal a from address buffer XADB
xQ ~ axi (here, for example, external address signal AX
The internal address signal axQ having the same phase as O and the internal address signal axQ having the opposite phase are collectively expressed as a complementary internal address signal axQ. (same below) will be supplied. X address decoder
DCR receives these complementary internal address signals axQ to ax
i is decoded, and one word line specified by the X address signals AXO to AXi is set to a high level selected state. The X address decoder XDCR is brought into operation by a timing signal φce supplied from the timing control circuit TC when this static type RAM is brought into the selected state. As a result, static type RAM
The power consumption in the non-selected state is reduced.

The X address bus function XADB is the external terminal AXO to AX.
X address signals AXO to AXi supplied via i are taken in, and the complementary internal address signal a
x Qx, a x i is formed to form an X address decoder
Supply to DCR.

On the other hand, complementary data input-1 of memory array M-ARYO
-C3WO corresponding switch MO3FET pair Q9・Q
It is appropriately connected to complementary common data lines CDO and CDO via IO to Qll and Q12.

These switches MO3FET pair Q9・QIO~Qll
・The gates of Q12 are connected in common, and the corresponding data line selection signal YO~ is sent from the Y address decoder YDCR.
Yn is supplied.

Y address decoder YDCR is Y address buffer Y
Complementary internal address signals ayo to yj supplied from ADB are decoded to form data line selection signals YO to Yn for selecting a - set of complementary data lines and connecting them to complementary common data lines CDO and CD1. This Y address decoder YDCR is similar to the X address decoder XDCR,
It is selectively brought into operation according to the timing signal φce supplied from the timing control circuit TC.

Although not particularly limited, the above-mentioned X address decoder XDCR
, X address buffer XADB, Y address decoder Y
DCR, Y address buffer YADB, and timing control circuit TC to be described later are arranged in 16 memory arrays M-AR.
YO~M-ARYI5 and column switch cswo~C
Commonly used for 3W15.

A sense amplifier S is connected to the complementary common data line CDO/Hyakuga 1.
The input terminals of the AO are coupled, and the light amplifier W
The output terminals of AO are coupled iL. The output terminal of sense amplifier SAO is coupled to the input terminal of data output buffer DOBO, and the input terminal A of write amplifier WAO is coupled to the output terminal of data input buffer DIBO.

As described later, the sense amplifier SAO is selectively activated in accordance with the timing signal φsa supplied from the timing control circuit TC, and the sense amplifier SAO
The read signal transmitted from the terminal via the complementary common data lines CDO and CDO is biased. The output signal of sense amplifier SAO is transmitted to data output buffer DOBO.

The specific circuit configuration and operation of this sense amplifier SAO will be explained in detail later.

The data output buffer DOBO is static type RAM.
In the read operation mode, the timing control circuit T
It is selectively brought into operation according to a timing signal φoe supplied from C. The data output buffer DOBO is
The memory cell read signal output from the sense amplifier SAO is further amplified and sent to an external device via the input/output terminal D100. The output of the data output buffer DOBO is in a high impedance state in the non-selected state of the static RAM and in the write operation mode when the timing signal φoe is at a low level.

On the other hand, the data input buffer DIBO has an input/output terminal D1 in the write operation mode of the static RAM.
Write data supplied from an external device via 00 is made into a complementary write signal and transmitted to the write amplifier WAO.

The write amplifier WAO is selectively brought into operation according to the timing signal φ-e supplied from the timing control circuit TC in the write operation mode of the static RAM. Write amplifier WAO supplies a write current according to a complementary write signal supplied via data input buffer DIBQ to complementary common data lines CD0-σ1.

The output of the write amplifier WAO is in a high impedance state in the non-selected state of the static RAM and in the read operation mode when the timing signal φwe is at a low level.

The timing control circuit TC uses a chip selection signal supplied as a control signal from the outside.
The various timing signals mentioned above are formed based on E and the output enable signal σπ, and are supplied to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of a sense amplifier SAO of a CMOS static RAM to which the present invention is applied. In addition to this sense amplifier SAO, the static RAM of this embodiment also includes a sense amplifier SAO.
15 sense amplifiers SAI with the same circuit configuration as
.about.5A15 are provided corresponding to each bit of storage data. FIG. 1 exemplarily shows a part of the circuit of the sense amplifier SAO, the memory array M-ARYo, and the column switch cswo related to the sense amplifier SAO.

In FIG. 1, the non-inverted signal line CD of the complementary common data line
O is an N-channel type input MO3FETQ13 (first
MOSFET Q37 (fifth MOSFET) and P-channel type input MOSFET Q37 (fifth MOSFET).
FET). In addition, the inverted signal line σ1 of the complementary common data line similarly connects an N-channel type input MOSFETQ15 (second MOSFET) and a P-channel type input MOSFETQ36 (sixth MOSFET).
OSFET> gate. MO3FETQ1
3 and Q36 and the sources and drains of MO3FETQ15 and Q37 are commonly coupled, respectively, and the parallel transmission gate) M
Functions as an OSFET.

The complementary common data line CDO・101 is connected to the memory array M-AR via the switch MO3FET pair Q9・QIO of the column switch cswo and the complementary data line DO・lower 1.
YO memory cell MC is coupled. Further, although not particularly limited, an equalizing MO3FET Q35 receiving a timing signal φsa at its gate is provided between the non-inverted signal line CDO and the inverted signal line DO of the complementary common data line. These timing signals φs and lI are set to low level when the static RAM is not selected, and when the static RAM is in the selected state, the read signal from the designated memory cell is complementary to the 3m data lines CDO and CD. It is set to a logic high level at the timing established on completion of the signal. MO3FETQ35 is turned on when the static type RAM is not selected, where the timing signal ψsa/l<logic low level, and the complementary common data lines CDO and CD0- are switched on and off. As a result, the standby level of the image signal line of the common y-ta line is
It is a half-charge level of about 1/2 of the power supply voltage Vcc.

Parallel transmission game of sense amplifier SAO) M OS FE
TQ13 and Q36 are 1. One of them is coupled to the power supply voltage ■cc of the I-ζ circuit, and the other is an N-channel MO3
The drain of Fn"I"Q14 is connected.

Similarly, parallel transmission gate MO3FETQI5・Q37
is coupled at one end to the circuit power supply voltage Vcc, and at the other end to the drain of the N-channel MO3FET Q16. These MO3FETQ14 and Q1
6 acts as a differential MO3FET constituting a positive feedback amplifier circuit by having its sources commonly connected and its gates and drains cross-connected to each other. Differential MO3F
The commonly connected sources of ETQ14 and Q16 are coupled to the ground potential of the circuit via an N-channel MO3FETQI7. The gate of this MO3FET QI 7 is supplied with the timing signal φsa.

Further, the drains of the differential MO3FETs QI4 and Q16 are coupled to the input terminals of the output inverter circuits N1 and N2, respectively. The output signals of inverter circuits N1 and N2 are respectively inverted output signals S of this sense amplifier SAO.
DO and the non-inverted output signal SDO are supplied to the corresponding data output buffer DOBO.

Next, an outline of the operation of the sense amplifier SAO of this CMO3 static type RAM will be explained along the circuit diagram of FIG.

In the non-selected state of the static RAM, the timing signal φsa is set to a logic low level, so the MO3F
ETQI 7 is in the off state and the differential MO3FETQI
The sense amplifier SAO, whose basic configuration is 4.Q16, is put in a non-operating state. Also, as mentioned above, equalize M
The O3FET Q35 is turned on, and the complementary common data lines CD0-0 are brought to a half precharge level of about 1/2 of the power supply voltage Vcc. With MO3FETQI 7 in the off state, differential MO3FETQI 4 and Q16
The drain of is in a floating state, but since the complementary common data lines CDO and σπ1 are each at a half precharge level, both P-channel MO3FETs Q36 and Q37 forming the parallel transmission gate are in an on state. Therefore, the drain voltages of the differential MO3FETs Q14 and Q16 in the standby state of the sense amplifier SAO are almost at the high level of the power supply voltage Vcc.

When the static RAM is selected and the timing signal φSa is set to a logic high level, equalization M(
JSFETQ35 is turned off, and M OS F E
TQ 17 is turned on. Also, complementary common data
A read signal from the memory cell MC is transmitted to the column switch C3WO via the 103F B'I' pair Q9 and Q10.

In order to speed up the read operation of the static RAM, this read signal is limited to a relatively small (g amplitude) centered on the half precharge level.

For example, when storage data of logic "0" is output from the memory cell MC of the memory array MARYO, the level of the inverted signal line CDO of the complementary common data line rises,
The level of the non-inverted signal line CDO decreases accordingly. As a result, the parallel transmission gate MO3FE of the sense amplifier SAO
The conductances of both TQ15 and Q37 are increased, and conversely, the conductances of the parallel transmission gates MO3FETQ13 and Q36 are decreased. On the other hand, memory array M-
When storage data of logic "1" is output from the memory cell MC of ARYO, the non-inverted signal line C of the complementary common data line
The level of DO increases and the level of inverted signal line CDO decreases by that amount. As a result, the conductance of both the parallel transmission gates MO3FETQ13 and Q36 of the sense amplifier SAO is increased, and conversely, the conductance of the parallel transmission gate MO3FETQ13 and Q36 of the sense amplifier SAO is increased.
The conductance of TQI 5 and Q37 is reduced.

Differential MO3FETQ14/Q16 of sense amplifier SAO
When the MO3FET QI 7 is turned on, its source becomes the ground potential level of the circuit. As mentioned above, in the non-selected state of the static RAM, the differential MO
The drain voltage of 3FETQI4·Q16 is set to high level. For this reason, the differential MO3FETQ14/Q16
turns on at the same time as MO3FETQ17 turns on, and its drain voltage begins to drop.

However, the parallel transmission gate MO3FETQI3・Q3
Since the conductance changes of QI 6 and Q15 and Q37 differ according to the read signal output from the memory cell MC, the drain voltages of the differential MO3FETs QI 4 and Q16 slightly differ according to the read signal. That is, when a read signal of logic "0" is output from the memory cell MC of the memory array M-ARYO, the coni/dugtance of the parallel transmission gate MO3FETQI3 and Q36 is reduced, so that the corresponding differential MO3FETQI4 is output.
The drain voltage of M drops rapidly, and the parallel transmission gate M
By increasing the conductance of the O3FETs QI5 and Q37, the low T of the 1'' line voltage of the corresponding differential MO3FETQi6 becomes relatively small. This level difference is determined by the differential MO3FETQ1 that constitutes the positive feedback amplifier circuit.
It will be rapidly expanded by 4/Q16. As a result, the drain voltage of the differential M○5FETQ16 becomes a logic high level like the power supply voltage VCC, and the drain voltage of the differential M○5FETQ16 becomes a logic high level like the power supply voltage VCC
14 is almost completely turned on. Also, differential MOSF
The drain voltage of ETQI4 becomes a logic low level like the ground potential of the circuit, and MO3FETQ16 is turned off. Therefore, the output signal of the inverter circuit N1, ie, the inverted output signal SD of the sense amplifier SAO, becomes a logic high level, and the output signal of the inverter circuit N2, ie, the non-inverted output signal SDO of the sense amplifier SAO, becomes a logic low level.

On the other hand, when a read signal of logic "1" is output from the memory cell MC of the memory array M-ARYO, the conductance of the parallel transmission gates MO3FETQI 5 and Q37 is reduced, so that the corresponding differential MO3FETQI
The drain voltage of 6 drops rapidly, and the parallel transmission gate)
By increasing the conductance of MO3FETQI3 and Q36, the drop in the drain voltage of the corresponding differential MO3FETQI4 becomes relatively small. This level difference is rapidly expanded by the differential MO3FETQI4 and Q16, and as a result, the differential MO3FETQ1
6 drain voltage becomes logic low level, MO3FE
TQ14 is turned off. Also, differential MO3FETQ
The drain voltage of I4 becomes a logic high level, and MO3
FETQI 6 is almost completely turned on. Therefore, the output signal of the inverter circuit N1, that is, the inverted output signal SDO of the sense amplifier SAO, becomes a logic low level, and the output signal of the inverter circuit N2, that is, the non-inverted output signal SDO of the sense amplifier S80, becomes a logic high level. .

As described above, the sense amplifier SAO of this embodiment is composed of an N-channel MOS FET and a P-channel MO3FET in parallel, and the gates of each are coupled to the non-inverting signal line and the inverting signal line of the complementary common data line. Two sets of parallel transmission games) MOS FET Q
13.Q36 and Q15.Q37, and a differential MO3FET QI which is provided in series with these parallel transmission gates MOS FET and whose gates and drains are cross-connected to each other to form a positive feedback amplifier circuit.
4.Includes Q16.

According to the read signal output from memory cell MC,
The conductance of the parallel transmission gate MOS FET is changed at a relatively high speed, and a level difference occurs between the drain voltages of Q14 and Q16. This level difference is rapidly expanded and amplified by differential MO5FETs QI4 and Q16. Therefore, the read operation of the static RAM is accelerated. Further, since the conductances of the parallel transmission gate MO3FET and the differential MO3FET are finally changed in a complementary manner, the operating current can be reduced and power consumption can be reduced.

Needless to say, a single level change on the complementary common data line CD0- is transmitted to the sense amplifier SAO through the gate of the parallel transmission gate MOSFET, and the load on the complementary common data line CDO·Er1 is reduced. Also, differential MO3
The drain voltages of FETQI4 and Q16 are output via inverter circuits N1 and N2, respectively, and are outputted to the differential MO
The load on 3FETQI4 and Q16 is also reduced. Therefore, the read operation of the static RAM can be made even faster.

[Embodiment 2] FIG. 2 shows a circuit diagram of a second embodiment of a sense amplifier SAO of a CMOS static type RAM to which the present invention is applied. In the following embodiments, the configuration and operation of circuit blocks (not shown) such as a memory array are the same as in the first embodiment described above, and their explanation will be omitted. Also,
MO for equalization provided in sense amplifier SAO
SFET is omitted.

In the sense amplifier SAO of this embodiment, parallel transmission gate MO3FETQI8・Q39 and Q20・Q41
and differential MO3FET QI 9 and Q21 are the parallel transmission gate MO3FET of the sense amplifier SAO of the above-mentioned embodiment 1.
QI 3/Q36 and Q15/Q37 and differential MO3FE
It corresponds to TQI 4 and Q16 respectively, and their functions and operations are the same. Sense amplifier SAO of this embodiment
Now, P-channel MO3FETQ38 (7th
MOSFET) is provided. Similarly, differential MO
Parallel transmission gate MO3FETQ with 3FETQ21
A P-channel MOSFET Q40 (eighth MOSFET) is provided in series with MOSFET 20 and Q41 sandwiched therebetween. The gates of these MO3FETs Q38 and Q40 are connected to the respective differential MO3FETs QI 9
and commonly connected to the gates of Q21. As a result, M
O3FETQ38 and Q19 are parallel transmission gate MO3
By turning on FETQI8 and Q39, C
Functions as a MOS inverter circuit.

Similarly, MO3FETs Q40 and Q21 function as a CMOS inverter circuit by turning on the parallel transmission gates MO3FETs Q20 and Q41. These two sets of CMOS inverter circuits are
By cross-coupling the gates and drains of QI9 and Q21, their input terminals and output terminals are cross-coupled, and they function as a positive feedback amplifier circuit with a relatively large DC amplification factor.

As in the case of the first embodiment described above, the non-inverted signal line CDO of the complementary common data line is supplied to the gates of MO3FETQI8 and Q41 that constitute the parallel transmission gate of the sense amplifier SAO, and the inverted signal line 6 is supplied to the gates of MO3FETQ20. and the gates of Q39, respectively. Also, differential M
Between the commonly connected sources of O3FETQI9 and Q21 and the circuit ground potential, there is an N-channel MO3FETQ22 whose gate receives the above-mentioned timing signal ψsa.
or can be established.

Furthermore, between the drain of the differential MOS FETQ 19 and the power supply voltage Vcc of the subject, a P-channel type MO3FETQ42 (ninth MOSFET) for pre-certification is provided which receives the timing signal φsa on its gate. Similarly, the tray I of the differential MO3FETQ2
and the circuit power supply voltage Vcc, there is a P-channel type presetting MOS FET Q43 (10th MOS
FET> is provided. MO3I for these presets
・ETQ42 and Q43 are turned on in the static type RA fviO selection state where the timing signal φsa is at a logic low level, and the differential MO3FETQ
19.The drain voltage of Q21 is set to a high level like the circuit power supply voltage Vcc. Differential MO3FETQ19・Q
The drain voltage of 21 is inverted by correspondingly provided inverter circuits N3 and N4, and the inverted output signal SDO and non-inverted output signal SDO of this sense amplifier SAO
is supplied to the data output buffer DOBO.

Next, an outline of the operation of the sense amplifier SAO of this embodiment will be explained along the circuit diagram of FIG.

In the non-selected state of the static RAM, the timing signal φsa is set to a logic low level, so the MO3F
ETQ22 is in the off state, and the differential MO3FETQI
The sense amplifier SAO, whose basic configuration is 9.Q21, is put in a non-operating state. In addition, complementary common data lines CD0-CD
0 is a half precharge level of approximately 1/2 of the power supply voltage Vcc.

By turning off MO3FETQ22, the differential MO3
The drains of FETQI9 and Q21 are in a floating state, but the drains of MO3FETQ42 and Q4 for presetting are
3 are both in the on state, static type RAM
Differential MOSFET Q19 and Q21 in the non-selected state
The drain voltage is almost at the high level of the power supply voltage Vcc. In addition, the drain voltages of the differential MO3FETs QI9 and Q21 become high level, so that the MOS FET
T Q 38 and Q40 are almost in an off state.

When the static type RAM is selected and the timing signal φsa is set to logic high level, the preset M
O3FETQ42 and Q43 are turned off, and MO3
FETQ22 is turned on. Further, a read signal from the memory cell MC is transmitted to the complementary common data line CDO·σ■].

As in the case of the first embodiment described above, the parallel transmission gates MO3FETQI8, Q39 and 0.
The conductance of 20.Q41 is changed according to this read signal.

That is, 1. Memory cell M of memory array M-ARYO
When storage data of logic "0" is output from C, the level of Tτ increases on the inverted signal line of the complementary common data line, and the level of the non-inverted signal line CDO decreases by that amount. As a result, the parallel transmission gate MO3FET of the sense amplifier SAO
The conductances of Q20 and Q41 are both increased,
Conversely, the conductance of the parallel transmission gates MO3FETQI8 and Q39 is reduced. On the other hand, memory array M-
When storage data of logic "1" is output from the memory cell MC of ARYO, the non-inverted signal line C of the complementary common data line
The level of DO increases, and the level of inverted signal line σDO decreases by that amount. As a result, the conductance of both the parallel transmission gates MO3FETQ18 and Q39 of the sense amplifier SAO is increased, and conversely, the conductance of the parallel transmission gate MO3FETQ18 and Q39 of the sense amplifier SAO is increased.
The conductance of TQ20 and Q41 is reduced.

Differential MO3FETQI 9/Q2 of sense amplifier SAO
1, when the MO3FET Q22 is turned on, its source becomes the ground potential level of the circuit. As mentioned above, in the non-selected state of the static RAM, the differential MO
The drain voltages of 3FETQI9 and Q21 are set to high level. For this reason, the differential MO3FETQ19/Q21
turns on at the same time as MO3F'ETQ22 turns on, and its drain voltage begins to drop.

At the same time, the gate voltages of MO3FETs Q38 and Q40 decrease, and these MO3FETs Q38 and Q40 are turned on. However, the parallel transmission gate MO3FE
Since the conductance changes of TQ18/Q39 and Q20/Q41 differ according to the read signal output from the memory cell MC, the differential MO3FET QI9 and Q2
The drain voltage of 1 will make a small difference according to the read signal. That is, when a read signal of logic "0" is output from the memory cell MC of the memory array M-ARYO, the conductance of the parallel transmission gate MO5FETQI 9 and Q39 is reduced, so that the corresponding differential MO3
The drain voltage of FET QI 9 drops rapidly. In addition, by increasing the conductance of MO3FETQ20/Q41 (parallel transmission game), the corresponding differential MO3FE
The drop in the train voltage of TQ21 is relatively small.

The level difference between
It is rapidly scaled up by the S inverter circuit. As a result, the drain voltage of the differential MO3FET Q21 becomes high level, the conductance of the MO3FET Q38 is decreased, and the conductance of the MO3FET QI 9 is increased. In addition, the drain voltage of the differential MO3FETQI9 becomes low level, and the MO3FETQ21
The conductance of MO3FETQ is also reduced.
40 has its conductance increased. As a result, the output signal of the inverter circuit N3, that is, the inverted output signal SDO of the sense amplifier SAO becomes a logic high level.
Further, the output signal of the inverter circuit N4, that is, the non-inverted output signal SDO of the sense amplifier SAO becomes a logic low level.

On the other hand, when a read signal of logic "1" is output from the memory cell MC of the memory array M-ARYO, the conductance of the parallel transmission gates MO3FETQ20 and Q41 is reduced, so that the drain voltage of the corresponding differential MO3FETQ21 rapidly increases. lowered and also parallel transmission gate MO
Since the conductance of 3FETQI8 and Q39 is large, the drop in drain voltage of the corresponding differential MO3FETQI9 is relatively small. This level difference is rapidly expanded by the two sets of CMOS inverter circuits that constitute the positive feedback amplifier circuit, and as a result, the differential MO3F
The drain voltage of ETQ21 becomes low level, and MO3
FETQI9 has its conductance reduced and MO3FETQ3B has its conductance increased. Further, the drain voltage of the differential i1JMo SF ETQ 19 becomes high level, the conductance of the MO3FETQ40 is decreased, and the conductance of the MO3FETQ21 is increased. Therefore, the output signal of the inverter circuit N3, ie, the inverted output signal SDO of the sense amplifier SAO, becomes a logic low level, and the output signal of the inverter circuit N4, ie, the non-inverted output signal SDO of the sense amplifier SAO, becomes a logic high level.

As described above, the sense amplifier SAO of this embodiment includes a parallel N-channel MO3FET and a P-channel MO3FET.
Two sets of parallel transmission gates constituted by O3FETs, each gate of which is coupled to a non-inverting signal line and an inverting signal line of a complementary common data line) MO3FETs QI 8, Q39 and Q20, Q41, and these parallel transmission gates 1-M03
Two sets of CMs are configured by an N-channel MO3FET and a P-channel MO3FET arranged in series so as to sandwich the FET, and their respective input terminals and output terminals are cross-connected to each other to constitute a positive feedback amplifier circuit.
Contains an OS inverter circuit. According to the read signal output from the memory cell MC, the parallel transmission gate MO3FE
The conductance of T is changed relatively quickly, and a level difference occurs in the output voltage of the CMOS inverter circuit according to this change in conductance. This level difference is rapidly expanded and amplified by these CMOS inverter circuits. Therefore, the read operation of the static RAM is faster than in the first embodiment described above. Also, CM
7) MOSF constituting the OS inverter circuit
Since the ETs are turned on in a complementary manner, their operating current is further reduced, and the power consumption of the static RAM is significantly reduced.

As in the case of the first embodiment, the complementary common data line CDO・σ
The level change of the line τ is transmitted to the sense amplifier SAO through the gate of the parallel transmission gate MOSFET, and the load on the complementary common data line CDO·σ11 is reduced. In addition, the drain voltages of the differential MO3FETs QI9 and Q21 are outputted via inverter circuits N3 and N4, respectively.
The load on the differential MO3FETs Q19 and Q21 is also reduced.

Therefore, the read operation of the static RAM can be made even faster.

[Embodiment 3] FIG. 3 shows a static type RA to which this invention is applied.
A circuit diagram of a third embodiment of M sense amplifier SAO is shown.

The sense amplifier SAO of this embodiment has a differential MO3FETQ24 (third MOSFET) whose gate and drain are cross-connected to each other to constitute a positive feedback amplifier circuit.
) and Q25 (fourth MOSFET). Between the drains of these differential MO3FETs and the circuit power supply voltage Vcc, there is an input MO3FET Q44 (the first MOSFET) and Q
45 (second MOSFET) is provided. In addition, between the commonly connected sources of the differential MO3FETs Q24 and Q25 and the ground potential of the circuit, there is an N-channel MO3FETQ2 whose gate receives the above-mentioned timing signal φsa.
7 is provided.

Furthermore, the differential MO3FETs Q24 and Q25 include N-channel MO3FETs Q23 whose gates are commonly connected to the input MO3FETs Q44 and Q45, respectively.
(11th MOSFET) and Q26 (12th MOS
FETs) are respectively provided in parallel configuration. These M
The drain voltages of the O3FETs Q23 and Q26, that is, the drain voltages of the differential MO3FETs Q24 and Q25, are inverted by inverter circuits N5 and N6, respectively, and the non-inverted signal line "4 S D O
and data output buffer D as the inverted output signal SDO.
Supplied to OBO.

In the non-selected state of the static RAM where the timing signal φsa is at a logic low level, MO3FETQ
27 is in the off state, and the differential MO3FETQ24・Q2
The sense amplifier SAO whose basic configuration is 5 is in a non-operating state. At this time, the complementary common data lines CDO and CDO are set to a half precharge level, as in the previous embodiment.

Therefore, the input MO3FETs Q44 and Q45 are turned on, and the drain voltages of the differential MO3FETs Q24 and Q25 are both at a high level such as the power supply voltage Vcc.

Next, when the static RAM is brought into a selected state and the timing signal φsa is set to a logic high level, the levels of the complementary common data lines CD0-CD0 are changed in accordance with the read signal output from the selected memory cell. Furthermore, the MO3FETQ27 of the sense amplifier SAO is turned on, and the ground potential of the circuit is supplied to the commonly connected drains of the differential M03FETQ24 and Q25. This allows the input MO3FETQ whose gates are commonly coupled
44 and Q23 and Q45 and Q26 are both in the on state, but their conductance is the same as that of the complementary common data line CD.
It changes according to the level of the read signal transmitted to 0-CD0. That is, when a read signal of logic "0" is output from the memory cell of the memory array M-ARYO, the level of the inverted signal line CDO of the complementary common data line becomes higher than the level of the non-inverted signal line. Therefore, the input M
The conductance of O3FETs Q44 and Q26 is increased, and the conductance of input MO3FETs Q45 and Q23 is decreased. Therefore, the differential MO3FE
The drain voltage of TQ24 is slightly higher than the voltage of differential MO3FETQ25.

On the other hand, when a read signal of logic "1" is output from the memory cells of the memory array M-ARYO, the level of the non-inverted signal line CDO of the complementary common data line becomes higher than the level of the inverted signal line. Therefore, the input MO3FETQ45
The conductance of Q23 and Q23 are increased, and the input M
The conductance of O3FETs Q44 and Q26 is reduced. Therefore, the drain voltage of differential MO3FETQ24.

The voltage becomes slightly lower than the voltage of the differential MO3FETQ25.

By the way, as described above, the drain voltages of the differential MO3FETs Q24 and Q2δ in the non-selected state of the static RAM, that is, the gate voltages thereof are set at a high level. Therefore, the static type RAM is set to the selected state and M
By turning on O5FETQ27, the differential MO3
FETs Q24 and Q25 are turned on at the same time, and their drain voltages begin to drop. However, the input MO3F
ETQ44. Q45. Since the conductance of Q23 and Q26 is changed according to the read signal transmitted to the complementary common data line CDO・ξ51, the differential MO3FETQ
A level difference occurs between the drain voltages of Q24 and Q25, that is, their gate voltages. That is, as described above, when the read signal of logic "0" is output from the memory cell Mc of the memory array M-ARY0, the differential MO3FETQ24
The drain voltage of is slightly higher than the voltage of the differential MO3FETQ25. This voltage difference causes the positive feedback amplifier circuit to
It is rapidly expanded by the constituent differential MO5FETs Q24 and Q25. As a result, 1 of differential MOSFETQ24
-The Reinoh voltage becomes high level, and MOS F E
The conductance of T Q 25 is increased. Also, differential! The drain voltage of AOS FETQ 25 becomes low level, and the conductance of MO3FETQ24 is reduced. Therefore, the output signal of the inverter circuit N5, that is, the non-inverted output signal SDO of the sense amplifier 5A (13) becomes a logic low level, and the output signal of the inverter circuit N6, that is, the inverted output signal of the sense amplifier SAO, becomes a logic high level.

On the other hand, when a read signal of logic "L" is output from the memory cell MC of the memory array M-ARYO, the differential MO
The drain voltage of 3FETQ24 is the differential MO3FETQ
The voltage will be slightly lower than that of 25. This voltage difference is the differential M
It is rapidly expanded by O3FETQ24 and Q25, and as a result, the drain voltage of differential MO3FETQ24 becomes low level, and the conductance of MO3FETQ25 is reduced. Further, the drain voltage of the differential MO3FETQ25 becomes high level, and the conductance of the MO3FETQ24 increases. Therefore, the output signal of the inverter circuit N5, ie, the non-inverted output signal SDO of the sense amplifier SAO, becomes a logic high level, and the output signal of the inverter circuit N6, ie, the inverted output signal io of the sense amplifier SAO, becomes a logic low level.

As described above, the sense amplifier SAO of this embodiment consists of a series-type N-channel MO3FET and a P-channel MO3FET.
Two sets of series human-powered MO3FETs Q44, Q23 and Q45 constituted by O3FETs and whose respective gates are coupled to the non-inverting signal line and the inverting signal line of the complementary common data line.
・Differential MO3 which configures a positive feedback amplifier circuit by connecting Q26 and N-channel MO3FETs Q23 and Q26 among these input MO3FETs in parallel and having their respective gates and drains cross-coupled with each other.
Includes FETQ24 and Q25. According to the read signal output from the memory cell MC, the conductance of the series input MO3FET is changed in a complementary manner, and a level difference is generated between the drain voltages of the differential MO3FETs Q24 and Q25 according to this change in conductance. This level difference is rapidly expanded by differential MO5FETQ24 and Q25.
Because of the amplification, the read operation of the static RAM becomes faster. Also, these series input MO3FE
Since the conductances of the T and differential MO3FETs are changed in a complementary manner, the operating current can be reduced and power consumption can be reduced. Also, as in the previous embodiments, level changes on the complementary common data lines CD0-CD0 are transmitted to the sense amplifier SAO via the gates of the input MO8FETs, reducing the load on the complementary common data lines CDO-CDO. Ru. Also, differential MO3FETQ24・Q
The drain voltages of 25 are outputted through inverter circuits N1 and N2, respectively, and are outputted to the differential MO3FETs Q24 and Q25.
The load on 25 is also reduced.

Therefore, the read operation of the static RAM can be made even faster.

(Embodiment 4) FIG. 4 shows a static type RA to which this invention is applied.
A circuit diagram of a fourth embodiment of M sense amplifier SAO is shown.

The sense amplifier SAO of this embodiment basically follows the circuit configuration of the conventional sense amplifier shown in FIG.
1 and Q46 to Q48 and the inverter circuit N7 respectively correspond to the MO3FETs Q32 to Q34 and Q50 to Q52 and the inverter circuit N8 of the sense amplifier SAO in FIG.

In Figure 4, the complementary common data line CDO/01 is N
It is coupled to the gates of channel type differential MO3FETs Q28 and Q29, respectively. Between the drains of the differential MO3FETs Q28 and Q29 and the circuit power supply voltage Vcc,
P-channel MO3FETs Q47 and Q48 are provided, respectively. These MO3FETs Q47 and Q48 have the gate and drain of the MO3FE748 connected in common and further connected in common to the gate of the MO3FET Q47, thereby forming a current mirror configuration and acting as an active load. Furthermore, the MO3FETQ47 has a P channel M which receives the above-mentioned timing signal φsa at its gate.
O3FETQ4G is provided in parallel configuration.

On the other hand, series N-channel MO3FETs Q30 and Q31 are provided between the commonly connected sources of the differential MO3FETs Q2B and Q29 and the ground potential of the circuit.

The gate of MO3FETQ30 is coupled to the non-inverted signal line CDO of the complementary common data line, and the timing signal φsa is supplied to the gate of MO3FETQ31. Furthermore, the drain voltage of the differential MO3FET Q28 is inverted by the inverter circuit N7, and the sense amplifier SA
The non-inverted output signal SDO of 0 is supplied to the data output sofa DOBO.

In the non-selected state of the static RAM where the timing signal φsa is at a logic low level, MO3FETQ
31 is turned off, and the sense amplifier SAO is rendered inactive. At this time, differential MO3FETQ28・Q2
Both drains of 9 are in a floating state, but M
Since the gate of O3FETQ48 is coupled to its drain, MO3FETQ48 is connected to MO3FETQ2.
! l) Drain voltage is power supply voltage Vcc - VTHP
(VTHP is the threshold voltage of MO3FETQ29). Further, by setting the timing signal φsa to a logic low level, the MO3FETQ46 is turned on, and the drain voltage of the differential MO3FETQ28 becomes a high level approximately equal to the power supply voltage Vcc. As a result, the output signal of the inverter circuit N7, that is, the non-inverted output signal SDO of this sense amplifier SAO becomes a logic low level.

Next, when the static RAM is brought into the selected state, the levels of the complementary common data lines CDO and CDO are changed in accordance with the read signal output from the selected memory cell. Further, by setting the timing signal φSa to a logic high level, the MOSFETQ31 is turned on, and the circuit ground potential is supplied to the sources of the differential MO3FETQ28 and Q29. As a result, the sense amplifier SA
O is in the operating state.

Logic “0” from memory cells of memory array MARYO
” is output, the level on the inverted signal line C00 of the complementary common data line is higher than the level on the non-inverted signal line CDO. Therefore, the differential MO3FET
The conductance of Q29 is increased, and conversely the differential MO3
The conductance of FETQ28 is reduced. As a result, the drain voltage of MO3FETQ29 decreases, and as the drain voltage of MO3FETQ29 decreases, the conductance of MO3FETQ48 is increased, and the conductance of MO3FETQ47 is also increased. Therefore, the I input voltage of the MOSFET Q28 becomes high level, and the output signal of the inverter circuit N7, that is, the non-inverted output signal SDO of this sense amplifier SAO becomes a logic low level. At this time, the conductance of the MO3FET Q30 whose gate is coupled to the non-inverted signal line CDO of the complementary common data line is reduced by lowering the level of the non-inverted signal line CDO, and as a result, the conductance of the MO3FET Q30 is Reduce the operating current flowing.

On the other hand, when a read signal of logic "1" is output from the memory cell of the memory array M-ARYO, the level of the inverted signal line CDO of the complementary common data line is equal to that of the non-inverted signal line CDO.
lower than the level of Therefore, the differential MO3FE
The conductance of TQ29 is reduced, and conversely, the differential MO
The conductance of 3FETQ28 is increased. This suppresses a drop in the drain voltage of MO3FETQ29, reduces the conductance of MO3FETQ48, and further reduces the conductance of MO3FETQ47. Therefore, the drain voltage of MO3FETQ28 becomes low level, and the output signal of inverter circuit N7, that is, the non-inverted output signal S of this sense amplifier SAO.
DO becomes a logic high level. At this time, MO3FE
Although the conductance of TQ28 is increased, the conductance of MO3FETQ47 coupled in series thereto is complementarily decreased. Also, MO3FETQ
The conductances of Q29 and Q48 are both reduced. Therefore, although the conductance of MO3FETQ30 is increased by increasing the level of the non-inverted signal line, the operating current of sense amplifier SAO is small.

As described above, the sense amplifier SAO of this embodiment has the same basic configuration as the conventional sense amplifier shown in FIG. Between them, a MO3FET Q30 is provided whose gate is coupled to the non-inverted signal line CDO of the complementary common data line. This MO8FETQ
30 is a logic “0” from the selected memory cell when the operating current of the sense amplifier SAO is about to increase.
” when the read signal is output, its conductance is reduced. Therefore, the differential MOS F
Even though the load on ET is an active load, the power consumption of the sense amplifier SAO is reduced, and it is possible to reduce the power consumption of the static RAM.

As shown in the first to fourth embodiments above, when the present invention is applied to a semiconductor memory device such as a static RAM that inputs/outputs stored data in parallel in units of 16 bits, the following will occur. Effects can be obtained. That is, (11 sense amplifiers include a pair of input MOSFETs whose gates are respectively coupled to a non-inverting signal line and an inverting signal line of the complementary common data line, and a pair of input MOSFETs connected in series to these input MOSFET pairs, respectively, and whose gates are connected to the non-inverting signal line and the inverting signal line of the complementary common data line, respectively. and drains are cross-coupled with each other to constitute a positive feedback amplifier circuit, and its conductance is the same as that of the input MOSFET.
By providing a differential MOSFET pair that changes complementary to the pair, it is possible to achieve the effect of speeding up the amplification operation of the sense amplifier and speeding up the readout operation of static type RA FA etc. .

(2) According to the above item (1), the operating current of the sense amplifier is suppressed, and the power consumption of a static type RAM or the like in which stored data is simultaneously input/output in units of 16 bits, for example, can be reduced in power consumption.

(3) In the above (paragraph 0), input MOS FET is connected to N channel N1oSFET and P channel MO3F.
By using a parallel transmission gate with ETs connected in parallel, it is possible to increase the change in the conductance of the input λ (O3FET), making the amplification operation of the sense amplifier faster and the readout operation of static RAM etc. faster. This has the effect of being able to be converted into

(4) In the above item (3), a P-channel MOS FET is provided in series with the differential MO3FET, and a CMOS inverter circuit consisting of these MOS FETs is cross-connected to form a positive feedback amplifier circuit. Therefore, it is possible to achieve the effect that the amplification operation of the sense amplifier circuit can be made faster, and the read operation of a static type RAM or the like can be made faster.

(5) In item (1) above, the input MO3FET is configured with a P-channel inter-channel O3FET and an N-channel MO3FET in series, and the conductance of the input MO3FET is changed complementarily to further increase the operating current of the sense amplifier. This has the effect of reducing the power consumption of a semiconductor memory device such as a static RAM.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (it is understood that various changes can be made without departing from the gist of the invention). Needless to say, for example, in the sense amplifiers shown in FIGS. 1 to 3, the differential MO3FET may be configured by a P-channel O3FET.

In this case, the input MO3FET is provided between the differential MO3FET and the ground potential of the circuit, and the MOS for supplying operating current is
The FET must be placed between the differential MO3FET and the circuit power supply voltage Vcc. It is also possible to provide equalization between the output nodes of each sense amplifier, that is, between the input terminals of the two output inharter circuits, by providing a MOSFET that is selectively turned on when the static RAM is not selected. The output inverter circuits in FIGS. 1 to 4 may be logic gate circuits powered by two or more people,
It may also be a clocked inverter circuit. Furthermore, the block configuration of the static RAM shown in FIG. 5, the combination of control signals, etc. can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly applied to CMOS static type RAM, which is the background field of application, but it is not limited thereto.
It can also be applied to M and other semiconductor memory devices. The present invention is widely applicable to semiconductor memory devices having at least a sense amplifier or a main amplifier coupled to a complementary common data line.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the sense amplifier includes a pair of input MOSFETs whose gates are respectively coupled to a non-inverting signal line and an inverting signal line of the complementary common data line, and these input MOSFETs.
A positive feedback amplifier circuit is constructed by providing T pairs in series and having their gates and drains cross-coupled with each other, and whose conductance is the input MO3FE1.
By providing a differential MOSFET pair that changes complementary to the pair, it is possible to speed up the amplification operation of the sense amplifier and suppress its operating current. This makes it possible to speed up the read operation and reduce power consumption of type RAM and the like.

[Brief Description of the Drawings] Figure 1 shows a static RAM to which this invention is applied.
A circuit diagram showing an embodiment of the sense amplifier circuit of FIG.
A circuit diagram showing a second embodiment of the sense amplifier circuit, FIG. 3 is a static RAM to which the present invention is applied.
A circuit diagram showing a third embodiment of the sense amplifier circuit of FIG. 4 is a static type RA to which the present invention is applied.
A circuit diagram showing a fourth embodiment of the M sense amplifier circuit, FIG. 5 is a static type RA to which the present invention is applied.
FIG. 6 is a circuit block diagram showing one embodiment of M. FIG. 6 is a circuit diagram showing an example of a sense amplifier circuit of a conventional static type RAM. SAO...Sense amplifier, M-ARYO...Memory array, MC...Memory cell, C3WO...Column switch. Q1~Q34-...N channel MO3FET. Q35~Q52...P channel MO3FET. N l ” N 8...Inverter circuit, R1-R2
···resistance. XDCR・--X at L/S decoder, YDCR...
Y address decoder, XADB...X address buffer, YADB...Y address buffer, DOBO...
・Data output cover sofa, WAO... light amplifier, D
IBO...data input cover sofa, TC...timing control circuit.

Claims (1)

[Claims] 1. First and second MOSs whose gates are respectively coupled to a non-inverting signal line and an inverting signal line of the complementary common data line;
A semiconductor memory device comprising an amplifier circuit including a FET, and third and fourth MOSFETs which are provided in series with the first and second MOSFETs, respectively, and whose gates and drains are cross-coupled to each other. . 2. The first and second MOSFETs have gates coupled to an inverted signal line and a non-inverted signal line of the complementary common data line, respectively, and have a conductivity type different from that of the first and second MOSFETs. 2. The semiconductor memory device according to claim 1, wherein the fifth and sixth MOSFETs are each provided in parallel. 3. The third and fourth MOSFETs have seventh and fourth MOSFETs whose gates are commonly coupled to the gates of the third and fourth MOSFETs, respectively, and whose conductivity type is different from that of the third and fourth MOSFETs. An eighth MOSFET is provided in series so as to sandwich the first or second MOSFET, and between the drains of the third and fourth MOSFETs and the power supply voltage or ground potential of the circuit is connected to the amplifier circuit. 3. The semiconductor memory device according to claim 1, further comprising ninth and tenth MOSFETs that are turned on in a non-operating state. 4. The third and fourth MOSFETs include eleventh and fourth MOSFETs whose gates are commonly coupled to the gates of the first and second MOSFETs, respectively, and whose conductivity type is the same as that of the third and fourth MOSFETs. 2. The semiconductor memory device according to claim 1, wherein each of the twelve MOSFETs is provided in parallel. 5. A thirteenth MOSFET that is turned on in the operating state of the amplifier circuit is provided between the commonly connected sources of the third and fourth MOSFETs and the ground potential or power supply voltage of the circuit. A semiconductor memory device according to claim 1, 2, 3, or 4, characterized in that: 6. The drains of the third and fourth MOSFETs have:
The semiconductor memory device according to claim 1, 2, 3, 4, or 5, wherein the input terminals of the output inverter circuit are respectively coupled. 7. The above semiconductor memory device is a CMOS static type R
The semiconductor memory device according to claim 1, 2, 3, 4, 5, or 6, which is an AM.