JPS63196970A

JPS63196970A - Microcomputer

Info

Publication number: JPS63196970A
Application number: JP62028607A
Authority: JP
Inventors: Masatoshi Aikawa; 相川　雅俊
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1987-02-10
Filing date: 1987-02-10
Publication date: 1988-08-15

Abstract

PURPOSE:To remove a test exclusive terminal, and to simplify the constitution by controlling directly an address bus control circuit by a CPU so that a direct memory access can be executed, at the time of testing. CONSTITUTION:At the time of normal operating, a memory 1 is operated, based on an address and a control signal outputted through an address bus 2 from a CPU 11. Also, this microcomputer is constituted so that an address bus control circuit 10 can be controlled directly by the CPU 11, at the time of testing. That is, on the same chip, the memory 1, the address bus 2 and the circuit 10 for controlling the bus 2 are provided, and an address from an address bus terminal 3 can be transferred directly to the memory 1. In such a state, when an instruction exists at the time of testing, the circuit 10 is controlled directly by the CPU 11, and this circuit 10 is turned on and a direct memory access is executed. In such a way, a test exclusive terminal is made unnecessary and the constitution can be simplified.

Description

【発明の詳細な説明】〔産業上の利用分野〕この発明は、シングルチップマイクロコンピュータに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a single-chip microcomputer.

（従来の技術）第３図は従来のマイクロコンピュータを示す。(Conventional technology) FIG. 3 shows a conventional microcomputer.

図において、１はメモリ（データ格納手段）、２はこの
メモリ１にアドレスバス端子３および後述するＣＰＵ　
９からのアドレスを転送するアドレスバス、４はこのア
ドレスバスをテスト専用端子５からの１３号に基づき制
御するアドレスバス１１御回路、６は前記メモリ１のデ
ータ書き込み、読み出し用制御端子（Ｒ／Ｗ制御端子）
、７は前記メモリ１にデータバス端子８と後述する（：
ＰＵ　９からのデータを転送するデータバス、９はアド
レスと制御信号に基づき前記メそす１にデータの書き込
みあるいは読み出しを行なうＣＰＵである。In the figure, 1 is a memory (data storage means), and 2 is a memory 1 connected to an address bus terminal 3 and a CPU (described later).
4 is an address bus 11 control circuit that controls this address bus based on No. 13 from the test-only terminal 5; 6 is a control terminal for data writing and reading of the memory 1 (R/ W control terminal)
, 7 are connected to the memory 1 as a data bus terminal 8, which will be described later (:
A data bus 9 transfers data from the PU 9, and a CPU 9 writes data to or reads data from the memory 1 based on an address and a control signal.

従来のマイクロコンピュータは、上記のように＃１ＩＪ
ＩＡシたから、通常動作時は、ＣＰｔ１９により、ＣＰ
Ｕ　９からのアドレスと制御信号に基づきメモリ１が動
作される。一方、テスト時は、テスト専用端子５からア
ドレスバス制御回路４に所定の信号を入力すると、制御
回路４によりアドレスバス２が解放される。そして、ア
ドレスバス端子３からアドレスをメモリ１に直接入力す
ると、入力されたアドレスに相当するメモリｌ上のアド
レスにデータが書き込まれ、またはメモリ１十のアドレ
スからデータが読み出される。The conventional microcomputer is #1IJ as mentioned above.
Because of the IA, during normal operation, CPt19
Memory 1 is operated based on the address and control signals from U9. On the other hand, during testing, when a predetermined signal is input from the test-dedicated terminal 5 to the address bus control circuit 4, the address bus 2 is released by the control circuit 4. When an address is directly input to the memory 1 from the address bus terminal 3, data is written to the address on the memory 1 corresponding to the input address, or data is read from the address of the memory 10.

（発明が解決しようとする問題点）従来のマイクロコンピュータは、テスト時、テスト専用
端子５からの信号に基づきアドレスバス制御回路４を制
御する構成にしたから、通常動作時に不必要なテスト専
用端子５を設けなければならないという問題点があった
。(Problems to be Solved by the Invention) Conventional microcomputers are configured to control the address bus control circuit 4 based on signals from the test-dedicated terminal 5 during testing, so the test-dedicated terminal is unnecessary during normal operation. There was a problem that 5 had to be provided.

この発明は、上記のような問題点を解決するためになさ
れたもので、テスト専用端子を除去したマイクロコンピ
ュータを得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a microcomputer in which test-only terminals are removed.

（問題点を解決るするための手段）この発明に係るマイクロコンピュータは、同一チップ上
に、データ格納手段と、これにアドレスバス端子からの
アドレスを転送するアドレスバスと、このアドレスバス
を制御するアドレスバス制御手段と、これを制御する制
御手段とを設けたものである。(Means for Solving the Problems) A microcomputer according to the present invention includes, on the same chip, a data storage means, an address bus for transferring an address from an address bus terminal to the data storage means, and a control unit for controlling this address bus. This device is provided with an address bus control means and a control means for controlling the address bus control means.

（作用）この発明における制御手段は、アドレスバス制御手段を
制御し、アドレスバス端子からのアドレスをデータ格納
手段に直接転送することを可能にする。(Function) The control means in the present invention controls the address bus control means and makes it possible to directly transfer the address from the address bus terminal to the data storage means.

（実施例）第１図はこの発明の一実施例を示す。図において、ｌ〜
３．６〜８は第２図と同一部分を示す。(Embodiment) FIG. 1 shows an embodiment of the present invention. In the figure, l~
3.6 to 8 show the same parts as in FIG.

ｌＯは前記アドレスバス２を制御するアドレスバス制御
回路（アドレスバス制御手段）、１１はこのアドレスバ
ス制御回路１０を制御するＣＰＵ　（制御手段）である
。10 is an address bus control circuit (address bus control means) that controls the address bus 2, and 11 is a CPU (control means) that controls this address bus control circuit 10.

この実施例と従来例とが相違する点は、ＣＰＵ　１１に
よりアドレスバス制御回路ｌＯを直接制御できるように
した点であり、テスト時、命令があると（ＳＴＥＰ−１
）、ＣＰＵ　１１により直接アドレスバス制御回路１０
が制御され、このアドレスバス制御回路１０がＯＮされ
（ＳＴＥＰ−２）、ＤＭＡ（ｄｉｒｅｃｔ　ｍｅ＋＊ｏ
ｒｙ　ａｃｃｅｓｓ）が可能になる（ＳＴＥＰ−３）。The difference between this embodiment and the conventional example is that the address bus control circuit IO can be directly controlled by the CPU 11, and when there is an instruction during testing (STEP-1
), the address bus control circuit 10 directly by the CPU 11
is controlled, this address bus control circuit 10 is turned on (STEP-2), and the DMA (direct me+*o
ry access) becomes possible (STEP-3).

（発明の効果）以上のように、この発明によれば、テスト時、１１Ｊａ
手段によりアドレスバス制御手段を直接−制御する構成
にしたので、テスト専用端子を除去できるという効果あ
る。(Effects of the Invention) As described above, according to the present invention, at the time of testing, 11Ja
Since the address bus control means is directly controlled by the means, there is an effect that a test-dedicated terminal can be eliminated.

[Brief explanation of the drawing]

第１図はこの発明の一実施例を示す要部ブロック図、第
２図は動作フローチャート、第３図は従来のマイクロコ
ンピュータの要部ブロック図である。図において、１はメモリ、２はアドレスバス、３はアド
レスバス端子、１０はアドレスバス制御回路、１１はｃ
ｐυである。なお、図中、同一符号は同一または相当部分を示す。FIG. 1 is a block diagram of main parts showing an embodiment of the present invention, FIG. 2 is a flowchart of operation, and FIG. 3 is a block diagram of main parts of a conventional microcomputer. In the figure, 1 is a memory, 2 is an address bus, 3 is an address bus terminal, 10 is an address bus control circuit, and 11 is a c
It is pυ. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Claims]

The present invention is characterized by comprising, on the same chip, a data storage means, an address bus for transferring an address from an address bus terminal to the data storage means, an address bus control means for controlling the address bus, and a control means for controlling the same. microcomputer.